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| document number: 313056-003 intel ? i/o controller hub 8 (ich8) family datasheet ? for the intel ? 82801hb ich8, 82801hr ich8r, 82801hdh ich8dh, 82801hdo ich8do, 82801hbm ich8m, and 82801hem ich8m-e i/o controller hubs may 2007
2 intel ? ich8 family datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by th is document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a par ticular purpose, merchantability, or infringement of any patent, copyright or ot her intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no respon sibility whatsoever for conf licts or incompatibilities arising from future changes to them. the intel ? i/o controller hub 8 (ich8) family chipset component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and be fore placing your product o rder. i 2 c is a two-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, in cluding philips electronics n.v. and north american philips corporation. intel ? active management technology requires the platform have an intel ? amt-enabled chipset and network hardware and software, be plugged into a power source, and have a network connection. alert on lan is a result of the intel-ibm advanc ed manageability alliance and a trademark of ibm. intel, intel speedstep and the intel logo are trademarks of intel corporation in the u.s. and other countries. *other names and brands may be claimed as the property of others. copyright ? 2006?2007, intel corporation intel ? ich8 family datasheet 3 contents 1 introduction .................................................................................................... ........ 45 1.1 overview ......................................................................................... ................ 48 1.2 intel ? ich8 family high-level component differences ........................................... 55 2 signal description ................................................................................................... 5 7 2.1 direct media interface (dmi) to host controller .................................................. ... 60 2.2 pci express* ..................................................................................... ............... 60 2.3 lan connect interface ............................................................................ ........... 61 2.4 gigabit lan connect interface .................................................................... ........ 61 2.5 firmware hub interface........................................................................... ........... 62 2.6 pci interface .................................................................................... ................ 63 2.7 serial ata interface............................................................................. .............. 66 2.8 ide interface (mobile only) ...................................................................... .......... 68 2.9 lpc interface .................................................................................... ................ 69 2.10 interrupt interface ............................................................................. ............... 70 2.11 usb interface ................................................................................... ................ 71 2.12 power management interface...................................................................... ........ 72 2.13 processor interface............................................................................. ............... 75 2.14 smbus interface................................................................................. ............... 77 2.15 system management interface ..................................................................... ....... 77 2.16 real time clock interface ....................................................................... ............ 78 2.17 other clocks .................................................................................... ................. 79 2.18 miscellaneous signals ........................................................................... ............. 79 2.19 intel ? high definition audio link ......................................................................... 80 2.20 serial peripheral interface (spi) ............................................................... ........... 81 2.21 intel ? quick resume technology (intel ? ich8dh only) ......................................... 82 2.22 controller link ................................................................................. ................. 82 2.23 intel ? quiet system technology (desktop only) ................................................... 83 2.24 general purpose i/o signals ..................................................................... .......... 83 2.25 power and ground ................................................................................ ............. 86 2.26 pin straps ...................................................................................... .................. 88 2.26.1 functional straps ............................................................................. ...... 88 2.26.2 external rtc circuitry ........................................................................ ..... 90 3 intel ? ich8 pin states ............................................................................................. 91 3.1 integrated pull-ups and pull-downs ............................................................... ...... 91 3.2 ide integrated series termination resistors (m obile only)...................................... 92 3.3 output and i/o signals planes and states......................................................... .... 92 3.4 power planes for input signals ................................................................... ....... 102 4 intel ? ich8 and system clock domains ................................................................. 107 5 functional description ........................................................................................... 109 5.1 pci-to-pci bridge (d30:f0) ....................................................................... ....... 109 5.1.1 pci bus interface .............................................................................. ... 109 5.1.2 pci bridge as an initiator ..................................................................... . 109 5.1.2.1 memory reads and writes........................................................ 110 5.1.2.2 configuration reads and writes ................................................ 110 5.1.2.3 locked cycles ........................................................................ 110 5.1.2.4 target / master aborts............................................................. 110 5.1.2.5 secondary master latency timer............................................... 110 5.1.2.6 dual address cycle (dac) ........................................................ 110 5.1.2.7 memory and i/o decode to pci................................................. 111 5.1.3 parity error detection and generation ..................................................... 111 4 intel ? ich8 family datasheet 5.1.4 pcirst# ........................................................................................ ..... 111 5.1.5 peer cycles .................................................................................... ...... 112 5.1.6 pci-to-pci bridge model ........................................................................ 112 5.1.7 idsel to device number mapping ........................................................... 112 5.1.8 standard pci bus configuration mechanism.............................................. 113 5.2 pci express* root ports (d28:f0,f1,f2,f3,f4,f5) ................................................ 11 3 5.2.1 interrupt generation ........................................................................... .. 113 5.2.2 power management............................................................................... 114 5.2.2.1 s3/s4/s5 support ................................................................... 114 5.2.2.2 resuming from suspended state ............................................... 114 5.2.2.3 device initiated pm_pme message ............................................. 114 5.2.2.4 smi/sci generation................................................................. 115 5.2.3 serr# generation ............................................................................... . 115 5.2.4 hot-plug ....................................................................................... ....... 115 5.2.4.1 presence detection .................................................................. 115 5.2.4.2 message generation ................................................................ 116 5.2.4.3 attention button detection ....................................................... 116 5.2.4.4 smi/sci generation................................................................. 117 5.3 gigabit ethernet controller (b0:d25:f0) .......................................................... ... 118 5.3.1 gbe pci bus interface .......................................................................... . 118 5.3.1.1 transaction layer.................................................................... 118 5.3.1.2 data alignment ....................................................................... 118 5.3.1.3 configuration request retry status ........................................... 119 5.3.2 error events and error reporting ............................................................ 119 5.3.2.1 data parity error ..................................................................... 119 5.3.2.2 completion with unsuccessful completion status ......................... 119 5.3.3 ethernet interface ............................................................................. ... 119 5.3.3.1 mac/lan connect interface ...................................................... 119 5.3.4 pci power management ......................................................................... 12 0 5.3.4.1 wake-up................................................................................ 120 5.3.5 configurable leds.............................................................................. ... 122 5.3.6 intel ? auto connect battery saver (mobile only) ...................................... 122 5.3.6.1 partial and full power down options .......................................... 123 5.3.6.2 intel ? acbs signal configurations ............................................. 123 5.4 lpc bridge (w/ system and management functi ons) (d31:f0) ............................... 124 5.4.1 lpc interface .................................................................................. ..... 124 5.4.1.1 lpc cycle types ...................................................................... 125 5.4.1.2 start field definition .................. .............................................. 125 5.4.1.3 cycle type / direction (cyctype + dir)..................................... 126 5.4.1.4 size....................................................................................... 12 6 5.4.1.5 sync ..................................................................................... 127 5.4.1.6 sync time-out ....................................................................... 127 5.4.1.7 sync error indication .............................................................. 127 5.4.1.8 lframe# usage...................................................................... 127 5.4.1.9 i/o cycles .............................................................................. 128 5.4.1.10 bus master cycles ................................................................... 128 5.4.1.11 lpc power management ........................................................... 128 5.4.1.12 configuration and intel ? ich8 implications................................. 128 5.5 dma operation (d31:f0) ........................................................................... ....... 129 5.5.1 channel priority............................................................................... ..... 129 5.5.1.1 fixed priority .......................................................................... 130 5.5.1.2 rotating priority ...................................................................... 130 5.5.2 address compatibility mode .... ............ ........... ........... ............ ........... ...... 130 5.5.3 summary of dma transfer sizes ............................................................. 131 5.5.3.1 address shifting when programmed for 16-bit i/o count by words ...................................................................... 131 5.5.4 autoinitialize ................................................................................. ....... 131 intel ? ich8 family datasheet 5 5.5.5 software commands............................................................................. 1 32 5.6 lpc dma .......................................................................................... .............. 132 5.6.1 asserting dma requests........................................................................ 1 32 5.6.2 abandoning dma requests .................................................................... 133 5.6.3 general flow of dma transfers............................................................... 133 5.6.4 terminal count ................................................................................. ... 133 5.6.5 verify mode .................................................................................... ..... 134 5.6.6 dma request deassertion...................................................................... 13 4 5.6.7 sync field / ldrq# rules ..................................................................... 13 5 5.7 8254 timers (d31:f0) ............................................................................. ........ 135 5.7.1 timer programming .............................................................................. 136 5.7.2 reading from the interval timer............................................................. 137 5.7.2.1 simple read........................................................................... 137 5.7.2.2 counter latch command.......................................................... 137 5.7.2.3 read back command .............................................................. 138 5.8 8259 interrupt controllers (pic) (d31:f0) ........................................................ .. 139 5.8.1 interrupt handling ............................................................................. ... 140 5.8.1.1 generating interrupts.............................................................. 140 5.8.1.2 acknowledging interrupts ........................................................ 140 5.8.1.3 hardware/software interrupt sequence ..................................... 141 5.8.2 initialization command words (icwx) ......... ............................................ 141 5.8.2.1 icw1 .................................................................................... 141 5.8.2.2 icw2 .................................................................................... 142 5.8.2.3 icw3 .................................................................................... 142 5.8.2.4 icw4 .................................................................................... 142 5.8.3 operation command words (ocw) ......................................................... 142 5.8.4 modes of operation ............................................................................. . 143 5.8.4.1 fully nested mode................................................................... 143 5.8.4.2 special fully-nested mode........................................................ 143 5.8.4.3 automatic rotation mode (equal priority devices)........................ 143 5.8.4.4 specific rotation mode (specific prio rity).................................... 143 5.8.4.5 poll mode ............................................................................... 144 5.8.4.6 cascade mode ........................................................................ 144 5.8.4.7 edge and level triggered mode ................................................ 144 5.8.4.8 end of interrupt (eoi) operations ............................................. 144 5.8.4.9 normal end of interrupt........................................................... 144 5.8.4.10 automatic end of interrupt mode .............................................. 145 5.8.5 masking interrupts ............................................................................. .. 145 5.8.5.1 masking on an individual interrupt request ................................ 145 5.8.5.2 special mask mode .................................................................. 145 5.8.6 steering pci interrupts ........................................................................ . 145 5.9 advanced programmable interrupt controller (apic) (d31:f0) .............................. 146 5.9.1 interrupt handling ............................................................................. ... 146 5.9.2 interrupt mapping .............................................................................. .. 146 5.9.3 pci / pci express* message-based interrupts .......................................... 147 5.9.4 front side bus interrupt delivery ........................................................... 147 5.9.4.1 edge-triggered operation ........................................................ 148 5.9.4.2 level-triggered operation........................................................ 148 5.9.4.3 registers associated with front side bus interrupt delivery .......... 148 5.9.4.4 interrupt message format........................................................ 148 5.10 serial interrupt (d31:f0) ....................................................................... .......... 149 5.10.1 start frame ................................................................................... ...... 149 5.10.2 data frames................................................................................... ..... 150 5.10.3 stop frame .................................................................................... ..... 150 5.10.4 specific interrupts not supported via serirq .......................................... 150 5.10.5 data frame format ............................................................................. . 151 6 intel ? ich8 family datasheet 5.11 real time clock (d31:f0) ........................................................................ ......... 152 5.11.1 update cycles ................................................................................. ..... 152 5.11.2 interrupts .................................................................................... ........ 153 5.11.3 lockable ram ranges........................................................................... . 153 5.11.4 century rollover.............................................................................. ..... 153 5.11.5 clearing battery-backed rtc ram........................................................... 153 5.12 processor interface (d31:f0) .................................................................... ........ 155 5.12.1 processor interface signals ................................................................... . 155 5.12.1.1 a20m# (mask a20).................................................................. 155 5.12.1.2 init# (initialization)................................................................ 156 5.12.1.3 ferr#/ignne# (numeric coprocessor error/ ignore numeric error)........................................................................ 157 5.12.1.4 nmi (non-maskable interrupt) .................................................. 157 5.12.1.5 stop clock request and cpu sleep (stpclk# and cpuslp#) ......................................................... 157 5.12.1.6 cpu power good (cpupwrgood) ............................................. 157 5.12.1.7 deeper sleep (dpslp#) (mobile only)........................................ 158 5.12.2 dual-processor issues (desktop only) ..................................................... 158 5.12.2.1 signal differences ................................................................... 158 5.12.2.2 power management ................................................................. 158 5.13 power management (d31:f0) ....................................................................... ..... 159 5.13.1 features ...................................................................................... ........ 159 5.13.2 intel ? ich8 and system power states ..................................................... 160 5.13.3 system power planes ........................................................................... . 162 5.13.4 smi#/sci generation ........................................................................... . 162 5.13.4.1 pci express* sci .................................................................... 165 5.13.4.2 pci express* hot-plug ............................................................. 165 5.13.5 dynamic processor clock control .............. .............................................. 165 5.13.5.1 slow c4 exit (mobile only) ....................................................... 166 5.13.5.2 transition rules among s0/cx and throttling states .................... 167 5.13.5.3 deferred c3/c4 (mobile only) ................................................... 167 5.13.5.4 popup (auto c3/c4 to c2) (mobile only) .................................... 167 5.13.5.5 popdown (auto c2 to c3/c4) (mobile only)............................... 168 5.13.6 dynamic pci clock control (mobile only) ................................................. 168 5.13.6.1 conditions for checking the pci clock ........................................ 168 5.13.6.2 conditions for maintaining the pci clock..................................... 168 5.13.6.3 conditions for stopping the pci cloc k ........................................ 168 5.13.6.4 conditions for re-starting the pci clock ..................................... 169 5.13.6.5 lpc devices and clkrun# ....................................................... 169 5.13.7 sleep states .................................................................................. ...... 169 5.13.7.1 sleep state overview............................................................... 169 5.13.7.2 initiating sleep state ............................................................... 169 5.13.7.3 exiting sleep states................................................................. 170 5.13.7.4 pci express* wake# signal and pme event message ................... 172 5.13.7.5 sx-g3-sx, handling power failures ............................................ 172 5.13.8 thermal management............................................................................ 173 5.13.8.1 thrm# signal......................................................................... 173 5.13.8.2 software initiated passive cooling ............................................. 173 5.13.8.3 thrm# override software bit ................................................... 173 5.13.8.4 active cooling......................................................................... 173 5.13.9 event input signals and their usage ....................................................... 174 5.13.9.1 pwrbtn# (power button) ........................................................ 174 5.13.9.2 ri# (ring indicator) ................................................................ 175 5.13.9.3 pme# (pci power management event) ....................................... 175 5.13.9.4 sys_reset# signal ................................................................ 175 5.13.9.5 thrmtrip# signal .................................................................. 176 5.13.9.6 bmbusy# (mobile only) ........................................................... 176 intel ? ich8 family datasheet 7 5.13.10alt access mode.............................................................................. .... 177 5.13.10.1write only registers with read paths in alt access mode .......................................................................... 177 5.13.10.2pic reserved bits ................................................................... 179 5.13.10.3read only registers with write paths in alt access mode .......................................................................... 180 5.13.11system power supplies, planes, and signals ............................................ 180 5.13.11.1power plane control with slp_s3#, slp_s4#, slp_s5# and slp_m# ............................................................. 180 5.13.11.2slp_s4# and suspend-to-ram sequencing ............................... 181 5.13.11.3pwrok signal ........................................................................ 181 5.13.11.4cpupwrgd signal .................................................................. 181 5.13.11.5vrmpwrgd signal .................................................................. 181 5.13.11.6batlow# (battery low) (mobile only) ...................................... 182 5.13.11.7controlling leakag e and power consumption during low-power states ......................................................... 182 5.13.12clock generators............................................................................. ..... 182 5.13.12.1clock control signals from intel ? ich8 to clock synthesizer (mobile only) ........................................................ 183 5.13.13legacy power management theory of operation ....................................... 183 5.13.13.1apm power management (desktop only) .................................... 183 5.13.13.2mobile apm power management (mobile only) ............................ 183 5.14 system management (d31:f0)...................................................................... .... 184 5.14.1 theory of operation........................................................................... ... 184 5.14.1.1 detecting a system lockup ...................................................... 184 5.14.1.2 handling an intruder ............................................................... 184 5.14.1.3 detecting improper firmware hub programming ......................... 185 5.14.2 tco modes ..................................................................................... ..... 185 5.14.2.1 tco legacy/compatible mode .................................................. 185 5.14.2.2 advanced tco mode ............................................................... 187 5.14.2.3 advanced tco bmc mode ........................................................ 187 5.15 ide controller (d31:f1) (mobile only)........................................................... ..... 189 5.15.1 pio transfers ................................................................................. ..... 189 5.15.1.1 pio ide timing modes ............................................................. 189 5.15.1.2 iordy masking....................................................................... 190 5.15.1.3 pio 32-bit ide data port accesses ............................................ 190 5.15.1.4 pio ide data port prefetching and posting ................................. 190 5.15.2 bus master function ........................................................................... .. 191 5.15.2.1 physical region descriptor format ............................................ 191 5.15.2.2 bus master ide timings ........................................................... 192 5.15.2.3 interrupts .............................................................................. 192 5.15.2.4 bus master ide operation ........................................................ 192 5.15.2.5 error conditions...................................................................... 193 5.15.3 ultra ata/100/66/33 protocol ................................................................ 19 4 5.15.3.1 operation .............................................................................. 194 5.15.4 ultra ata/33/66/100 timing .................................................................. 19 5 5.15.5 ata swap bay .................................................................................. ... 195 5.15.6 smi trapping .................................................................................. ..... 195 5.16 sata host controller (d31:f2, f5) ............................................................... ..... 196 5.16.1 theory of operation........................................................................... ... 197 5.16.1.1 standard ata emulation .......................................................... 197 5.16.1.2 48-bit lba operation............................................................... 197 5.16.2 sata swap bay support ....................................................................... 19 8 5.16.3 intel ? matrix storage technology configuration (intel ? ich8r, ich8dh, ich8do, and ich8m-e only) .................................................... 198 5.16.3.1 intel ? matrix storage manager raid option rom........................ 199 5.16.4 power management operation................................................................ 199 8 intel ? ich8 family datasheet 5.16.4.1 power state mappings.............................................................. 199 5.16.4.2 power state transitions............................................................ 200 5.16.4.3 smi trapping (apm)................................................................. 201 5.16.5 sata led ...................................................................................... ...... 201 5.16.6 ahci operation ................................................................................ .... 201 5.16.7 serial ata reference clock low power request (sataclkreq#) ................ 202 5.16.8 sgpio signals ................................................................................. ..... 202 5.16.9 external sata (intel ? ich8r, ich8dh, and ich8do only) ......................... 202 5.17 high precision event timers ..................................................................... ......... 203 5.17.1 timer accuracy ................................................................................ .... 203 5.17.2 interrupt mapping............................................................................. .... 203 5.17.3 periodic vs. non-periodic modes .............. ................................................ 204 5.17.4 enabling the timers ........................................................................... ... 204 5.17.5 interrupt levels.............................................................................. ...... 205 5.17.6 handling interrupts ........................................................................... .... 205 5.17.7 issues related to 64-bit timers with 32 -bit processors .............................. 205 5.18 usb uhci host controllers (d29:f0, f1, f2 and d26:f0, f1) ................................. 206 5.18.1 data structures in main memory ............................................................. 206 5.18.2 data transfers to/from main memory ...................................................... 206 5.18.3 data encoding and bit stuffing ............................................................... 2 06 5.18.4 bus protocol.................................................................................. ....... 206 5.18.4.1 bit ordering............................................................................ 206 5.18.4.2 sync field ............................................................................. 206 5.18.4.3 packet field formats................................................................ 206 5.18.4.4 address fields......................................................................... 207 5.18.4.5 frame number field ................................................................ 207 5.18.4.6 data field .............................................................................. 207 5.18.4.7 cyclic redundancy check (crc) ................................................ 207 5.18.5 packet formats ................................................................................ .... 207 5.18.6 usb interrupts ................................................................................ ..... 207 5.18.6.1 transaction-based interrupts .................................................... 207 5.18.6.2 non-transaction based interrupts ............................................. 209 5.18.7 usb power management ........................................................................ 21 0 5.18.8 usb legacy keyboard operation ............................................................. 210 5.19 usb ehci host controllers (d29:f7 and d26:f7) ................................................. 21 3 5.19.1 ehc initialization ............................................................................ ...... 213 5.19.1.1 bios initialization ................................................................... 213 5.19.1.2 driver initialization .................................................................. 213 5.19.1.3 ehc resets ............................................................................ 214 5.19.2 data structures in main memory ............................................................. 214 5.19.3 usb 2.0 enhanced host controller dma ................................................... 214 5.19.4 data encoding and bit stuffing ............................................................... 2 14 5.19.5 packet formats ................................................................................ .... 214 5.19.6 usb 2.0 interrupts and error conditions .................................................. 215 5.19.6.1 aborts on usb 2.0-initiated memory reads................................. 215 5.19.7 usb 2.0 power management .................................................................. 216 5.19.7.1 usb pre-fetch pause feature .................................................... 216 5.19.7.2 suspend feature ..................................................................... 216 5.19.7.3 acpi device states .................................................................. 216 5.19.7.4 acpi system states................................................................. 217 5.19.7.5 mobile considerations .............................................................. 217 5.19.8 interaction with uhci host controllers..................................................... 217 5.19.8.1 port-routing logic ................................................................... 217 5.19.8.2 device connects ..................................................................... 218 5.19.8.3 device disconnects.................................................................. 219 5.19.8.4 effect of resets on port-routing lo gic ........................................ 219 intel ? ich8 family datasheet 9 5.19.9 usb 2.0 legacy keyboard operation ....................................................... 219 5.19.10usb 2.0 based debug port .................................................................... 2 20 5.19.10.1 theory of operation ............................................................... 220 5.20 smbus controller (d31:f3) ....................................................................... ........ 225 5.20.1 host controller............................................................................... ...... 225 5.20.1.1 command protocols ................................................................ 226 5.20.2 bus arbitration............................................................................... ...... 229 5.20.3 bus timing .................................................................................... ...... 230 5.20.3.1 clock stretching ..................................................................... 230 5.20.3.2 bus time out (intel ? ich8 as smbus master)............................. 230 5.20.4 interrupts / smi#............................................................................. .... 230 5.20.5 smbalert# ..................................................................................... ... 232 5.20.6 smbus crc generation and checking...................................................... 232 5.20.7 smbus slave interface ......................................................................... . 232 5.20.7.1 format of slave write cycle ..................................................... 233 5.20.7.2 format of read command........................................................ 235 5.20.7.3 format of host notify command ............................................... 237 5.21 intel ? high definition audio overview ................................................................ 238 5.21.1 intel ? high definition audio docking (mobile only) ................................... 238 5.21.1.1 dock sequence....................................................................... 238 5.21.1.2 exiting d3/crst# when docked ............................................... 239 5.21.1.3 cold boot/resume from s3 when docked .................................. 240 5.21.1.4 undock sequence ................................................................... 240 5.21.1.5 interaction between dock/undock and power management states ................................................................ 241 5.21.1.6 relationship between hda_dock_rst# and hda_rst# ............. 241 5.22 intel ? active management technology (intel ? amt) (intel ? ich8do and ich8m-e only)) ................................................................. 242 5.22.1 intel ? amt features ............................................................................. 242 5.22.2 intel ? amt requirements ...................................................................... 242 5.23 serial peripheral interface (spi) ............................................................... ......... 243 5.23.1 spi supported feature overview ............................................................ 243 5.23.1.1 flash descriptor...................................................................... 244 5.23.1.2 flash access .......................................................................... 245 5.23.1.3 program register software sequencing...................................... 245 5.23.1.4 direct access security ............................................................. 245 5.23.1.5 register access security .......................................................... 245 5.23.2 spi device compatibility re quirements ...... ................ ............ ........... ...... 246 5.23.2.1 device requirements for system bios storage only ................... 246 5.23.2.2 device requirements for intel ? amt, asf and afsc firmware ............................................................................... 246 5.23.2.3 device requirements for gbe ................................................... 247 5.23.3 serial flash command set ..................................................................... 2 47 5.23.3.1 required command set for interopera bility ......... ........... ............ 247 5.23.3.2 recommended command set and opcodes ................................ 248 5.23.3.3 jedec device identification ...................................................... 248 5.23.3.4 multiple page write usage model............................................... 248 5.24 intel ? quiet system technology (desktop only) ................................................. 249 5.24.1 pwm outputs................................................................................... .... 249 5.24.2 tach inputs ................................................................................... ..... 249 5.25 thermal sensors ................................................................................. ............ 249 5.26 intel ? quick resume technology (intel ? ich8dh only) ....................................... 250 5.26.1 5.26.1 visual off ............................................................................. ..... 250 5.26.2 5.26.2 ce-like on/off ......................................................................... .. 250 5.26.3 intel ? quick resume technology signals................................................. 250 5.26.4 power button sequence ........................................................................ 2 51 10 intel ? ich8 family datasheet 5.27 feature capability mechanism ...... ............ ........... ............ ........... .......... ............. 251 5.28 serial post codes over gpio..................................................................... ....... 252 5.28.1 theory of operation........................................................................... .... 252 5.28.2 serial message format ......................................................................... . 253 6 register and memory mapping ............................................................................... 255 6.1 pci devices and functions ........................................................................ ........ 255 6.2 pci configuration map ............................................................................ .......... 257 6.3 i/o map.......................................................................................... ................ 257 6.3.1 fixed i/o address ranges ...................................................................... 2 57 6.3.2 variable i/o decode ranges ................................................................... 26 0 6.4 memory map ....................................................................................... ............ 261 6.4.1 boot-block update scheme .................................................................... 263 7 chipset configuration registers ............................................................................. 265 7.1 chipset configuration registers (memory space) .. ............................................... 265 7.1.1 vch?virtual channel capability header re gister ........... .......... ........... ...... 268 7.1.2 vcap1?virtual channel capability #1 regist er .............. .......... ........... ...... 268 7.1.3 vcap2?virtual channel capability #2 regist er .............. .......... ........... ...... 268 7.1.4 pvc?port virtual channel control register............................................... 269 7.1.5 pvs?port virtual channel status register................................................ 269 7.1.6 v0cap?virtual channel 0 resource capab ility register.... ................ .......... 269 7.1.7 v0ctl?virtual channel 0 resource control register ................................. 270 7.1.8 v0sts?virtual channel 0 resource status register .................................. 270 7.1.9 v1cap?virtual channel 1 resource capab ility register.... ................ .......... 271 7.1.10 v1ctl?virtual channel 1 resource control register ................................. 271 7.1.11 v1sts?virtual channel 1 resource status register .................................. 272 7.1.12 pat?port arbitration table .................................................................... 272 7.1.13 cir1?chipset initialization register 1 ..... ................................................ 272 7.1.14 rctcl?root complex topology capabilitie s list register ........ ............ ...... 273 7.1.15 esd?element self description register ................................................... 273 7.1.16 uld?upstream link descriptor register .................................................. 273 7.1.17 ulba?upstream link base address register ............................................ 274 7.1.18 rp1d?root port 1 descriptor register..................................................... 274 7.1.19 rp1ba?root port 1 base address register............................................... 274 7.1.20 rp2d?root port 2 descriptor register..................................................... 275 7.1.21 rp2ba?root port 2 base address register............................................... 275 7.1.22 rp3d?root port 3 descriptor register..................................................... 275 7.1.23 rp3ba?root port 3 base address register............................................... 276 7.1.24 rp4d?root port 4 descriptor register..................................................... 276 7.1.25 rp4ba?root port 4 base address register............................................... 276 7.1.26 hdd?intel ? high definition audio descriptor register............................... 277 7.1.27 hdba?intel ? high definition audio base address register......................... 277 7.1.28 rp5d?root port 5 descriptor register..................................................... 277 7.1.29 rp5ba?root port 5 base address register............................................... 278 7.1.30 rp6d?root port 6 descriptor register..................................................... 278 7.1.31 rp6ba?root port 6 base address register............................................... 278 7.1.32 ilcl?internal link capabilities list regist er .......... ........... .......... ............. 279 7.1.33 lcap?link capabilities regist er ............. .......... ........... .......... ........... ...... 279 7.1.34 lctl?link control register ................................................................... 2 80 7.1.35 lsts?link status register .................................................................... 2 80 7.1.36 cir2 ? chipset initialization register 2 ................................................... 280 7.1.37 cir3 ? chipset initialization register 3 ................................................... 281 7.1.38 cir4 ? chipset initialization register 4 ................................................... 281 7.1.39 bcr ? backbone configuration register .................................................. 281 7.1.40 rpc?root port configuration register ..................................................... 282 intel ? ich8 family datasheet 11 7.1.41 dmic?dmi control register .................................................................. 282 7.1.42 rpfn?root port function number for pc i express* root ports................... 283 7.1.43 cir5?chipset initialization register 5..... ................................................ 284 7.1.44 trsr?trap status register ................... ................................................ 284 7.1.45 trcr?trapped cycle register ............................................................... 284 7.1.46 twdr?trapped write data register......... .............................................. 285 7.1.47 iotrn ? i/o trap register (0?3) ........................................................... 285 7.1.48 dmc?dmi miscellaneous control register (mobile only) ............................ 286 7.1.49 cir6?chipset initialization register 6 (mobile only) ................................. 286 7.1.50 cir7?chipset initialization register 7..... ................................................ 286 7.1.51 tctl?tco configuration register .......................................................... 287 7.1.52 d31ip?device 31 interrupt pin register.................................................. 288 7.1.53 d30ip?device 30 interrupt pin register.................................................. 289 7.1.54 d29ip?device 29 interrupt pin register.................................................. 289 7.1.55 d28ip?device 28 interrupt pin register.................................................. 290 7.1.56 d27ip?device 27 interrupt pin register.................................................. 291 7.1.57 d26ip?device 26 interrupt pin register.................................................. 291 7.1.58 d25ip?device 25 interrupt pin register.................................................. 292 7.1.59 d31ir?device 31 interrupt route register ............................................. 292 7.1.60 d30ir?device 30 interrupt route register ............................................. 293 7.1.61 d29ir?device 29 interrupt route register ............................................. 293 7.1.62 d28ir?device 28 interrupt route register ............................................. 295 7.1.63 d27ir?device 27 interrupt route register ............................................. 296 7.1.64 d26ir?device 26 interrupt route register ............................................. 297 7.1.65 d25ir?device 25 interrupt route register ............................................. 298 7.1.66 oic?other interrupt control register ..................................................... 299 7.1.67 rc?rtc configuration register ............................................................. 299 7.1.68 hptc?high precision timer configuration register ................................... 300 7.1.69 gcs?general control and status register ............................................... 301 7.1.70 buc?backed up control register ........................................................... 303 7.1.71 fd?function disable register ................ ................................................ 303 7.1.72 cg?clock gating (mobile only).............................................................. 306 7.1.73 fdsw?function disable sus well ............ .............................................. 307 7.1.74 cir8?chipset initialization register 8..... ................................................ 308 7.1.75 cir9?chipset initialization register 9..... ................................................ 308 8 gigabit lan configuration registers ...................................................................... 309 8.1 gigabit lan configuration registers (gigabit lan ? d25:f0) ................................ 309 8.1.1 vid?vendor identification register (gigabit lan?d25:f0)........................ 310 8.1.2 did?device identification register (gig abit lan?d25:f0) ........................ 310 8.1.3 pcicmd?pci command register (gigabit lan?d25:f0) ........................... 311 8.1.4 pcists?pci status register (gigabit lan?d25:f0) ................................. 312 8.1.5 rid?revision identification register (g igabit lan?d25:f0) ...................... 313 8.1.6 cc?class code register (gigabit lan?d25:f0)....................................... 313 8.1.7 cls?cache line size register (gigabit lan?d25:f0)............................... 313 8.1.8 plt?primary latency timer register (gigabit lan?d25:f0) ..................... 313 8.1.9 ht?header type register (gigabit lan?d25:f0) .................................... 313 8.1.10 mbara?memory base address register a (gigabit lan?d25:f0) .............. 314 8.1.11 mbarb?memory base address register b (gigabit lan?d25:f0) .............. 314 8.1.12 mbarc?memory base address register c (gigabit lan?d25:f0) .............. 315 8.1.13 sid?subsystem id register (gigabit lan?d25:f0) ................................. 315 8.1.14 svid?subsystem vendor id register (gigabit lan?d25:f0) .................... 315 8.1.15 erba?expansion rom base address register (gigabit lan?d25:f0).......................................................................... 316 8.1.16 capp?capabilities list po inter register (gigabit lan? d25:f0) ........ .......... 316 12 intel ? ich8 family datasheet 8.1.17 intr?interrupt information register (gigabit lan?d25:f0)...................... 316 8.1.18 mlmg?maximum latency/minimum grant register (gigabit lan?d25:f0) .......................................................................... 316 8.1.19 clist 1?capabilities list register 1 (gigabit lan?d25:f0) ....................... 317 8.1.20 pmc?pci power management capabilities register (gigabit lan?d25:f0) .......................................................................... 317 8.1.21 pmcs?pci power management control and status register (gigabit lan?d25:f0) .............................................................. 318 8.1.22 dr?data register (gigabit lan?d25:f0)................................................ 318 8.1.23 clist 2?capabilities list register 2 (gigabit lan?d25:f0) ....................... 319 8.1.24 mctl?message control register (gigabit lan?d25:f0) ............................ 319 8.1.25 maddl?message address low register (gigabit lan?d25:f0) .................. 319 8.1.26 maddh?message address high register (gigabit lan?d25:f0)................. 320 8.1.27 mdat?message data register(gigabit lan?d25:f0) ................................ 320 8.2 gbar0?gigabit lan base address register 0 registers ........................................ 321 8.2.1 ldcr1?lan device control register 1 (gigabit lan memory mapped base address register) ............................... 321 8.2.2 ldcr2?lan device control register 2 (gigabit lan memory mapped base address register) ............................... 321 8.2.3 ldr1?lan device initialization register 1 (gigabit lan memory mapped base address register) ............................... 321 8.2.4 extcnf_ctrl?extended configuration control register (gigabit lan memory mapped base address register) ............................... 322 8.2.5 ldr2?lan device initialization register 2 (gigabit lan memory mapped base address register) ............................... 322 9 lpc interface bridge registers (d31:f0) ............................................................... 323 9.1 pci configuration registers (lpc i/f?d31:f0) .................................................... 3 23 9.1.1 vid?vendor identification register (lpc i/f?d31:f0) .............................. 324 9.1.2 did?device identification register (lpc i/f?d31:f0)............................... 324 9.1.3 pcicmd?pci command register (lpc i/f?d31:f0)................................. 325 9.1.4 pcists?pci status register (lpc i/f?d31:f0)........................................ 325 9.1.5 rid?revision identification register (l pc i/f?d31:f0) ............................ 326 9.1.6 pi?programming interface register (lpc i/f?d31:f0) ............................. 326 9.1.7 scc?sub class code register (lpc i/f?d31:f0) ..................................... 327 9.1.8 bcc?base class code register (lpc i/f?d31:f0) .................................... 327 9.1.9 plt?primary latency timer register (lpc i/f?d31:f0) ............................ 327 9.1.10 headtyp?header type register (lpc i/f?d31:f0) .................................. 327 9.1.11 ss?sub system identifiers register (lpc i/f?d31:f0) ............................. 328 9.1.12 pmbase?acpi base address register (lpc i/f?d31:f0) ........................... 328 9.1.13 acpi_cntl?acpi control register (lpc i/f ? d31:f0) ............................. 329 9.1.14 gpiobase?gpio base address register (lpc i/f ? d31:f0) ..................... 329 9.1.15 gc?gpio control register (lpc i/f ? d31:f0) ........................................ 330 9.1.16 pirq[n]_rout?pirq[a,b,c,d] routing control register (lpc i/f?d31:f0) ................................................................................ 330 9.1.17 sirq_cntl?serial irq control register (lpc i/f?d31:f0) ....................... 331 9.1.18 pirq[n]_rout?pirq[e,f,g,h] routing control register (lpc i/f?d31:f0) ................................................................................ 332 9.1.19 lpc_i/o_dec?i/o decode ranges register (lpc i/f?d31:f0)................... 333 9.1.20 lpc_en?lpc i/f enables register (lpc i/f?d31:f0) ................................ 334 9.1.21 gen1_dec?lpc i/f generic decode range 1 register (lpc i/f?d31:f0) ................................................................................ 335 9.1.22 gen2_dec?lpc i/f generic decode range 2register (lpc i/f?d31:f0) ................................................................................ 335 9.1.23 gen3_dec?lpc i/f generic decode range 3register (lpc i/f?d31:f0) ................................................................................ 336 intel ? ich8 family datasheet 13 9.1.24 gen4_dec?lpc i/f generic decode range 4register (lpc i/f?d31:f0) ................................................................................ 336 9.1.25 fwh_sel1?firmware hub select 1 register (lpc i/f?d31:f0) ................................................................................ 337 9.1.26 fwh_sel2?firmware hub select 2 register (lpc i/f?d31:f0) ................................................................................ 338 9.1.27 fwh_dec_en1?firmware hub decode enable register (lpc i/f?d31:f0) ................................................................................ 338 9.1.28 bios_cntl?bios control register (lpc i/f?d31:f0) ................................................................................ 341 9.1.29 fdcap?feature detection capability id (lpc i/f?d31:f0) ................................................................................ 341 9.1.30 fdlen?feature detection capability length (lpc i/f?d31:f0) ................................................................................ 342 9.1.31 fdver?feature detection version (lpc i/f?d31:f0) ................................................................................ 342 9.1.32 fdvct?feature vector (lpc i/f?d31:f0)............................................... 342 9.1.33 rcba?root complex base address register (lpc i/f?d31:f0) ................................................................................ 343 9.2 dma i/o registers (lpc i/f?d31:f0) ............................................................... . 344 9.2.1 dmabase_ca?dma base and current address registers (lpc i/f?d31:f0) .................................................................. 345 9.2.2 dmabase_cc?dma base and current count registers (lpc i/f?d31:f0) ................................................................................ 346 9.2.3 dmamem_lp?dma memory low page registers (lpc i/f?d31:f0) ................................................................................ 346 9.2.4 dmacmd?dma command register (lpc i/f?d31:f0) ................................................................................ 347 9.2.5 dmasta?dma status register (lpc i/f?d31:f0) ................................................................................ 347 9.2.6 dma_wrsmsk?dma write single mask register (lpc i/f?d31:f0) ................................................................................ 348 9.2.7 dmach_mode?dma channel mode register (lpc i/f?d31:f0) ................................................................................ 349 9.2.8 dma clear byte pointer register (lpc i/f?d31:f0) ................................................................................ 350 9.2.9 dma master clear register (lpc i/f?d31:f0) .......................................... 350 9.2.10 dma_clmsk?dma clear mask register (lpc i/f?d31:f0) ................................................................................ 351 9.2.11 dma_wrmsk?dma write all mask register (lpc i/f?d31:f0) ................................................................................ 351 9.3 timer i/o registers (lpc i/f?d31:f0)............................................................. .. 352 9.3.1 tcw?timer control word register (lpc i/f?d31:f0) ................................................................................ 353 9.3.2 sbyte_fmt?interval timer status byte format register (lpc i/f?d31:f0) ................................................................................ 355 9.3.3 counter access ports register (lpc i/f?d31:f0) ..................................... 356 9.4 8259 interrupt controller (pic) registers (lpc i/f?d31:f0) .................................................................................... ....... 356 9.4.1 interrupt controller i/o map (lpc i/f?d31:f0) ....................................... 356 9.4.2 icw1?initialization command word 1 register (lpc i/f?d31:f0) ................................................................................ 357 9.4.3 icw2?initialization command word 2 register (lpc i/f?d31:f0) ................................................................................ 358 9.4.4 icw3?master controller initialization command word 3 register (lpc i/f?d31:f0)......................................................... 358 14 intel ? ich8 family datasheet 9.4.5 icw3?slave controller initialization command word 3 register (lpc i/f?d31:f0) ......................................................... 359 9.4.6 icw4?initialization command word 4 register (lpc i/f?d31:f0) ................................................................................ 359 9.4.7 ocw1?operational control word 1 (interrupt mask) register (lpc i/f?d31:f0) .................................................................... 360 9.4.8 ocw2?operational control word 2 register (lpc i/f?d31:f0) ................................................................................ 360 9.4.9 ocw3?operational control word 3 register (lpc i/f?d31:f0) ................................................................................ 361 9.4.10 elcr1?master controller edge/level triggered register (lpc i/f?d31:f0) ................................................................................ 362 9.4.11 elcr2?slave controller edge/level triggered register (lpc i/f?d31:f0) ................................................................................ 363 9.5 advanced programmable interrupt controller (apic)(d31:f0)................................ 364 9.5.1 apic register map (lpc i/f?d31:f0)...................................................... 364 9.5.2 ind?index register (lpc i/f?d31:f0) ................................................... 364 9.5.3 dat?data register (lpc i/f?d31:f0) .................................................... 365 9.5.4 eoir?eoi register (lpc i/f?d31:f0) .................................................... 365 9.5.5 id?identification register (lpc i/f?d31: f0) ........................................... 366 9.5.6 ver?version register (lpc i/f?d31:f0) ................................................ 366 9.5.7 redir_tbl?redirection table (lpc i/f?d3 1:f0) ..................................... 367 9.6 real time clock registers (lpc i/f?d31:f0)....................................................... 369 9.6.1 i/o register address map (lpc i/f?d31:f0) ............................................ 369 9.6.2 indexed registers (lpc i/f?d31:f0) ...................................................... 370 9.6.2.1 rtc_rega?register a (lpc i/f?d31:f0) .................................. 371 9.6.2.2 rtc_regb?register b (general configuration) (lpc i/f?d31:f0) ................................................................... 372 9.6.2.3 rtc_regc?register c (flag register) (lpc i/f?d31:f0) ................................................................... 373 9.6.2.4 rtc_regd?register d (flag register) (lpc i/f?d31:f0) ................................................................... 373 9.7 processor interface registers (lpc i/f?d31:f0) .................................................. 3 74 9.7.1 nmi_sc?nmi status and control register (lpc i/f?d31:f0) ................................................................................ 374 9.7.2 nmi_en?nmi enable (and real time clock index) register (lpc i/f?d31:f0) .................................................................... 375 9.7.3 port92?fast a20 and init register (lpc i/f?d31:f0) ............................. 375 9.7.4 coproc_err?coprocessor error register (lpc i/f?d31:f0) ................................................................................ 376 9.7.5 rst_cnt?reset control register (lpc i/f?d31:f0)................................. 376 9.8 power management registers (pm?d31:f0) ....................................................... 377 9.8.1 power management pci configuration registers (pm?d31:f0) ...................................................................................... 377 9.8.1.1 gen_pmcon_1?general pm configuration 1 register (pm?d31:f0) ......................................................................... 378 9.8.1.2 gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) ......................................................................... 380 9.8.1.3 gen_pmcon_3?general pm configuration 3 register (pm?d31:f0) ......................................................................... 381 9.8.1.4 gen_pmcon_lock?general power management configuration lock register ...................................................... 383 9.8.1.5 cx-state_cnf?cx state configuration register (pm?d31:f0) (mobile only) ..................................................... 384 9.8.1.6 c4-timing_cnt?c4 timing control register (pm?d31:f0) (mobile only) ..................................................... 385 9.8.1.7 bm_break_en register (pm?d31:f0) (mobile only) ................... 386 intel ? ich8 family datasheet 15 9.8.1.8 pmir?power management initialization register......................... 387 9.8.1.9 qrt_sts (pm?d31:f0): quick resume technology status register (intel ? ich8dh only) ....................................... 387 9.8.1.10 qrt_cnt1 (pm?d31:f0): quick resume technology control 1 register (intel ? ich8dh only).................................... 388 9.8.1.11 qrt_cnt2 (pm?d31:f0): quick resume technology control 2 register (intel ? ich8dh only).................................... 389 9.8.1.12 gpio_rout?gpio routing control register (pm?d31:f0) ........................................................................ 389 9.8.2 apm i/o decode ................................................................................. .. 390 9.8.2.1 apm_cnt?advanced power management control port register .......................................................................... 390 9.8.2.2 apm_sts?advanced po wer management status port register .......................................................................... 390 9.8.3 power management i/o registers ........................................................... 391 9.8.3.1 pm1_sts?power management 1 status register ........................ 393 9.8.3.2 pm1_en?power management 1 enable register ......................... 396 9.8.3.3 pm1_cnt?power management 1 control ................................... 397 9.8.3.4 pm1_tmr?power management 1 timer register......................... 398 9.8.3.5 proc_cnt?processor control register ...................................... 398 9.8.3.6 lv2 ? level 2 register (mobile only) ........................................ 400 9.8.3.7 lv3?level 3 register (mobile only) .......................................... 400 9.8.3.8 lv4?level 4 register (mobile only) .......................................... 400 9.8.3.9 lv5?level 5 register (mobile only) .......................................... 401 9.8.3.10 lv6?level 6 register (mobile only) .......................................... 401 9.8.3.11 pm2_cnt?power management 2 control (mobile only)................ 401 9.8.3.12 gpe0_sts?general purpose event 0 status register .................. 402 9.8.3.13 gpe0_en?general purpose event 0 enables register .................. 405 9.8.3.14 smi_en?smi control and enable register ................................. 407 9.8.3.15 smi_sts?smi status register ................................................. 409 9.8.3.16 alt_gp_smi_en?alternate gpi smi enable register .................. 411 9.8.3.17 alt_gp_smi_sts?alternate gpi smi status register ................. 412 9.8.3.18 gpe_cntl? general purpose control register............................ 412 9.8.3.19 devact_sts ? device activity status register .......................... 413 9.8.3.20 ss_cnt? intel speedstep ? technology control register (mobile only) .................................................. 414 9.8.3.21 c3_res? c3 residency register (mobile only) ........................... 414 9.8.3.22 c5_res? c5 residency register (mobile only) ........................... 415 9.9 system management tco registers (d31:f0) ..................................................... 416 9.9.1 tco_rld?tco timer reload and current value register .......................... 416 9.9.2 tco_dat_in?tco data in register ....................................................... 417 9.9.3 tco_dat_out?tco data out register .................................................. 417 9.9.4 tco1_sts?tco1 status register .......................................................... 417 9.9.5 tco2_sts?tco2 status register .......................................................... 419 9.9.6 tco1_cnt?tco1 control register ......................................................... 420 9.9.7 tco2_cnt?tco2 control register ......................................................... 421 9.9.8 tco_message1 and tco_message2 registers ....................................... 421 9.9.9 tco_wdcnt?tco watchdog control register ......................................... 422 9.9.10 sw_irq_gen?software irq generation register .................................... 422 9.9.11 tco_tmr?tco timer initial value register............................................. 422 9.10 general purpose i/o registers (d31:f0).......................................................... ... 423 9.10.1 gpio_use_sel?gpio use select register .............................................. 424 9.10.2 gp_io_sel?gpio input/output select register ....................................... 424 9.10.3 gp_lvl?gpio level for input or output register ..................................... 425 9.10.4 gpio_use_sel override register (low)?gpio use select override register low ........................................................................... 425 9.10.5 gpo_blink?gpo blink enable register .................................................. 426 9.10.6 gp_ser_blink[31:0]?gp serial blink .................................................... 426 16 intel ? ich8 family datasheet 9.10.7 gp_sb_cmdsts[31:0]?gp serial blink command status .......................... 427 9.10.8 gp_sb_data[31:0]?gp serial blink data................................................ 427 9.10.9 gpi_inv?gpio signal invert register ..................................................... 428 9.10.10 gpio_use_sel2?gpio use select 2 register[63:32]................................ 428 9.10.11 gp_io_sel2?gpio input/output select 2 register[63:32] ........................ 429 9.10.12 gp_lvl2?gpio level for input or output 2 register[63:32] ...................... 429 9.10.13gpio_use_sel override register (high)?gpio use select override register high .......................................................................... 430 10 pci-to-pci bridge registers (d30:f0) .................................................................... 431 10.1 pci configuration registers (d30:f0) ............................................................ ..... 431 10.1.1 vid? vendor identification register (pci-pci?d30:f0)............................. 432 10.1.2 did? device identification register (pci-pci?d30:f0) ............................. 432 10.1.3 pcicmd?pci command (pci-pci?d30:f0) ............................................. 432 10.1.4 psts?pci status register (pci-pci?d30:f0) .......................................... 433 10.1.5 rid?revision identification register (pci-pci?d30:f0) ............................ 435 10.1.6 cc?class code register (pci-pci?d30:f0)............................................. 435 10.1.7 pmlt?primary master latency timer register (pci-pci?d30:f0)................................................................................ 436 10.1.8 headtyp?header type register (pci-pci?d30:f0) ................................. 436 10.1.9 bnum?bus number register (pci-pci?d30:f0) ...................................... 436 10.1.10 smlt?secondary master latency timer register (pci-pci?d30:f0)................................................................................ 437 10.1.11iobase_limit?i/o base and limit register (pci-pci?d30:f0)................................................................................ 437 10.1.12secsts?secondary status register (pci-pci?d30:f0)................................................................................ 438 10.1.13membase_limit?memory base and limit register (pci-pci?d30:f0)................................................................................ 439 10.1.14 pref_mem_base_limit?prefetchable memory base and limit register (pci-pci?d30:f0) ..................................................... 439 10.1.15pmbu32?prefetchable memory base upper 32 bits register (pci-pci?d30:f0) ................................................................... 440 10.1.16pmlu32?prefetchable memory limit upper 32 bits register (pci-pci?d30:f0) ................................................................... 440 10.1.17capp?capability list pointer register (pci-pci?d30:f0)................................................................................ 440 10.1.18intr?interrupt information register (pci-pci?d30:f0)................................................................................ 440 10.1.19 bctrl?bridge control register (pci-pci?d30:f0) ................................... 441 10.1.20spdh?secondary pci device hiding register (pci-pci?d30:f0)................................................................................ 442 10.1.21dtc?delayed transaction control regist er (pci-pci?d30:f0) ................... 443 10.1.22 bps?bridge proprietary status register (pci-pci?d30:f0) ....................... 444 10.1.23 bpc?bridge policy configuration register (pci-pci?d30:f0) ..................... 445 10.1.24svcap?subsystem vend or capability register (pci-pci?d30:f0)................................................................................ 446 10.1.25svid?subsystem vendor ids register (pci-pci?d30:f0) ......................... 446 11 ide controller registers (d31:f1) (mobile only) .................................................... 447 11.1 pci configuration registers (ide?d31:f1) ........................................................ . 447 11.1.1 vid?vendor identification register (ide?d31:f1) ................................... 448 11.1.2 did?device identification register (ide ?d31:f1).................................... 448 11.1.3 pcicmd?pci command register (ide?d31:f1) ...................................... 449 11.1.4 pcists ? pci status register (ide?d31:f1)........................................... 450 11.1.5 rid?revision identification register (i de?d31:f1).................................. 451 11.1.6 pi?programming interface register (ide?d31:f1) .................................. 451 intel ? ich8 family datasheet 17 11.1.7 scc?sub class code register (ide?d31:f1).......................................... 451 11.1.8 bcc?base class code register (ide?d31:f1) ........................................ 452 11.1.9 cls?cache line size register (ide?d31:f1) .......................................... 452 11.1.10pmlt?primary master latency timer register (ide?d31:f1) .................... 452 11.1.11pcmd_bar?primary command block base address register (ide?d31:f1)......................................................................... 452 11.1.12pcnl_bar?primary control block base address register (ide?d31:f1)......................................................................... 453 11.1.13scmd_bar?secondary command block base address register (ide d31:f1) .......................................................................... 453 11.1.14scnl_bar?secondary control block base address register (ide d31:f1) .......................................................................... 453 11.1.15bm_base ? bus master base address register (ide?d31:f1) ..................................................................................... 454 11.1.16ide_svid ? subsystem vendor identification (ide?d31:f1) ..................................................................................... 454 11.1.17ide_sid ? subsystem identification register (ide?d31:f1) ..................................................................................... 454 11.1.18intr_ln?interrupt line register (ide?d31:f1)...................................... 455 11.1.19intr_pn?interrupt pin register (ide?d31:f1) ....................................... 455 11.1.20ide_timp ? ide primary timing register (ide?d31:f1) .......................... 455 11.1.21ide_tims ? ide secondary timing register (ide?d31:f1) ..................................................................................... 457 11.1.22slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) ..................................................................................... 457 11.1.23sdma_cnt?synchronous dma control register (ide?d31:f1) ..................................................................................... 458 11.1.24sdma_tim?synchronous dma timing register (ide?d31:f1) ..................................................................................... 459 11.1.25ide_config?ide i/o configuration register (ide?d31:f1) ..................................................................................... 460 11.1.26atc?apm trapping control register (ide?d31:f1) ................................. 461 11.1.27ats?apm trapping status register (ide ?d31:f1)................................... 461 11.2 bus master ide i/o registers (ide?d31:f1) ...................................................... 4 62 11.2.1 bmicp?bus master ide command register (ide?d31:f1) ..................................................................................... 462 11.2.2 bmisp?bus master ide status register (ide?d31:f1) ............................. 463 11.2.3 bmidp?bus master ide descriptor table pointer register (ide?d31:f1) ..................................................................................... 463 12 sata controller registers (d31:f2) ....................................................................... 465 12.1 pci configuration registers (sata?d31:f2)....................................................... . 465 12.1.1 vid?vendor identification register (sata?d31:f2) ................................ 466 12.1.2 did?device identification register (sata?d31:f2) ................................. 467 12.1.3 pcicmd?pci command register (sata?d31:f2)..................................... 467 12.1.4 pcists ? pci status register (sata?d31:f2) ......................................... 468 12.1.5 rid?revision identification register (sata?d31:f2)............................... 468 12.1.6 pi?programming interface register (sata?d31:f2)................................. 469 12.1.6.1 when sub class code register (d31:f2:offset 0ah) = 01h ...................................................... 469 12.1.6.2 when sub class code register (d31:f2:offset 0ah) = 04h ...................................................... 469 12.1.6.3 when sub class code register (d31:f2:offset 0ah) = 06h ...................................................... 470 12.1.7 scc?sub class code register (sata?d31:f2) ........................................ 470 12.1.8 bcc?base class code register (sata?d31:f2sata?d31:f2) ................................................................ 470 18 intel ? ich8 family datasheet 12.1.9 pmlt?primary master latency timer register (sata?d31:f2) .................................................................................... 471 12.1.10pcmd_bar?primary command block base address register (sata?d31:f2)........................................................................ 471 12.1.11pcnl_bar?primary control block base address register (sata?d31:f2) .................................................................................... 471 12.1.12scmd_bar?secondary command block base address register (ide d31:f1) ........................................................................... 472 12.1.13scnl_bar?secondary control block base address register (ide d31:f1) ........................................................................... 472 12.1.14bar ? legacy bus mast er base address register (sata?d31:f2) .................................................................................... 473 12.1.15abar/sidpba1 ? ahci base address register/serial ata index data pair base address (sata?d31:f2).................................... 473 12.1.15.1when cc.scc is not 01h .......................................................... 473 12.1.15.2when cc.scc is 01h................................................................ 474 12.1.16svid?subsystem vendor identification register (sata?d31:f2) .................................................................................... 474 12.1.17sid?subsystem identification register (sata?d31:f2)............................. 474 12.1.18cap?capabilities pointer register (sata? d31:f2) ......... .......... ........... ...... 474 12.1.19int_ln?interrupt line register (sata?d3 1:f2)....................................... 475 12.1.20int_pn?interrupt pin register (sata?d31: f2) ........................................ 475 12.1.21 ide_tim ? ide timing register (sata?d31:f2) ....................................... 475 12.1.22 sidetim?slave ide timing register (sata?d31:f2) ................................ 477 12.1.23sdma_cnt?synchronous dma control register (sata?d31:f2) .................................................................................... 478 12.1.24sdma_tim?synchronous dma timing register (sata?d31:f2) .................................................................................... 478 12.1.25ide_config?ide i/o configuration register (sata?d31:f2) .................................................................................... 480 12.1.26pid?pci power management capability identification register (sata?d31:f2)........................................................................ 481 12.1.27pc?pci power management capabilities register (sata?d31:f2) .................................................................................... 482 12.1.28pmcs?pci power management control and status register (sata?d31:f2)........................................................................ 482 12.1.29msici?message signaled inte rrupt capability identification (sata?d31:f2) .................................................................................... 483 12.1.30msimc?message signaled interrupt message control (sata?d31:f2) .................................................................................... 483 12.1.31msima? message signaled interrupt message address (sata?d31:f2) .................................................................................... 485 12.1.32msimd?message signaled interrupt message data (sata?d31:f2)............................................................................. 485 12.1.33 map?address map register (sata?d31:f2)............................................. 486 12.1.34pcs?port control and status register (sata?d31:f2) .................................................................................... 487 12.1.35 sclkcg?sata clock gating control register ........................................... 489 12.1.36 sclkgc?sata clock general configuration register................................. 490 12.1.37 siri?sata indexed registers index register........................................... 490 12.1.38 strd?sata indexed register data register ............................................ 490 12.1.39sttt1?sata indexed registers index 00h (sata tx termination test register 1) .................................................... 492 12.1.40sir18?sata indexed registers index 18h (sata initialization register 18h) ........................................................... 492 12.1.41stme?sata indexed registers index 1ch (sata test mode enable register) .......................................................... 492 intel ? ich8 family datasheet 19 12.1.42sir28?sata indexed registers index 28h (sata initialization register 28h) ........................................................... 493 12.1.43sir40?sata indexed registers index 40h (sata initialization register 40h) ........................................................... 493 12.1.44sttt2?sata indexed registers index 74h (sata tx termination test register 2).................................................... 493 12.1.45sir78?sata indexed registers index 78h (sata initialization register 78h) ........................................................... 494 12.1.46sir84?sata indexed registers index 84h (sata initialization register 84h) ........................................................... 494 12.1.47sir88?sata indexed registers index 88h (sata initialization register 88h) ........................................................... 494 12.1.48sir8c?sata indexed registers index 8ch (sata initialization register 8ch) ........................................................... 494 12.1.49sttt3?sata indexed registers index 90h (sata tx termination test register 3).................................................... 495 12.1.50sir94?sata indexed registers index 94h (sata initialization register 94h) ........................................................... 495 12.1.51sira0?sata indexed registers index a0h (sata initialization register a0h) ........................................................... 495 12.1.52sira8?sata indexed registers index a8h (sata initialization register a8h) ........................................................... 495 12.1.53sirac?sata indexed registers index ach (sata initialization register ach)........................................................... 496 12.1.54satacr0?sata capability register 0 (sata?d31:f2) ..... .......... ........... .... 496 12.1.55satacr1?sata capability register 1 (sata?d31:f2) ..... .......... ........... .... 497 12.1.56atc?apm trapping control register (sata?d31:f2) ................................ 498 12.1.57 ats?apm trapping status register (sata?d31:f2) ................................. 498 12.1.58sp scratch pad register (sata?d31:f2) ... .............................................. 498 12.1.59bfcs?bist fis control/status register (sata?d31:f2) ........................... 499 12.1.60bftd1?bist fis transmit data1 register (sata?d31:f2) ........................ 501 12.1.61bftd2?bist fis transmit data2 register (sata?d31:f2) ........................ 501 12.2 bus master ide i/o registers (d31:f2) ........................................................... ... 502 12.2.1 bmic[p,s]?bus master ide command register (d31:f2) .......................... 503 12.2.2 bmis[p,s]?bus master ide status register (d31:f2) ............................... 504 12.2.3 bmid[p,s]?bus master ide descriptor table pointer register (d31:f5) ................................................................................ 505 12.2.3.1 pxssts?serial ata status register (d31:f5) ............................ 505 12.2.3.2 pxsctl ? serial ata control register (d31:f5).......................... 507 12.2.3.3 pxserr?serial ata error register (d31:f5) .............................. 508 12.2.4 air?ahci index register (d31:f2) ........................................................ 509 12.2.5 aidr?ahci index data register (d31:f2) .............................................. 510 12.3 serial ata index/data pair superset registers ... ................................................. 510 12.3.1 sindx?sata index register (d31:f5) ................................................... 510 12.3.2 sdata?sata index data register (d31:f5)............................................ 511 12.4 ahci registers (d31:f2) (intel ? ich8r, ich8dh, ich8do, and ich8m-e only)....................................................................................... ......... 512 12.4.1 ahci generic host control registers (d31:f2) ......................................... 513 12.4.1.1 cap?host capabilities register (d31 :f2).......... .......... ........... .... 513 12.4.1.2 ghc?global ich8 control register (d31:f2).............................. 515 12.4.1.3 is?interrupt status register (d31:f2) ...................................... 516 12.4.1.4 pi?ports implemented register (d31:f2) .................................. 517 12.4.1.5 vs?ahci version (d31:f2) ..................................................... 518 12.4.1.6 ccc_ctl?command completion coalescing control register (d31:f2) ................................................................... 518 12.4.1.7 ccc_ports?command completion coalescing ports register (d31:f2) ................................................................... 519 20 intel ? ich8 family datasheet 12.4.1.8 em_loc?enclosure management location register (d31:f2)................................................................................ 519 12.4.1.9 em_ctl?enclosure management control register (d31:f2)................................................................................ 520 12.4.2 port registers (d31:f2) ....................................................................... .. 521 12.4.2.1 pxclb?port [5:0] command list base address register (d31:f2) ................................................................... 524 12.4.2.2 pxclbu?port [5:0] command list base address upper 32-bits register (d31:f2) ........................................................ 524 12.4.2.3 pxfb?port [5:0] fis base address register (d31:f2) .................. 525 12.4.2.4 pxfbu?port [5:0] fis base address upper 32-bits register (d31:f2) ................................................................... 525 12.4.2.5 pxis?port [5:0] interrupt status register (d31:f2) .................... 526 12.4.2.6 pxie?port [5:0] interrupt enable register (d31:f2) .................... 527 12.4.2.7 pxcmd?port [5:0] command register (d31:f2) ......................... 529 12.4.2.8 pxtfd?port [5:0] task file data register (d31:f2)..................... 532 12.4.2.9 pxsig?port [5:0] signature register (d31:f2) ........................... 532 12.4.2.10pxssts?port [5:0] serial ata status register (d31:f2) ................................................................... 533 12.4.2.11pxsctl ? port [5:0] serial ata control register (d31:f2) ................................................................... 534 12.4.2.12pxserr?port [5:0] serial ata error register (d31:f2) ................ 535 12.4.2.13pxsact?port [5:0] serial ata active (d31:f2) ........................... 537 12.4.2.14pxci?port [5:0] command issue register (d31:f2) .................... 537 13 sata controller registers (d31:f5) ....................................................................... 539 13.1 pci configuration registers (sata?d31:f5) ....................................................... . 539 13.1.1 vid?vendor identification register (sata?d31:f5) ................................. 540 13.1.2 did?device identification register (sata?d31:f5) ................................. 541 13.1.3 pcicmd?pci command register (sata?d31:f5) ..................................... 541 13.1.4 pcists ? pci status register (sata?d31:f5) ......................................... 542 13.1.5 rid?revision identification register (sata?d31:f5) ............................... 542 13.1.6 pi?programming interface register (sata?d31:f5) ................................. 543 13.1.7 scc?sub class code register (sata?d31:f5) ......................................... 543 13.1.8 bcc?base class code register (sata?d31:f5sata?d31:f5)................................................................. 543 13.1.9 pmlt?primary master latency timer register (sata?d31:f5) .................................................................................... 543 13.1.10pcmd_bar?primary command block base address register (sata?d31:f5)........................................................................ 544 13.1.11pcnl_bar?primary control block base address register (sata?d31:f5) .................................................................................... 544 13.1.12scmd_bar?secondary command block base address register (ide d31:f1) ........................................................................... 544 13.1.13scnl_bar?secondary control block base address register (ide d31:f1) ........................................................................... 545 13.1.14bar ? legacy bus mast er base address register (sata?d31:f5) .................................................................................... 545 13.1.15sidpba ? sata index/data pair base address register (sata?d31:f5) .................................................................................... 546 13.1.16svid?subsystem vendor identification register (sata?d31:f5) .................................................................................... 546 13.1.17sid?subsystem identification register (sata?d31:f5) .................................................................................... 546 13.1.18cap?capabilities pointer register (sata? d31:f5) ......... .......... ........... ...... 546 13.1.19int_ln?interrupt line register (sata?d3 1:f5)....................................... 547 13.1.20int_pn?interrupt pin register (sata?d31: f5) ........................................ 547 13.1.21 ide_tim ? ide timing register (sata?d31:f5) ....................................... 547 intel ? ich8 family datasheet 21 13.1.22d1tim?device 1 ide timing register (sata?d31:f5) .............................. 549 13.1.23sdma_cnt?synchronous dma control register (sata?d31:f5).................................................................................... 549 13.1.24sdma_tim?synchronous dma timing register (sata?d31:f5).................................................................................... 550 13.1.25ide_config?ide i/o configuration register (sata?d31:f5).................................................................................... 551 13.1.26 pid?pci power manageme nt capability identification register (sata?d31:f5) ....................................................................... 552 13.1.27 pc?pci power management capabilities register (sata?d31:f5).................................................................................... 552 13.1.28pmcs?pci power management control and status register (sata?d31:f5) ....................................................................... 553 13.1.29map?address map register (sata?d31:f5) ............................................ 553 13.1.30pcs?port control and status register (sata?d31:f5).............................. 554 13.1.31atc?apm trapping control register (sata?d31:f5) ................................ 555 13.1.32 ats?apm trapping status register (sata?d31:f5) ................................. 555 13.2 bus master ide i/o registers (d31:f5) ........................................................... ... 556 13.2.1 bmic[p,s]?bus master ide command register (d31:f5) .......................... 557 13.2.2 bmis[p,s]?bus master ide status register (d31:f5) ............................... 558 13.2.3 bmid[p,s]?bus master ide descriptor table pointer register (d31:f5) ................................................................................ 558 13.2.3.1 pxssts?serial ata status register (d31:f5) ............................ 559 13.2.3.2 pxsctl ? serial ata control register (d31:f5).......................... 560 13.2.3.3 pxserr?serial ata error register (d31:f5) .............................. 561 13.3 serial ata index/data pair superset registers ... ................................................. 563 13.3.1 sindx?sata index register (d31:f5) ................................................... 563 13.3.2 sdata?sata index data register (d31:f5)............................................ 563 14 uhci controllers registers .................................................................................... 565 14.1 pci configuration registers (usb?d29:f0/f1/f2, d26:f0/f1) ..................................................................... 56 5 14.1.1 vid?vendor identification register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 566 14.1.2 did?device identification register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 566 14.1.3 pcicmd?pci command register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 567 14.1.4 pcists?pci status register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 568 14.1.5 rid?revision identification register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 568 14.1.6 pi?programming interface register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 569 14.1.7 scc?sub class code register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 569 14.1.8 bcc?base class code register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 569 14.1.9 mlt?master latency timer register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 569 14.1.10headtyp?header type register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 570 14.1.11base?base address register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 570 14.1.12svid ? subsystem vendor identification register (usb?d29:f0/f1/f2, d26:f0/f1) .......................................................... 570 22 intel ? ich8 family datasheet 14.1.13sid ? subsystem identification register (usb?d29:f0/f1/f2/f3, d26:f0/f1) ...................................................... 571 14.1.14int_ln?interrupt line register (usb?d29:f0/f1/f2, d26:f0/f1)........................................................... 571 14.1.15int_pn?interrupt pin register (usb?d29:f0/f1/f2/f3, d26:f0/f1) ...................................................... 571 14.1.16usb_relnum?serial bus release number register (usb?d29:f0/f1/f2, d26:f0/f1)........................................................... 572 14.1.17usb_legkey?usb legacy keyboard/mouse control register (usb?d29:f0/f1/f2, d26:f0/f1) .............................................. 572 14.1.18usb_res?usb resume enable register (usb?d29:f0/f1/f2, d26:f0/f1)........................................................... 574 14.1.19cwp?core well policy register (usb?d29:f0/f1/f2, d26:f0/f1)........................................................... 574 14.2 usb i/o registers............................................................................... ............. 575 14.2.1 usbcmd?usb command register .......................................................... 576 14.2.2 usbsts?usb status register ................................................................ 579 14.2.3 usbintr?usb interrupt enable register................................................. 580 14.2.4 frnum?frame number register ............................................................ 580 14.2.5 frbaseadd?frame list base address register........................................ 581 14.2.6 sofmod?start of frame modify register ................................................ 581 14.2.7 portsc[0,1]?port status and control register ........................................ 582 15 ehci controller registers (d29:f7, d26:f7) ........................................................... 585 15.1 usb ehci configuration registers (usb ehci?d29:f7, d26:f7)........................................................................... . 585 15.1.1 vid?vendor identification register (usb ehci?d29:f7, d26:f7)................................................................. 586 15.1.2 did?device identification register (usb ehci?d29:f7, d26:f7)................................................................. 586 15.1.3 pcicmd?pci command register (usb ehci?d29:f7, d26:f7)................................................................. 587 15.1.4 pcists?pci status register (usb ehci?d29:f7, d26:f7)................................................................. 588 15.1.5 rid?revision identification register (usb ehci?d29:f7, d26:f7)................................................................. 589 15.1.6 pi?programming interface register (usb ehci?d29:f7, d26:f7)................................................................. 589 15.1.7 scc?sub class code register (usb ehci?d29:f7, d26:f7)................................................................. 589 15.1.8 bcc?base class code register (usb ehci?d29:f7, d26:f7)................................................................. 589 15.1.9 pmlt?primary master latency timer register (usb ehci?d29:f7, d26:f7)................................................................. 590 15.1.10mem_base?memory base address register (usb ehci?d29:f7, d26:f7)................................................................. 590 15.1.11svid?usb ehci subsystem vendor id register (usb ehci?d29:f7, d26:f7)................................................................. 590 15.1.12sid?usb ehci subsystem id register (usb ehci?d29:f7, d26:f7)................................................................. 591 15.1.13cap_ptr?capabilit ies pointer register (usb ehci?d29:f7, d26:f7)................................................................. 591 15.1.14int_ln?interrupt line register (usb ehci?d29:f7, d26:f7)................................................................. 591 15.1.15int_pn?interrupt pin register (usb ehci?d29:f7, d26:f7)................................................................. 591 intel ? ich8 family datasheet 23 15.1.16pwr_capid?pci power management capability id register (usb ehci?d29:f7, d26:f7) .................................................... 592 15.1.17nxt_ptr1?next item pointer #1 register (usb ehci?d29:f7, d26:f7) ................................................................ 592 15.1.18 pwr_cap?power management capabilities register (usb ehci?d29:f7, d26:f7) ................................................................ 593 15.1.19pwr_cntl_sts?power management control/ status register (usb ehci?d29:f7, d26:f7) .......................................... 594 15.1.20debug_capid?debug port capability id register (usb ehci?d29:f7, d26:f7) ................................................................ 595 15.1.21nxt_ptr2?next item pointer #2 register (usb ehci?d29:f7, d26:f7) ................................................................ 595 15.1.22debug_base?debug port base offset register (usb ehci?d29:f7, d26:f7) ................................................................ 595 15.1.23usb_relnum?usb release number register (usb ehci?d29:f7, d26:f7) ................................................................ 595 15.1.24fl_adj?frame length adjustment register (usb ehci?d29:f7, d26:f7) ................................................................ 596 15.1.25 pwake_cap?port wa ke capability register (usb ehci?d29:f7, d26:f7) ................................................................ 597 15.1.26leg_ext_cap?usb ehci legacy support extended capability register (usb ehci?d29:f7, d26: f7) ............ .......... ........... .... 597 15.1.27leg_ext_cs?usb ehci legacy support extended control / status register (usb ehci?d29:f7, d26:f7) ............................. 598 15.1.28special_smi?intel specific usb 2.0 smi register (usb ehci?d29:f7, d26:f7) ................................................................ 600 15.1.29access_cntl?access control register (usb ehci?d29:f7, d26:f7) ................................................................ 601 15.1.30ehciir1?ehci initialization register 1 (mobile only) (usb ehci?d29:f7, d26:f7) ................................................................ 602 15.1.31ehciir2?ehci initialization register 2 (usb ehci?d29:f7, d26:f7) ................................................................ 602 15.2 memory-mapped i/o registers ..................................................................... ..... 603 15.2.1 host controller capability registers .......... ............ ........... ........... ............ 603 15.2.1.1 caplength?cap ability registers length........ .......... ........... ...... 604 15.2.1.2 hciversion?host controller interface version number...................................................................... 604 15.2.1.3 hcsparams?host controller structural parameters ............................................................................ 605 15.2.1.4 hccparams?host controller capability parameters register ................................................................ 606 15.2.2 host controller operational registers ........ .............................................. 607 15.2.2.1 usb2.0_cmd?usb 2.0 command register ................................ 608 15.2.2.2 usb2.0_sts?usb 2.0 status register ...................................... 610 15.2.2.3 usb2.0_intr?usb 2.0 interrupt enable register ....................... 612 15.2.2.4 frindex?frame index register ............................................... 613 15.2.2.5 ctrldssegment?control data structure segment register ................................................................... 614 15.2.2.6 periodiclistbase?periodic frame list base address register..................................................................... 614 15.2.2.7 asynclistaddr?current asynchronous list address register..................................................................... 615 15.2.2.8 configflag?configure flag register ....................................... 615 15.2.2.9 portsc?port n status and control register .............................. 616 15.2.3 usb 2.0-based debug port register ........................................................ 620 15.2.3.1 cntl_sts?control/status register .......................................... 621 15.2.3.2 usbpid?usb pids register ..................................................... 622 15.2.3.3 databuf[7:0]?data buffer bytes[7:0] register ......................... 623 24 intel ? ich8 family datasheet 15.2.3.4 config?configuration register................................................ 623 16 smbus controller registers (d31:f3) ..................................................................... 625 16.1 pci configuration registers (smbus?d31:f3) .................................................... 62 5 16.1.1 vid?vendor identification register (smbus?d31:f3) .............................. 625 16.1.2 did?device identification register (smbus?d31:f3)............................... 626 16.1.3 pcicmd?pci command register (smbus?d31:f3).................................. 626 16.1.4 pcists?pci status register (smbus?d31:f3)........................................ 627 16.1.5 rid?revision identification register (s mbus?d31:f3)............................. 627 16.1.6 pi?programming interface register (smbus?d31:f3).............................. 628 16.1.7 scc?sub class code register (smbus?d31:f3) ..................................... 628 16.1.8 bcc?base class code register (smbus?d31:f3) .................................... 628 16.1.9 smbmbar0 ? d31_f3_smbus memory base address 0 .............................. 628 16.1.10smb_base?smbus base address register (smbus?d31:f3) ................................................................................ 629 16.1.11svid ? subsystem vendor identification register (smbus?d31:f2/f4) ............................................................................ 629 16.1.12sid ? subsystem identification register (smbus?d31:f2/f4) ............................................................................ 629 16.1.13 int_ln?interrupt line register (smbus?d31:f3) ................................... 630 16.1.14int_pn?interrupt pin register (smbus?d 31:f3) .................................... 630 16.1.15hostc?host configuration register (smbus?d31:f3) ............................. 630 16.2 smbus i/o and memory mapped i/o registers ..................................................... 63 1 16.2.1 hst_sts?host status register (smbus?d31:f3) ................................... 632 16.2.2 hst_cnt?host control register (smbus?d31:f3) .................................. 633 16.2.3 hst_cmd?host command register (smbus?d31:f3) ............................. 635 16.2.4 xmit_slva?transmit slave address register (smbus?d31:f3) ................................................................................ 635 16.2.5 hst_d0?host data 0 register (smbus?d31:f3)..................................... 635 16.2.6 hst_d1?host data 1 register (smbus?d31:f3)..................................... 635 16.2.7 host_block_db?host bl ock data byte register (smbus?d31:f3) ................................................................................ 636 16.2.8 pec?packet error check (pec) register (smbus?d31:f3) ................................................................................ 636 16.2.9 rcv_slva?receive slave address register (smbus?d31:f3) ................................................................................ 637 16.2.10 slv_data?receive slave data register (smbus?d31:f3) ....................... 637 16.2.11 aux_sts?auxiliary status register (smbus?d31:f3).............................. 637 16.2.12aux_ctl?auxiliary control register (s mbus?d31:f3)........... ............ ...... 638 16.2.13smlink_pin_ctl?smlink pin control register (smbus?d31:f3) ................................................................................ 638 16.2.14smbus_pin_ctl?smbus pin control register (smbus?d31:f3) ................................................................................ 639 16.2.15 slv_sts?slave status register (smbus ?d31:f3) .................................. 639 16.2.16slv_cmd?slave command register (smbus?d31:f3) ............................ 640 16.2.17notify_daddr?notify device address register (smbus?d31:f3) ................................................................................ 640 16.2.18notify_dlow?notify data low byte register (smbus?d31:f3) ................................................................................ 641 16.2.19notify_dhigh?notify data high byte register (smbus?d31:f3) ................................................................................ 641 17 intel ? high definition audio co ntroller registers (d27:f0) .................................... 643 17.1 intel ? high definition audio pci configuration space (intel ? high definition audio? d27:f0)........................................................................... ..... 643 17.1.1 vid?vendor identification register (intel ? high definition audio controller?d27:f0) ..................................... 645 intel ? ich8 family datasheet 25 17.1.2 did?device identification register (intel ? high definition audio controller?d27:f0)..................................... 645 17.1.3 pcicmd?pci command register (intel ? high definition audio controller?d27:f0)..................................... 646 17.1.4 pcists?pci status register (intel ? high definition audio controller?d27:f0)..................................... 647 17.1.5 rid?revision identification register (intel ? high definition audio controller?d27:f0)..................................... 647 17.1.6 pi?programming interface register (intel ? high definition audio controller?d27:f0)..................................... 648 17.1.7 scc?sub class code register (intel ? high definition audio controller?d27:f0)..................................... 648 17.1.8 bcc?base class code register (intel ? high definition audio controller?d27:f0)..................................... 648 17.1.9 cls?cache line size register (intel ? high definition audio controller?d27:f0)..................................... 648 17.1.10lt?latency timer register (intel ? high definition audio controller?d27:f0)..................................... 648 17.1.11headtyp?header type register (intel ? high definition audio controller?d27:f0)..................................... 649 17.1.12hdbarl?intel ? high definition audio lower base address register (intel ? high definition audio?d27:f0) ....................................... 649 17.1.13hdbaru?intel ? high definition audio upper base address register (intel ? high definition audio controller?d27:f0) ........................ 649 17.1.14svid?subsystem vendor identification register (intel ? high definition audio controller?d27:f0)..................................... 650 17.1.15sid?subsystem identification register (intel ? high definition audio controller?d27:f0)..................................... 650 17.1.16capptr?capabilities pointe r register (audio?d30:f2) .... .......... ........... .... 650 17.1.17intln?interrupt line register (intel ? high definition audio controller?d27:f0)..................................... 651 17.1.18intpn?interrupt pin register (intel ? high definition audio controller?d27:f0)..................................... 651 17.1.19hdctl?intel ? high definition audio control register (intel ? high definition audio controller?d27:f0)..................................... 651 17.1.20tcsel?traffic class select register (intel ? high definition audio controller?d27:f0)..................................... 652 17.1.21dckctl?docking control register (intel ? high definition audio controller?d27:f0) (mobile only) ................. 652 17.1.22dcksts?docking status register (intel ? high definition audio controller?d27:f0) (mobile only) ................. 653 17.1.23 pid?pci power manageme nt capability id register (intel ? high definition audio controller?d27:f0)..................................... 653 17.1.24 pc?power management capabilities register (intel ? high definition audio controller?d27:f0)..................................... 654 17.1.25pcs?power management co ntrol and status register (intel ? high definition audio controller?d27:f0)..................................... 654 17.1.26 mid?msi capability id register (intel ? high definition audio controller?d27:f0)..................................... 655 17.1.27mmc?msi message control register (intel ? high definition audio controller?d27:f0)..................................... 655 17.1.28mmla?msi message lower address register (intel ? high definition audio controller?d27:f0)..................................... 656 17.1.29mmua?msi message upper address register (intel ? high definition audio controller?d27:f0)..................................... 656 17.1.30mmd?msi message data register (intel ? high definition audio controller?d27:f0)..................................... 656 26 intel ? ich8 family datasheet 17.1.31pxid?pci express* capability id register (intel ? high definition audio controller?d27:f0) ..................................... 656 17.1.32pxc?pci express* capabilities register (intel ? high definition audio controller?d27:f0) ..................................... 657 17.1.33devcap?device ca pabilities register (intel ? high definition audio controller?d27:f0) ..................................... 657 17.1.34devc?device control register (intel ? high definition audio controller?d27:f0) ..................................... 658 17.1.35devs?device status register (intel ? high definition audio controller?d27:f0) ..................................... 659 17.1.36vccap?virtual channel enhanced capability header (intel ? high definition audio controller?d27:f0) ..................................... 659 17.1.37pvccap1?port vc capability register 1 (intel ? high definition audio controller?d27:f0) ..................................... 660 17.1.38pvccap2 ? port vc capability register 2 (intel ? high definition audio controller?d27:f0) ..................................... 660 17.1.39pvcctl ? port vc control register (intel ? high definition audio controller?d27:f0) ..................................... 660 17.1.40pvcsts?port vc status register (intel ? high definition audio controller?d27:f0) ..................................... 661 17.1.41vc0cap?vc0 resource capability register (intel ? high definition audio controller?d27:f0) ..................................... 661 17.1.42vc0ctl?vc0 resource control register (intel ? high definition audio controller?d27:f0) ..................................... 661 17.1.43vc0sts?vc0 resource status register (intel ? high definition audio controller?d27:f0) ..................................... 662 17.1.44vcicap?vci resource capability register (intel ? high definition audio controller?d27:f0) ..................................... 662 17.1.45vcictl?vci resource control register (intel ? high definition audio controller?d27:f0) ..................................... 663 17.1.46vcists?vci resource status register (intel ? high definition audio controller?d27:f0) ..................................... 663 17.1.47rccap?root complex link declaration enhanced capability header register (intel ? high definition audio controller?d27:f0) .............................................................................. 664 17.1.48esd?element self description register (intel ? high definition audio controller?d27:f0) ..................................... 664 17.1.49l1desc?link 1 description register (intel ? high definition audio controller?d27:f0) ..................................... 664 17.1.50l1addl?link 1 lower address register (intel ? high definition audio controller?d27:f0) ..................................... 665 17.1.51l1addu?link 1 upper address register (intel ? high definition audio controller?d27:f0) ..................................... 665 17.2 intel ? high definition audio memory mapped configuration registers (intel ? high definition audio? d27:f0)................ .............................................. 666 17.2.1 gcap?global capabilities register (intel ? high definition audio controller?d27:f0) ..................................... 670 17.2.2 vmin?minor version register (intel ? high definition audio controller?d27:f0) ..................................... 670 17.2.3 vmaj?major version register (intel ? high definition audio controller?d27:f0) ..................................... 670 17.2.4 outpay?output payload capability register (intel ? high definition audio controller?d27:f0) ..................................... 671 17.2.5 inpay?input payload capability register (intel ? high definition audio controller?d27:f0) ..................................... 671 17.2.6 gctl?global control register (intel ? high definition audio controller?d27:f0) ..................................... 672 intel ? ich8 family datasheet 27 17.2.7 wakeen?wake enable register (intel ? high definition audio controller?d27:f0)..................................... 673 17.2.8 statests?state change status register (intel ? high definition audio controller?d27:f0)..................................... 673 17.2.9 gsts?global status register (intel ? high definition audio controller?d27:f0)..................................... 674 17.2.10 ecap?extended capabilities (intel ? high definition audio controller?d27:f0)..................................... 675 17.2.11outstrmpay?output stream payload capability (intel ? high definition audio controller?d27:f0)..................................... 675 17.2.12 instrmpay? input stream payload capability (intel ? high definition audio controller?d27:f0)..................................... 676 17.2.13intctl?interrupt control register (intel ? high definition audio controller?d27:f0)..................................... 677 17.2.14intsts?interrupt status register (intel ? high definition audio controller?d27:f0)..................................... 678 17.2.15walclk?wall clock counter register (intel ? high definition audio controller?d27:f0)..................................... 679 17.2.16ssync?stream synchronization register (intel ? high definition audio controller?d27:f0)..................................... 679 17.2.17corblbase?corb lower base address register (intel ? high definition audio controller?d27:f0)..................................... 680 17.2.18corbubase?corb upper base address register (intel ? high definition audio controller?d27:f0)..................................... 680 17.2.19corbwp?corb write pointer register (intel ? high definition audio controller?d27:f0)..................................... 680 17.2.20corbrp?corb read pointer register (intel ? high definition audio controller?d27:f0)..................................... 681 17.2.21corbctl?corb control register (intel ? high definition audio controller?d27:f0)..................................... 681 17.2.22corbst?corb status register (intel ? high definition audio controller?d27:f0)..................................... 682 17.2.23corbsize?corb size register intel ? high definition audio controller?d27:f 0) ...................................... 682 17.2.24rirblbase?rirb lower base address register (intel ? high definition audio controller?d27:f0)..................................... 682 17.2.25 rirbubase?rirb upper base address register (intel ? high definition audio controller?d27:f0)..................................... 683 17.2.26rirbwp?rirb write pointer register (intel ? high definition audio controller?d27:f0)..................................... 683 17.2.27rintcnt?response interrupt count register (intel ? high definition audio controller?d27:f0)..................................... 684 17.2.28 rirbctl?rirb control register (intel ? high definition audio controller?d27:f0)..................................... 684 17.2.29 rirbsts?rirb status register (intel ? high definition audio controller?d27:f0)..................................... 685 17.2.30rirbsize?rirb size register (intel ? high definition audio controller?d27:f0)..................................... 685 17.2.31ic?immediate command register (intel ? high definition audio controller?d27:f0)..................................... 685 17.2.32ir?immediate response register (intel ? high definition audio controller?d27:f0)..................................... 686 17.2.33irs?immediate command status register (intel ? high definition audio controller?d27:f0)..................................... 686 17.2.34dplbase?dma position lower base address register (intel ? high definition audio controller?d27:f0)..................................... 687 28 intel ? ich8 family datasheet 17.2.35dpubase?dma position upper base address register (intel ? high definition audio controller?d27:f0) ..................................... 687 17.2.36sdctl?stream descriptor control register (intel ? high definition audio controller?d27:f0) ..................................... 688 17.2.37 sdsts?stream descriptor status register (intel ? high definition audio controller?d27:f0) ..................................... 690 17.2.38sdlpib?stream descriptor link position in buffer register (intel ? high definition audio controller?d27:f0) ......................... 691 17.2.39sdcbl?stream descriptor cyclic buffer length register (intel ? high definition audio controller?d27:f0) ..................................... 691 17.2.40sdlvi?stream descriptor last valid index register (intel ? high definition audio controller?d27:f0) ..................................... 692 17.2.41sdfifow?stream descriptor fifo watermark register (intel ? high definition audio controller?d27:f0) ..................................... 692 17.2.42sdfifos?stream descriptor fifo size register (intel ? high definition audio controller?d27:f0) ..................................... 693 17.2.43sdfmt?stream descriptor format register (intel ? high definition audio controller?d27:f0) ..................................... 694 17.2.44sdbdpl?stream descriptor buff er descriptor list pointer lower base address register (intel ? high definition audio controller?d27:f0) .............................................................................. 695 17.2.45sdbdpu?stream descriptor buffer descriptor list pointer upper base address register (intel ? high definition audio controller?d27:f0) .............................................................................. 695 18 pci express* conf iguration registers .................................................................... 697 18.1 pci express* configuration registers (pci express?d28:f0/f1/f2/f3/f4/f5) .............................................................. 697 18.1.1 vid?vendor identification register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 700 18.1.2 did?device identification register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 700 18.1.3 pcicmd?pci command register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 701 18.1.4 pcists?pci status register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 702 18.1.5 rid?revision identification register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 703 18.1.6 pi?programming interface register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 703 18.1.7 scc?sub class code register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 703 18.1.8 bcc?base class code register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 703 18.1.9 cls?cache line size register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 704 18.1.10plt?primary latency timer register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 704 18.1.11 headtyp?header type register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 704 18.1.12bnum?bus number register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 704 18.1.13slt?secondary latency timer (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 705 18.1.14iobl?i/o base and limit register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 705 18.1.15ssts?secondary status register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 706 intel ? ich8 family datasheet 29 18.1.16mbl?memory base and limit register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 707 18.1.17pmbl?prefetchable memory base and limit register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 707 18.1.18pmbu32?prefetchable memory base upper 32 bits register (pci express?d28:f0/f1/f2/f3/f4/f5) ...................................... 708 18.1.19pmlu32?prefetchable memory limit upper 32 bits register (pci express?d28:f0/f1/f2/f3/f4/f5) ...................................... 708 18.1.20capp?capab ilities list pointer register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 708 18.1.21intr?interrupt information register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 709 18.1.22bctrl?bridge control register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 709 18.1.23 clist?capabilities list register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 710 18.1.24 xcap?pci express* capabilities register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 710 18.1.25dcap?device ca pabilities register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 711 18.1.26dctl?device control register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 712 18.1.27dsts?device status register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 713 18.1.28lcap?link capabilities register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 713 18.1.29lctl?link control register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 715 18.1.30lsts?link status register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 716 18.1.31 slcap?slot capabilities register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 717 18.1.32slctl?slot control register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 718 18.1.33slsts?slot status register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 719 18.1.34rctl?root control register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 720 18.1.35rsts?root status register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 720 18.1.36mid?message signaled interrupt identifiers register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 721 18.1.37mc?message signaled interrupt message control register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 721 18.1.38ma?message signaled interrupt message address register (pci express?d28:f0/f1/f2/f3/f4/f5) ...................................... 721 18.1.39md?message signaled interrupt message data register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 722 18.1.40 svcap?subsystem ve ndor capability register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 722 18.1.41svid?subsystem vendor identification register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 722 18.1.42 pmcap?power management capability register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 722 18.1.43 pmc?pci power management capabilities register (pci express?d28:f0/f1/f2/f3/f4/f5)................................................... 723 30 intel ? ich8 family datasheet 18.1.44pmcs?pci power management control and status register (pci express?d28:f0/f1/f2/f3/f4/f5)....................................... 724 18.1.45mpc?miscellaneous port configuration register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 725 18.1.46 smscs?smi/sci status register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 727 18.1.47 rpdcgen?root port dynamic clock gating enable (pci express-d28:f0/f1/f2/f3/f4 /f5) (mobile only) ....................................................... 728 18.1.48ipws?intel ? pro/wireless 3945abg status (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 728 18.1.49vch?virtual channel capability header register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 729 18.1.50vcap2?virtual channel capability 2 register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 729 18.1.51pvc?port virtual channel control register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 729 18.1.52pvs ? port virtual channel status register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 729 18.1.53v0cap ? virtual channel 0 resource capability register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 730 18.1.54v0ctl ? virtual channel 0 resource control register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 731 18.1.55v0sts ? virtual channel 0 resource status register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 731 18.1.56ues ? uncorrectable error status register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 732 18.1.57uem ? uncorrectable error mask (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 733 18.1.58uev ? uncorrectable error severity (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 734 18.1.59ces ? correctable error status register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 735 18.1.60cem ? correctable error mask register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 736 18.1.61aecc ? advanced error ca pabilities and control register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 736 18.1.62res ? root error status register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 737 18.1.63rctcl ? root complex topology capability list register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 737 18.1.64esd ? element self description register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 738 18.1.65uld ? upstream link description register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 738 18.1.66ulba ? upstream link base address register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 739 18.1.67peetm ? pci express* extended test mode register (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................... 739 19 high precision event timer registers ..................................................................... 741 19.1 memory-mapped registers ......................................................................... ....... 741 19.1.1 gcap_id?general capabilities and identifi cation register ...... ......... .......... 742 19.1.2 gen_conf?general configuration register ............................................. 743 19.1.3 gintr_sta?general interrupt status register......................................... 743 19.1.4 main_cnt?main counter value register ................................................. 744 19.1.5 timn_conf?timer n configuration and ca pabilities register .... ........... ...... 744 19.1.6 timn_comp?timer n comparator value register ..................................... 746 intel ? ich8 family datasheet 31 20 serial peripheral interface (spi) ........................................................................... 747 20.1 serial peripheral interface memory-mapped configuration registers ....................... 747 20.1.1 bfpr?bios flash primary region register (spi memory mapped configuration registers) ......................................... 748 20.1.2 hsfs?hardware sequencing flash status register (spi memory mapped configuration registers) ......................................... 749 20.1.3 hsfc?hardware sequencing flash control register (spi memory mapped configuration registers) ......................................... 750 20.1.4 faddr?flash address register (spi memory mapped configuration registers) ......................................... 751 20.1.5 fdata0?flash data 0 register (spi memory mapped configuration registers) ......................................... 751 20.1.6 fdatan?flash data [n] register (spi memory mapped configuration registers) ......................................... 751 20.1.7 frap?flash regions access permissions register (spi memory mapped configuration registers) ......................................... 752 20.1.8 freg0?flash region 0 (flash descriptor) register (spi memory mapped configuration registers) ......................................... 752 20.1.9 freg1?flash region 1 (bios descriptor) register (spi memory mapped configuration registers) ......................................... 753 20.1.10freg2?flash region 2 (me) register (spi memory mapped configuration registers) ......................................... 753 20.1.11freg3?flash region 3 (gbe) register (spi memory mapped configuration registers) ......................................... 754 20.1.12pr0?protected range 0 register (spi memory mapped configuration registers) ......................................... 754 20.1.13pr1?protected range 1 register (spi memory mapped configuration registers) ......................................... 755 20.1.14pr2?protected range 2 register (spi memory mapped configuration registers) ......................................... 755 20.1.15pr3?protected range 3 register (spi memory mapped configuration registers) ......................................... 756 20.1.16pr4?protected range 4 register (spi memory mapped configuration registers) ......................................... 756 20.1.17ssfs?software sequencing flash status register (spi memory mapped configuration registers) ......................................... 757 20.1.18ssfc?software sequencing flash control register (spi memory mapped configuration registers) ......................................... 758 20.1.19preop?prefix opcode configuration register (spi memory mapped configuration registers) ......................................... 759 20.1.20optype?opcode type configuration register (spi memory mapped configuration registers) ......................................... 759 20.1.21opmenu?opcode menu configuration register (spi memory mapped configuration registers) ......................................... 760 20.1.22fdoc?flash descriptor ob servability control register (spi memory mapped configuration registers) ......................................... 761 20.1.23fdod?flash descriptor observability data register (spi memory mapped configuration registers) ......................................... 761 20.1.24 vscc?vendor specific co mponent capabilities register (spi memory mapped configuration registers) ......................................... 762 20.2 flash descriptor registers ...................................................................... .......... 763 20.2.1 flash descriptor content ...................................................................... . 763 20.2.1.1 flvalsig?flash valid signature register (flash descriptor memory mapped configuration registers) .............................................................................. 763 32 intel ? ich8 family datasheet 20.2.1.2 flmap0?flash map 0 register (flash descriptor memory mapped configuration registers) .............................................................................. 763 20.2.1.3 flmap1?flash map 1 register (flash descriptor memory mapped configuration registers) .............................................................................. 764 20.2.1.4 flmap2?flash map 2 register (flash descriptor memory mapped configuration registers) .............................................................................. 764 20.2.2 flash descriptor component section ....................................................... 765 20.2.2.1 flcomp?flash components register (flash descriptor memory mapped configuration registers) .............................................................................. 765 20.2.2.2 flill?flash invalid instructions register (flash descriptor memory mapped configuration registers) .............................................................................. 766 20.2.3 flash descriptor region section .............................................................. 7 67 20.2.3.1 flreg0?flash region 0 (flash descriptor) register (flash descriptor memory mapped configuration registers) .............................................................................. 767 20.2.3.2 flreg1?flash region 1 (bios) register (flash descriptor memory mapped configuration registers) .............................................................................. 767 20.2.3.3 flreg2?flash region 2 (me) register (flash descriptor memory mapped configuration registers) .............................................................................. 768 20.2.3.4 flreg3?flash region 3 (gbe) register (flash descriptor memory mapped configuration registers) .............................................................................. 768 20.2.4 flash descriptor master section .............................................................. 7 69 20.2.4.1 flmstr1?flash master 1 (host proc essor/ bios)........................ 769 20.2.4.2 flmstr2?flash master 2 (me) ................................................. 769 20.2.4.3 flmstr3?flash master 3 (gbe)................................................ 770 20.2.5 flash descriptor strap ........................................................................ ... 771 20.2.5.1 strp0?strap 0 register (flash descriptor memory mapped configuration registers) .............................................................................. 771 20.2.5.2 strp1?strap 1 register (flash descriptor memory mapped configuration registers) .............................................................................. 772 20.2.5.3 flumap1?flash upper map 1 ................................................... 773 20.2.5.4 jid0?jedec-id 0 register ....................................................... 773 20.2.5.5 vscc0?vendor specific component capabilities 0....... .......... ...... 773 20.2.5.6 jid0?jedec-id n register ....................................................... 774 20.2.5.7 vscc0n?vendor specific component capabilities n ..................... 775 20.2.5.8 oem section ........................................................................... 776 20.3 gbe spi flash program registers ................................................................. ...... 776 20.3.1 glfpr?gigabit lan flash primary region register (gbe lan memory mapped configuration registers) .................................. 777 20.3.2 hsfs?hardware sequencing flash status register (gbe lan memory mapped configuration registers) .................................. 778 20.3.3 hsfc?hardware sequencing flash control register (gbe lan memory mapped configuration registers) .................................. 779 20.3.4 faddr?flash address register (gbe lan memory mapped configuration registers) .................................. 780 20.3.5 fdata0?flash data 0 register (gbe lan memory mapped configuration registers) .................................. 780 20.3.6 frap?flash regions access permissions register (gbe lan memory mapped configuration registers) .................................. 781 intel ? ich8 family datasheet 33 20.3.7 freg0?flash region 0 (flash descriptor) register (gbe lan memory mapped configuration registers) .................................. 782 20.3.8 freg1?flash region 1 (bios descriptor) register (gbe lan memory mapped configuration registers) .................................. 782 20.3.9 freg2?flash region 2 (me) register (gbe lan memory mapped configuration registers) .................................. 783 20.3.10freg3?flash region 3 (gbe) register (gbe lan memory mapped configuration registers) .................................. 783 20.3.11pr0?protected range 0 register (gbe lan memory mapped configuration registers) .................................. 784 20.3.12pr1?protected range 1 register (gbe lan memory mapped configuration registers) .................................. 784 20.3.13ssfs?software sequencing flash status register (gbe lan memory mapped configuration registers) .................................. 785 20.3.14ssfc?software sequencing flash control register (gbe lan memory mapped configuration registers) .................................. 786 20.3.15preop?prefix opcode configuration register (gbe lan memory mapped configuration registers) .................................. 787 20.3.16optype?opcode type configuration register (gbe lan memory mapped configuration registers) .................................. 787 20.3.17opmenu?opcode menu configuration register (gbe lan memory mapped configuration registers) .................................. 788 21 thermal sensor registers (d31:f6) ....................................................................... 789 21.1 pci bus configuration registers ................................................................. ....... 789 21.1.1 vid?vendor identification..................................................................... 790 21.1.2 did?device identification ..................................................................... 790 21.1.3 cmd?command .................................................................................. 7 90 21.1.4 sts?status .................................................................................... .... 791 21.1.5 rid?revision identification................................................................... 791 21.1.6 pi? programming interface ................................................................... 79 1 21.1.7 scc?sub class code ........................................................................... 7 92 21.1.8 bcc?base class code .......................................................................... 7 92 21.1.9 cls?cache line size........................................................................... . 792 21.1.10lt?latency timer............................................................................. ... 792 21.1.11htype?header type ............................................................................ 792 21.1.12bist?built-in self test ...................................................................... ... 793 21.1.13tbar?thermal base ............................................................................ 793 21.1.14tbarh?thermal base high dword......................................................... 793 21.1.15svid?subsystem vendor id ................................................................. 794 21.1.16sid?subsystem id ............................................................................. . 794 21.1.17cap_ptr ?capabilities pointer. ................ ............ ........... ........... ............ 794 21.1.18intln?interrupt line ......................................................................... .. 794 21.1.19intpn?interrupt pin .......................................................................... .. 795 21.1.20tbarb?bios assigned thermal base address ......................................... 795 21.1.21tbarbh?bios assigned thermal base high dword ................................. 795 21.1.22 pid?pci power management capability id .. .......... ........... ........... ............ 796 21.1.23pc?power management capa bilities ......... ............ ........... ........... ............ 796 21.1.24pcs?power management control and status ........................................... 797 21.2 thermal memory mapped configuration registers (thermal sensor - d31:f26)798 21.2.1 tsxe?thermal sensor [1:0] enable ....................................................... 798 21.2.2 tsxs?thermal sensor[1:0] status......................................................... 798 21.2.3 tsxttp?thermal sensor [1:0] catastrophic trip point .............................. 798 21.2.4 tsxco?thermal sensor [1:0] catastrophic lock-down............................. 799 21.2.5 tsxpc?thermal sensor [1:0] policy control ............................................ 799 34 intel ? ich8 family datasheet 21.2.6 tsxlock?thermal sensor [1:0] register lock control .............................. 799 22 ballout definition ................................................................................................... 8 01 22.1 ballout (desktop only) .......................................................................... ........... 801 22.2 ballout (mobile only)........................................................................... ............. 810 23 electrical characteristics ........................................................................................ 819 23.1 thermal specifications.......................................................................... ............ 819 23.2 absolute maximum ratings4 ....................................................................... ...... 819 23.3 dc characteristics .............................................................................. ............. 820 23.4 ac characteristics.............................................................................. .............. 832 23.5 timing diagrams ................................................................................. ............ 851 24 package information ............................................................................................. 867 24.1 package dimensions (desktop only)............................................................... .... 867 24.2 package dimensions (mobile only) ................................................................ ..... 869 a register bit index .................................................................................................. 87 2 intel ? ich8 family datasheet 35 figures desktop configuration ............................................................................... ............... 43 mobile configuration................................................................................ ................. 43 1 intel ? ich8 interface signals block diagram (desktop)................................................. 58 2 intel ? ich8 interface signals block diagram (mobile) ................................................... 59 3 example external rtc circuit....................................................................... .............. 90 4 desktop conceptual system clock diagram .......... ..................................................... 108 5 mobile conceptual clock diagram ........................ ..................................................... 108 6 generation of serr# to platform .................................................................... ......... 115 7 lpc interface diagram .............................................................................. .............. 124 8 intel ? ich8 dma controller ................................................................................ ..... 129 9 dma request assertion through ldrq# ................................................................ .... 132 10 coprocessor error timing diagram .................................................................. ......... 157 11 advanced tco intel? amt mode smbus/smlink configuration ..................................... 187 12 advanced tco bmc mode smbus/smlink configuration............................................... 188 13 physical region descriptor table entry............... ....................................................... 191 14 sata power states................................................................................. ................ 200 15 usb legacy keyboard flow diagram .................................................................. ....... 211 16 intel ? ich8-usb port connections .......................................................................... 218 17 flash descriptor.................................................................................. ................... 244 18 ballout (top view?left side) (desktop only)....................................................... ....... 802 19 ballout (top view?right side) (desktop only)...................................................... ...... 803 20 ballout (top view?left side) (mobile only) ........................................................ ........ 810 21 ballout (top view?right side) (mobile only) ....................................................... ....... 811 22 clock timing ...................................................................................... ................... 851 23 valid delay from rising clock edge.................... ....................................................... 851 24 setup and hold times.............................................................................. ............... 852 25 float delay....................................................................................... ..................... 852 26 pulse width ....................................................................................... .................... 852 27 output enable delay............................................................................... ................ 852 28 ide pio mode (mobile only) ........................................................................ ............ 853 29 ide multiword dma (mobile only) ................................................................... .......... 853 30 ultra ata mode (drive initiating a burst read) (mobile only) ...................................... . 854 31 ultra ata mode (sustained burst) (mobile only).................................................... ..... 854 32 ultra ata mode (pausing a dma burst) (mobile only) ................................................ .. 855 33 ultra ata mode (terminating a dma burst) (mobile only) ............................................ 855 34 usb rise and fall times........................................................................... ............... 856 35 usb jitter ........................................................................................ ..................... 856 36 usb eop width ..................................................................................... ................. 856 37 smbus transaction ................................................................................. ................ 857 38 smbus timeout..................................................................................... ................. 857 39 power sequencing and reset signal timings ......................................................... ..... 858 40 g3 (mechanical off) to s0 timings................................................................. ........... 859 41 s0 to s1 to s0 timing............................................................................. ................ 860 42 s0 to s5 to s0 timings, s3 (desktop only) ......................................................... ...... 860 43 s0 to s5 to s0 timings, s3 (mobile only) .................................................................. 861 44 c0 to c2 to c0 timings (mobile only) .............................................................. ......... 861 45 c0 to c3 to c0 timings (mobile only) .............................................................. ......... 862 46 c0 to c4 to c0 timings (mobile only) .............................................................. ......... 862 47 intel ? high definition audio input and output timings. ............................................... 863 48 spi timings....................................................................................... .................... 863 49 sleep control signal relationship ? host boots and me off ............................................. 864 50 sleep control signal relationship ? host and me boot after g3 ...................................... 864 51 sleep control signal relationship ? host stays in s5 and me boots after g3 ................... 865 36 intel ? ich8 family datasheet 52 s0 to g3 pwrok and vcc timing ..................................................................... ......... 865 53 s0 to g3 timings (mobile only) .................................................................... ............ 865 54 package dimensions (top view) (desktop only) ...................................................... ... 867 55 package dimensions (bottom view) (desktop only) ................................................... . 868 56 package dimensions (side view) (desktop only) ..................................................... ... 868 57 package dimensions (top view) (mobile only)....................................................... ..... 869 58 package dimensions (bottom view) (mobile only).................................................... ... 870 59 package dimensions (side view) (mobile only) ...................................................... ..... 870 tables 1 industry specifications ............................................................................ ..................45 2 pci devices and functions ................................ .........................................................49 3 intel ? ich8 desktop/server family ......................................................................... ...55 4 intel ? ich8 mobile family ................................................................................. ........55 5 direct media interface signals ..................................................................... ...............60 6 pci express* signals ............................................................................... .................60 7 lan connect interface signals...................................................................... ..............61 8 gigabit lan connect interface signals .............................................................. ...........61 9 firmware hub interface signals ..................................................................... .............62 10 pci interface signals ............................................................................. ...................63 11 serial ata interface signals ............................ ...........................................................66 12 ide interface signals (mobile only)............................................................... ..............68 13 lpc interface signals ............................................................................. ...................69 14 interrupt signals ................................................................................. .....................70 15 usb interface signals ............................................................................. ..................71 16 power management interface signals ................................................................ ..........72 17 processor interface signals ....................................................................... .................75 18 sm bus interface signals .......................................................................... .................77 19 system management interface signals ............................................................... .........77 20 real time clock interface ......................................................................... .................78 21 other clocks ...................................................................................... ......................79 22 miscellaneous signals............................................................................. ...................79 23 intel ? high definition audio link signals ................................................................. ....80 24 serial peripheral interface (spi) signals ............. .........................................................81 25 intel ? quick resume technology signals.................................................................... .82 26 controller link signals ........................................................................... ...................82 27 intel ? quiet system technology signals .................................................................... ..83 28 general purpose i/o signals ....................................................................... ...............83 29 power and ground signals .......................................................................... ...............86 30 functional strap definitions ......... ..............................................................................88 31 integrated pull-up and pull-down resistors........................................................ ..........91 32 ide series termination resistors .................................................................. ..............92 33 power plane and states for output and i/o sign als for desktop configurations .................93 34 power plane and states for output and i/o signal s for mobile configurations....................98 35 power plane for input signals for desktop configurations.......................................... ... 102 36 power plane for input signals for mobile configurations ........................................... .... 104 37 intel ? ich8 and system clock domains .................................................................... 10 7 38 pci bridge initiator cycle types .................................................................. ............. 109 39 type 1 address format ............................................................................. .............. 112 40 msi vs. pci irq actions ........................................................................... ............... 113 41 lan mode support.................................................................................. ................ 120 42 lpc cycle types supported......................................................................... ............. 125 43 start field bit definitions ....................................................................... .................. 125 44 cycle type bit definitions ........................................................................ ................ 126 intel ? ich8 family datasheet 37 45 transfer size bit definition ...................................................................... ................ 126 46 sync bit definition............................................................................... .................. 127 47 dma transfer size................................................................................. ................. 131 48 address shifting in 16-bit i/o dma transfers ...................................................... ....... 131 49 counter operating modes ........................................................................... ............. 137 50 interrupt controller core connections ............................................................. .......... 139 51 interrupt status registers ........................................................................ ............... 140 52 content of interrupt vector byte .................................................................. ............ 140 53 apic interrupt mapping ............................................................................ .............. 146 54 interrupt message address format .................................................................. ......... 148 55 interrupt message data format..................................................................... ........... 149 56 stop frame explanation ............................................................................ .............. 150 57 data frame format ................................................................................. ............... 151 58 configuration bits reset by rtcrst# assertion .... ..................................................... 154 59 init# going active ................................................................................ ................ 156 60 nmi sources....................................................................................... ................... 157 61 dp signal differences ............................................................................. ................ 158 62 general power states for systems using intel ? ich8.................................................. 160 63 state transition rules for intel ? ich8 ...................................................................... 161 64 system power plane ................................................................................ ............... 162 65 causes of smi# and sci ............................................................................ ............. 163 66 break events (mobile only) ........................................................................ ............. 166 67 sleep types ....................................................................................... ................... 170 68 causes of wake events ............................................................................. .............. 170 69 gpi wake events ................................................................................... ................ 171 70 transitions due to power failure .................................................................. ............ 172 71 transitions due to power button ................................................................... ........... 174 72 transitions due to ri# signal ..................................................................... ............. 175 73 write only registers with read paths in alt access mode ........................................... 178 74 pic reserved bits return values ................................................................... ........... 180 75 register write accesses in alt access mode ........................................................ ...... 180 76 intel ? ich8 clock inputs .................................................................................. ...... 182 77 tco legacy/compatible mode smbus configuration .................................................... 186 78 event transitions that cause messages ............................................................. ........ 186 79 ide transaction timings (pci clocks) ............... ....................................................... 190 80 interrupt/active bit interaction definition ....................................................... ........... 193 81 sata feature support .............................................................................. .............. 196 82 sata feature support .............................................................................. .............. 197 83 legacy replacement routing ........................................................................ ........... 203 84 bits maintained in low power states .................. ....................................................... 210 85 usb legacy keyboard state transitions ............... ..................................................... 211 86 uhci vs. ehci ..................................................................................... .................. 213 87 debug port behavior ............................................................................... ............... 221 88 i 2 c block read ........................................................................................ .............. 228 89 enable for smbalert# .............................................................................. ............. 231 90 enables for smbus slave write and smbus host events ............................................... 231 91 enables for the host notify command ............................................................... ........ 231 92 slave write registers ............................................................................. ................ 233 93 command types ..................................................................................... ............... 234 94 slave read cycle format ........................................................................... ............. 235 95 data values for slave read registers................. ....................................................... 235 96 host notify format ................................................................................ ................. 237 97 required commands and opcodes..................................................................... ....... 247 98 recommended command and opcode associations .................................................... 248 99 pci devices and functions......................................................................... .............. 256 38 intel ? ich8 family datasheet 100 fixed i/o ranges decoded by intel ? ich8 ................................................................. 258 101 variable i/o decode ranges....................................................................... .............. 260 102 memory decode ranges from processor perspective.................................................. .. 261 103 chipset configuration register memory map (memory space) ....................................... 26 5 104 gigabit lan configuration registers address map (gigabit lan ?d25:f0) ............................................................................... ............ 309 105 lpc interface pci register address map (lpc i/f?d31:f0) .......................................... 323 106 dma registers .................................................................................... ................... 344 107 pic registers (lpc i/f?d31:f0)................................................................... ............ 356 108 apic direct registers (lpc i/f?d31:f0)........................................................... ......... 364 109 apic indirect registers (lpc i/f?d31:f0) ......................................................... ........ 364 110 rtc i/o registers (lpc i/f?d31:f0) ............................................................... ......... 369 111 rtc (standard) ram bank (lpc i/f?d31:f0)......................................................... .... 370 112 processor interface pci register address map (lpc i/f?d31:f0).................................. 37 4 113 power management pci register address map (pm?d31:f0) ....................................... 377 114 apm register map................................................................................. .................. 390 115 acpi and legacy i/o register map ................................................................. ........... 391 116 tco i/o register address map ..................................................................... ............ 416 117 registers to control gpio address map ............................................................ ......... 423 118 pci bridge register address map (pci-pci?d30:f0) ................................................. .. 431 119 ide controller pci register address map (ide-d31:f1) ............................................. .. 447 120 bus master ide i/o registers ..................................................................... .............. 462 121 sata controller pci register address map (sata?d31:f2) .......................................... 4 65 122 sata indexed registers ........................................................................... ............... 491 123 bus master ide i/o register address map .......................................................... ........ 502 124 ahci register address map........................................................................ .............. 512 125 generic host controller register address map ..................................................... ....... 513 126 port [3:0] dma register address map.............................................................. .......... 521 127 sata controller pci register address map (sata?d31:f5) .......................................... 5 39 128 bus master ide i/o register address map .......................................................... ........ 556 129 uhci controller pci configuration map ............................................................ .......... 565 130 uhci controller pci register address map (usb?d29:f0/f1/f2, d26:f0/f1) ................. 565 131 usb i/o registers ................................................................................ .................. 575 132 run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation .................. 578 133 usb ehci pci register address map (usb ehci?d29:f7, d26:f7) ............................... 585 134 enhanced host controller capability registers ....... ........... .......... ........... ........ ............. 603 135 enhanced host controller operational register ad dress map......................................... 607 136 debug port register address map .................................................................. ........... 620 137 smbus controller pci register address map (smbus?d31:f3) ..................................... 625 138 smbus i/o and memory mapped i/o register address map .......................................... 631 139 intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) ...................................................................... . 643 140 intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) ...................................................................... . 666 141 pci express* configuration registers address map (pci express?d28:f0/f1/f2/f3/f4/f5) ................................................................. .... 697 142 memory-mapped registers.......................................................................... ............. 741 143 serial peripheral interface (spi) register address map (spi memory mapped configuration registers) ......................................................... .. 747 144 gigabit lan spi flash program register address map (gbe lan memory mapped configuration registers) .................................................... 7 76 145 thermal sensor register address map (d31:f6) ..................................................... .... 789 146 ballout by signal name (desktop only) ............................................................ ......... 804 147 ballout by signal name (mobile only)............................................................. ........... 812 148 intel ? ich8 absolute maximum ratings..................................................................... 8 19 intel ? ich8 family datasheet 39 149 dc current characteristics (desktop only) ........................................................ ........ 820 150 dc current characteristics (mobile only)......................................................... .......... 821 151 dc characteristic input signal association ........... ...................................................... 822 152 dc input characteristics ......................................................................... ................ 823 153 dc characteristic output signal association............................................................... 826 154 dc output characteristics .............................. ......................................................... 828 155 other dc characteristics ......................................................................... ................ 830 156 clock timings .................................................................................... .................... 832 157 pci interface timing............................................................................. .................. 834 158 ide pio mode timings (mobile only)............................................................... .......... 835 159 ide multiword dma timings (mobile only) .......................................................... ....... 836 160 ultra ata timing (mode 0, mode 1, mode 2) (mobile only).......................................... 836 161 ultra ata timing (mode 3, mode 4, mode 5) (mobile only)......................................... 839 162 universal serial bus timing ............................ ......................................................... 841 163 sata interface timings........................................................................... ................ 842 164 smbus timing..................................................................................... ................... 842 166 lpc timing....................................................................................... ..................... 843 167 miscellaneous timings ............................................................................ ................ 843 165 intel ? high definition audio timing ....................................................................... ... 843 168 spi timings (20 mhz) ............................................................................. ................ 844 169 spi timings (33 mhz) ............................................................................. ................ 844 170 sst timings (desktop only) ....................................................................... ............ 845 171 peci timings (desktop only) ...................................................................... ............. 845 172 power sequencing and reset signal timings ........................................................ ...... 846 173 power management timings ......................................................................... ........... 848 40 intel ? ich8 family datasheet revision history revision description date -001 ? initial release. june 2006 -002 ? added 82801hdh ich8 digital home (ich 8dh) and 82801hdo ich8 digital office (ich8do) july 2006 -003 ? added intel ? 82801hbm ich8 mobile (ich8m) and intel ? 82801hem ich8 mobile enhanced (ich8m-e) ? added documentation changes, specification changes, and specification clarifications from specification update, rev -008. may 2007 intel ? ich8 family datasheet 41 intel ? ich8 features direct media interface ? 10 gb/s each direction, full duplex ? transparent to software pci express* ? 6 pci express root ports ? supports pci express 1.1 ? ports 1-4 can be statically configured as four x1 or one x4 ? support for full 2.5 gb/s bandwidth in each direction per x1 lane ? module based hot-plug supported (e.g., expresscard*) pci bus interface ? supports pci rev 2.3 specification at 33 mhz ? four available pci req/gnt pairs ? support for 64-bit addressing on pci using dac protocol integrated serial ata host controller ? new: up to six sata ports (mobile has 3 ports) ? new: external sata support (desktop only) ? data transfer rates up to 3.0 gb/s (300 mb/s). ? integrated ahci controller intel ? matrix storage technology (ich8r, ich8dh, ich8do, ich8m-e only) ? configures the ich8 sata controller as a raid controller supporting raid 0/1/5/10 in the ich8r, ich8dh, ich8do, and supporting raid 0/1 in the ich8m-e integrated ide controller (mobile only) ? independent timing of up to two drives ? ultra ata/100/66/33, bmide and pio modes ? tri-state modes to enable swap bay new:intel ? active management technology with system defense (ich8do and ich8m-e only) intel ? high definition audio interface ? pci express endpoint ? independent bus master logic for eight general purpose streams: four input and four output ? support four external codecs ? supports variable length stream slots ? supports multichannel, 32-bit sample depth, 192 khz sample rate output ? provides mic array support ? allows for non-48 khz sampling output ? support for acpi device states ? low voltage mode ? docking support (mobile only) new: intel ? quiet system technology (desktop only) ? four tach signals and three pwm signals new: simple serial transport (sst) bus and platform environmental control interface (peci) (desktop only) usb 2.0 ? new: up to five uhci host controllers, supporting ten external ports ? new: up to two ehci host controllers that supports ten ports ? new: includes up to two usb 2.0 high-speed debug ports ? supports wake-up from sleeping states s1?s5 ? supports legacy keyboard/mouse software new: integrated gigabit lan controller ? integrated asf management controller ? new: network security with system defense ? supports ieee 802.3 ? lan connect interface (lci) and new gigabit lan connect interface (glci) ? 10/100/1000 mb/s ethernet support 42 intel ? ich8 family datasheet note: not all features are availabl e on all ich8 components. see section 1.2 for more details. power management logic ? supports acpi 3.0 ? acpi-defined power states (c1, s1, s3?s5 for desktop and c1?c4, s1, s3?s5 for mobile) ? acpi power management timer ? (mobile only) support for ?intel speedstep ? technology? processor power control and ?deeper sleep? power state ? pci clkrun# (mobile only) and pme# support ? smi# generation ? all registers readable/restorable for proper resume from 0 v suspend states external glue integration ? integrated pull-up, pull-down and series termination resistors on ide (mobile only), processor interface ? integrated pull-down and series resistors on usb smbus ? new: faster speed, up to 100 kbps ? flexible smbus/smlink architecture to optimize for asf ? provides independent manageability bus through smlink interface ? supports smbus 2.0 specification ? host interface allows processor to communicate via smbus ? slave interface allows an internal or external microcontroller to access system resources ? compatible with most two-wire components that are also i 2 c compatible high precision event timers ? advanced operating system interrupt scheduling timers based on 82c54 ? system timer, refresh request, speaker tone output real-time clock ? 256-byte battery-backed cmos ram ? integrated oscillator components ? lower power dc/dc converter implementation system tco reduction circuits ? timers to generate smi# and reset upon detection of system hang ? timers to detect improper processor reset ? integrated processor frequency strap logic ? supports ability to disable external devices enhanced dma controller ? two cascaded 8237 dma controllers ? supports lpc dma interrupt controller ? supports up to eight pci interrupt pins ? supports pci 2.3 message signaled interrupts ? two cascaded 82c59 with 15 interrupts ? integrated i/o apic capability with 24 interrupts ? supports processor system bus interrupt delivery 1.05 v operation with 1.5 v and 3.3 v i/o ? 5 v tolerant buffers on ide (mobile only), pci, usb, and selected legacy signals 1.05 v core voltage new: five integrated voltage regulators for different power rails firmware hub i/f supports bios memory size up to 8 mb serial peripheral interface (spi) ? new: supports up to two spi devices ? new: supports 20 mhz and 33 mhz spi devices low pin count (lpc) i/f ? supports two master/dma devices. ? support for security device (trusted platform module) connected to lpc. gpio ? ttl, open-drain, inversion package ? 31x31 mm 652 mbga (desktop only) ? 31x31 mm 676 mbga (mobile only) intel ? ich8 family datasheet 43 desktop configuration mobile configuration spi bios spi flash intel ? gigabit ethernet phy intel ? ich8 usb 2.0 (supports 10 usb ports dual ehci controller) system management (tco) gpio smbus 2.0/i 2 c power management pci bus ... clock generators s l o t s l o t intel? high definition audio codec(s) firmware hub other asics (optional) lpc i/f super i/o sata (6 ports) pci express* x1 dmi (to (g)mch) tpm (optional) lci glci in te l ? ic h 8 m u s b 2 .0 (s u p p o rts 1 0 u s b p o rts d u a l e h c i c o n tr o lle rs ) s y s te m m a n a g e m e n t ( t c o ) id e g p io s m b u s 2 .0 /i 2 c p o w e r m a n a g e m e n t p c i b u s c lo c k g e n e r a to r s c a rd b u s c o n tr o lle r (& a tta c h e d s lo ts ) d m i ( t o (g ) m c h ) in te l? g b e p h y in te l? h ig h d e fin itio n a u d io c o d e c (s ) f la s h b io s o th e r a s ic s (o p tio n a l) l p c i/f s u p e r i/o s a t a ( 3 p o rts ) d o c k in g b rid g e p c i e x p r e s s x 1 t p m (o p tio n a l) g l c i l c i s p i f la s h 44 intel ? ich8 family datasheet intel ? ich8 family datasheet 45 introduction 1 introduction this document is intended for original equipment manufacturers and bios vendors creating intel ? i/o controller hub 8 (ich8) family based products. this document is the datasheet for the following: ? intel ? 82801hb ich8 (ich8) ? intel ? 82801hr ich8 raid (ich8r) ? intel ? 82801hdh ich8 digital home (ich8dh) ? intel ? 82801hdo ich8 digital office (ich8do) ? intel ? 82801hbm ich8 mobile (ich8m) ? intel ? 82801hem ich8 mobile enhanced (ich8m-e) section 1.2 provides high-level feature differen ces for the ich8 family components. note: throughout this datasheet, ich8 is used as a general ich8 term and refers to the 82801hb ich8 and 82801hr ich8r 828 01hdh ich8dh, 82 801hdo ich8do, 82801hbm ich8m, and 82801hem ich8m-e co mponents, unless specifically noted otherwise. note: throughout this datasheet, the term ?desktop? refers to any implementation, be it in a desktop, server, workstation, etc., unless specifically noted otherwise. note: throughout this datasheet, the term ?desktop only? refers to information that is for the 82801hb ich8, 82801hr ich8r, 82801hdh ich8dh, and 82801hdo ich8do unless specifically noted otherwise. the term ?digital home only? refers to information that is for the 82801hdh ich8dh, unless specifically no ted otherwise. the term ?digital office only? refers to information that is for th e 82801hdo ich8do, unless specifically noted otherwise. the term ?mobile only? refers to information that is for both the 82801hbm ich8m and 82801hem ich8m-e, unless noted otherwise. this datasheet is intended for original equipment manufacturers and bios vendors creating intel ? ich8 family-based products. this manual assumes a working knowledge of the vocabulary and principles of pci express*, usb, ide (mobile only), ahci, sata, intel ? high definition audio (intel ? hd audio), smbus, pci, acpi and lpc. although some details of these features are described within this manual, refer to the individual industry specifications listed in table 1 for the complete details. table 1. industry specifications specification location intel ? i/o controller hub 8 (ich8) family specification update http://www.intel.com/design/ chipsets/specupdt/313057.htm pci express* base specification, revision 1.1 http://www.pcisig.com/specifications low pin count interface spec ification, revision 1.1 (lpc) http://developer.intel.com/design/ chipsets/industry/lpc.htm system management bus specification, version 2.0 (smbus) http://www.smbus.org/specs/ pci local bus specification, revision 2.3 (pci) http://www.pcisig.com/specifications pci mobile design guide, revision 1.1 http://www.pcisig.com/specifications pci power management specification, revision 1.1 http://www.pcisig.com/specifications introduction 46 intel ? ich8 family datasheet chapter 1. introduction chapter 1 introduces the ich8 and provides information on manual organization and gives a general overview of the ich8. chapter 2. signal description chapter 2 provides a block diagram of the ich8 and a detailed description of each signal. signals are arranged according to interface and details are provided as to the drive characteristics (input/output, open drain, etc.) of all signals. chapter 3. intel ? ich8 pin states chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and thei r logic level before and after reset. chapter 4. intel ? ich8 and system clock domains chapter 4 provides a list of each clock domain associated with the ich8 in an ich8 based system. chapter 5. functional description chapter 5 provides a detailed description of the functions in the ich8. all pci buses, devices and functions in this manual are abbreviated using the following nomenclature; bus:device:function. this manual abbreviates buses as b0 and b1, devices as d8, d27, d28, d29, d30 and d31 and functions as f0, f1, f2, f3, f4, f5, f6 and f7. for example device 31 function 0 is abbreviated as d31:f0, bus 1 device 8 function 0 is abbreviated as b1:d8:f0. generally, the bus number will not be used, and can be considered to be bus 0. note that the ich8 ?s external pci bus is typically bus 1, but may be assigned a different number depending upon system configuration. chapter 6. register and memory mappings chapter 6 provides an overview of the registers, fixed i/o ranges, variable i/o ranges and memory ranges decoded by the ich8. chapter 7. chipset configuration registers chapter 7 provides a detailed description of all registers and base functionality that is related to chipset configuration and not a spec ific interface (such as lpc, pci, or pci express). it contains the root complex register block, which describes the behavior of the upstream internal link. universal serial bus specification (usb), re vision 2.0 http://www.usb.org/developers/docs advanced configuration and power interface, version 2.0 (acpi) http://www.acpi.info/spec.htm universal host controller in terface, revision 1.1 (uhci) http://developer.intel.com/design/ usb/uhci11d.htm enhanced host controller interface specification for universal serial bus, revision 1.0 (ehci) http://developer.intel.com/ technology/usb/ehcispec.htm serial ata specification, revision 2.5 http://www.serialata.org/ specifications.asp alert standard format specif ication, version 1.03 http://www.dmtf.org/standards/asf ieee 802.3 fast ethernet http://standards.ieee.org/ getieee802/ at attachment - 6 with packet interface (ata/atapi - 6) http://t13.org (t13 1410d) ia-pc hpet (high precision event timers) specification, revision 0.98a http://www.intel.com/ hardwaredesign/hpetspec.htm table 1. industry specifications specification location intel ? ich8 family datasheet 47 introduction chapter 8. integrated lan controller registers chapter 8 provides a detailed description of all registers that reside in the ich8?s integrated lan controller. the integrated la n controller resides at device 25, function 0 (d25:f0). chapter 9. lpc bridge registers chapter 9 provides a detailed description of all registers that reside in the lpc bridge. this bridge resides at device 31, function 0 (d31:f0). this function contains registers for many different units within the ich8 in cluding dma, timers, interrupts, processor interface, gpio, power manageme nt, system management and rtc. chapter 10. pci-to-pci bridge registers chapter 10 provides a detailed description of all registers that reside in the pci-to-pci bridge. this bridge resides at device 30, function 0 (d30:f0). chapter 11. ide controller registers (mobile only) chapter 11 provides a detailed description of all registers that reside in the ide controller. this controller resides at device 31, function 1 (d31:f1). chapter 11. sata controller registers chapter 12 provides a detailed description of all registers that reside in the sata controller #1. this controller resides at device 31, function 2 (d31:f2). chapter 12. sata controller registers chapter 13 provides a detailed description of all registers that reside in the sata controller #2. this controller resides at device 31, function 5 (d31:f5). chapter 13. uhci controller registers chapter 14 provides a detailed description of all registers that reside in the five uhci host controllers. these controllers reside at device 29, functions 0, 1, 2, and 3 (d29:f0/f1/f2/f3) and device 26, function 1 (d26:f1) chapter 14. ehci controller registers chapter 15 provides a detailed description of all registers that reside in the ehci host controllers. this controller resides at device 29, function 7 (d29:f7) and device 26, function 7 (d26:f7) chapter 15. smbus controller registers chapter 16 provides a detailed description of all registers that reside in the smbus controller. this controller resides at device 31, function 3 (d31:f3). chapter 16. intel ? high definition audio controller registers chapter 17 provides a detailed description of all registers that reside in the intel high definition audio controller. this controller resides at device 27, function 0 (d27:f0). chapter 17. pci express* po rt controller registers chapter 18 provides a detailed description of all registers that reside in the pci express controller. this controller resides at device 28, functions 0 to 5(d30:f0-f5). chapter 18. high precision event timers registers chapter 19 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. chapter 19. serial periph eral interface registers chapter 20 provides a detailed description of all registers that reside in the spi memory mapped register space. chapter 20. thermal sensors chapter 21 provides a detailed description of all registers that reside in the thermal sensors pci configuration space. the registers reside at device 31, function 6 (d31:f6). introduction 48 intel ? ich8 family datasheet chapter 21. ballout definition chapter 22 provides a table of each signal and its ball assignment in the 652-mbga package. chapter 22. electrical characteristics chapter 23 provides all ac and dc characteristics including detailed timing diagrams. chapter 24. package information chapter 24 provides drawings of the physical dimensions and characteristics of the 652-mbga package. appendix a. index this volume ends with indexes of registers and register bits. 1.1 overview the ich8 provides extensive i/o suppo rt. functions and capabilities include: ? pci express* base specification, revision 1.1 support ? pci local bus specification , revision 2.3 support for 33 mhz pci operations ( supports up to four req/gnt pairs). ? acpi power management logic support ? enhanced dma controller, interrupt controller, and timer functions ? integrated serial ata host controllers with independent dma operation on up to six ports (desktop only) or three ports (mobile only) and ahci support. ? integrated ide controller supports ultra ata100/66/33 (mobile only) ? usb host interface with support for up to ten usb ports; five uhci host controllers; two ehci high-speed usb 2.0 host controllers ? integrated 10/100/1000 gbe mac with system defense ? system management bus (smbus) specification , version 2.0 with additional support for i 2 c devices) ? supports intel high definition audio ? supports intel ? matrix storage technology (ich8, ich8dh, ich8do, and ich8m-e only) ? supports intel ? active management technology (ich8do and ich8m-e only) ? low pin count (lpc) interface ? firmware hub (fwh) interface support ? serial peripheral interface (spi) support ? intel ? quiet system technology (desktop only) the intel ich8 incorporates a variety of pci devices and functions, as shown in table 2 . they are divided into seven logical devices. the first device is the dmi-to-pci bridge (device 30). the second device (device 31) contains most of the standard pci functions that have existed in legacy pci-to -isa bridges (south bridges). the third and fourth devices (device 29 and device 26) are the usb host controller devices. the fifth device (device 28) is pci express device. the sixth device (device 27) is the intel hd audio controller device, and the seventh device (device 25) is the gbe controller device. intel ? ich8 family datasheet 49 introduction notes: 1. the pci-to-lpc bridge contains registers that control lpc, powe r management, system management, gpio, processor interface , rtc, interrupts, timers, and dma. the following sub-sections provide an overview of ich8 capabilities. direct media interface (dmi) direct media interface (dmi) is the chip-to-chip connection between the memory controller hub / graphics memory controller hub ((g)mch) and i/o controller hub 8 (ich8). this high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. base functionality is completely software-transparent, permitting current and legacy software to operate normally. pci express* interface the ich8 provides up to 6 pci express root ports, supporting the pci express base specification, revision 1.1. each root port supports 2.5 gb/s bandwidth in each direction (5 gb/s concurrent). pci express root ports 1?4 can be statically configured as four x1 ports or ganged together to form one x4 port. ports 5 and 6 can only be used as two x1 ports. on mobile platforms, pci express ports 1?4 can also be configured as one x2 port (using ports 1 and 2) with ports 3 and 4 configured as x1 ports. table 2. pci devices and functions bus:device:function f unction description bus 0:device 30:functi on 0 pci-to-pci bridge bus 0:device 31:functi on 0 lpc controller 1 bus 0:device 31:function 1 ide controller (mobile only) bus 0:device 31:function 2 sata controller 1 bus 0:device 31:function 5 sata controller 2 bus 0:device 31:function 6 thermal subsystem bus 0:device 31:functi on 3 smbus controller bus 0:device 29:function 0 usb fs/ls uhci controller 1 bus 0:device 29:function 1 usb fs/ls uhci controller 2 bus 0:device 29:function 2 usb fs/ls uhci controller 3 bus 0:device 29:function 7 u sb hs ehci controller 1 bus 0:device 26:function 0 usb fs/ls uhci controller 4 bus 0:device 26:function 1 usb fs/ls uhci controller 5 bus 0:device 26:fucntion 7 u sb hs ehci controller 2 bus 0:device 28:function 0 pci express* port 1 bus 0:device 28:function 1 pci express port 2 bus 0:device 28:function 2 pci express port 3 bus 0:device 28:function 3 pci express port 4 bus 0:device 28:function 4 pci express port 5 bus 0:device 28:function 5 pci express port 6 bus 0:device 27:function 0 intel ? high definition audio controller bus 0:device 25:function 0 gbe controller introduction 50 intel ? ich8 family datasheet note: the integrated gbe controllers data lines fo r 1000 mb/s speed are multiplexed with pci express* root port 6 and, therefore, unava ilable if a gigabit ethernet phy is connected. the use of a 10/100 mb/s phy does not consume pci express root port 6 and, therefore, the port is available to be used as a x1 port. serial ata (sata) controller the ich8 has integrated sata host controllers that supports independent dma operation on up to six ports (desktop only ) or three ports (mobile only) and supports data transfer rates of up to 3.0 gb/s (300 mb/s). the sata controller contains two modes of operation ? a legacy mode using i/o space, and an ahci mode using memory space. sata and pata (mobile only) can also be used in a combined function mode (where the sata function is used with pata ). in this combined function mode, ahci mode is not used. software that uses legacy mode will not have ahci capabilities. the ich8 supports the serial ata specification , revision 2.5. the ich8 also supports several optional sections of the serial ata ii: extensions to serial ata 1.0 specification , revision 1.0 (ahci support is required for some elements). note: sata ports 2 and 3 are not on the ich8 base product. see section 1.2 for details on product feature availability. ahci the ich8 provides hardware support for advanced host controller interface (ahci), a new programming interface for sata host controllers. platforms supporting ahci may take advantage of performance features such as no master/slave designation for sata devices?each device is treated as a master?and hardware-assisted native command queuing. ahci also provides usability enhancements such as hot-plug. ahci requires appropriate software support (e.g., an ahci driver) and for some features, hardware support in the sata device or additional platform hardware. intel matrix storage technology (intel ? ich8r, ich8dh, ich8do , and ich8m-e only) the ich8 provides support for intel matrix storage technology, providing both ahci (see above for details on ahci) and integrated raid functionality. the industry-leading raid capability provides high-performance raid 0, 1, 5, and 10 functionality on up to 6 sata ports of ich8. matrix raid support is provided to allow multiple raid levels to be combined on a single set of hard drives , such as raid 0 and raid 1 on two disks. other raid features include hot spare support, smart alerting, and raid 0 auto replace. software components include an option rom for pre-boot configuration and boot functionality, a microsoft windows co mpatible driver, and a user interface for configuration and management of the raid capability of ich8. note that ich8m-e supports only raid 0 and raid 1. pci interface the ich8 pci interface provides a 33 mhz, revision 2.3 implementation. the ich8 integrates a pci arbiter that supports up to four external pci bus masters in addition to the internal ich8 requests. this allows for combinations of up to four pci down devices and pci slots. intel ? ich8 family datasheet 51 introduction ide interface (bus master capability and synchronous dma mode) (mobile only) the fast ide interface supports up to two ide devices providing an interface for ide hard disks and atapi devices. each ide device can have independent timings. the ide interface supports pio ide transfers up to 16 mb/sec and ultra ata transfers up 100 mb/sec. it does not consume any legacy dma resources. the ide interface integrates 16x32-bit buffers for optimal transfers. the ich8?s ide system contains a single, independent ide signal channel that can be electrically isolated. there are integrated se ries resistors on the data and control lines (see section 5.17 for details). see section 1.2 for details on component feature availability. low pin count (lpc) interface the ich8 implements an lpc interface as described in the lpc 1.1 specification . the low pin count (lpc) bridge function of the ic h8 resides in pci device 31:function 0. in addition to the lpc bridge interface functi on, d31:f0 contains other functional units including dma, interrupt co ntrollers, timers, power management, system management, gpio, and rtc. serial peripheral interface (spi) the ich8 implements an spi interface as an alternative interface for the bios flash device. an spi flash device can be used as a replacement for the fwh, and is required to support intel active management tec hnology (ich8do and ich8m-e only) and the integrated fan speed control (intel ? quiet system technology) (desktop only). the ich8 supports up to two spi flash devices with speeds up to 33 mhz using two chip select pins. compatibility modules (dma contro ller, timer/coun ters, interrupt controller) the dma controller incorporates the logic of two 82c37 dma controllers, with seven independently programmable channels. channels 0?3 are hardwired to 8-bit, count-by- byte transfers, and channels 5?7 are hardwired to 16-bit, count-by-word transfers. any two of the seven dma channels can be prog rammed to support fast type-f transfers. the ich8 supports lpc dma, which is sim ilar to isa dma, through the ich8?s dma controller. lpc dma is handled through the use of the ldrq# lines from peripherals and special encoding on lad[3:0] from the host. single, demand, verify, and increment modes are supported on the lpc in terface. channels 0?3 are 8-bit channels. channels 5?7 are 16-bit channels. channel 4 is reserved as a generic bus master request. the timer/counter block contains three counters that are equivalent in function to those found in one 82c54 programmable interval timer. these three counters are combined to provide the system timer function, and speaker tone. the 14.31818 mhz oscillator input provides the clock source for these three counters. the ich8 provides an isa-compatible prog rammable interrupt controller (pic) that incorporates the functionality of two, 82c59 interrupt controllers. the two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. in addition, the ich8 supports a serial interrupt scheme. all of the registers in these modules can be read and restored. this is required to save and restore system state after power has been removed and restored to the platform. introduction 52 intel ? ich8 family datasheet advanced programmable interrupt controller (apic) in addition to the standard isa compatible programmable interrupt controller (pic) described in the previous section, the ich8 incorporates the advanced programmable interrupt controller (apic). universal serial bus (usb) controllers the ich8 contains up to two enhanced host controller interface (ehci) host controllers that support usb high-speed signaling. high-s peed usb 2.0 allows data transfers up to 480 mb/s which is 40 times faster than full-speed usb. the ich8 also contains up to five universal host controller interface (uhc i) controllers that support usb full-speed and low-speed signaling. the ich8 supports up to ten usb 2.0 ports. all ten ports are high-speed, full-speed, and low-speed capable. ich8?s port-routing logic determines whether a usb port is controlled by one of the uhci or ehci controllers. see section 5.18 and section 5.19 for details. gigabit ethernet controller the gigabit ethernet controller provides a system interface via a pci function. the controller provides a full memory-mapped or io mapped interface along with a 64 bit address master support for systems using mo re than 4 gb of physical memory and dma (direct memory addressing) mechanisms for high performance data transfers. its bus master capabilities enable the compon ent to process high-level commands and perform multiple operations; this lowe rs processor utilization by off-loading communication tasks from the processor. two large configurable transmit and receive fifos (up to 16 kb each) help prevent data underruns and overruns while waiting for bus accesses. this enables the integrated lan controller to transmit data with minimum interframe spacing (ifs). the lan controller can operate at multiple speeds (10/100/1000 mb/s) and in either full duplex or half duplex mode. in full dupl ex mode the lan controller adheres with the ieee 802.3x flow control specification. half duplex performance is enhanced by a proprietary collision reduction mechanism. see section 5.3 for details. rtc the ich8 contains a motorola mc146818a-compa tible real-time clock with 256 bytes of battery-backed ram. the real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. the rtc operates on a 32.768 khz crystal and a 3 v battery. the rtc also supports two lockable memory ranges. by setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. this prevents unauthorized reading of passwords or other system security information. the rtc also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. gpio various general purpose inputs and outputs are provided for custom system design. the number of inputs and outputs varies depending on ich8 configuration. intel ? ich8 family datasheet 53 introduction enhanced power management the ich8?s power management functions include enhanced clock control and various low-power (suspend) states (e.g., suspend- to-ram and suspend-to-disk). a hardware- based thermal management circuit permits software-independent entrance to low- power states. the ich8 contains full support for the advanced configuration and power interface (acpi) specification, revision 2.0. intel ? quick resume technology (qrt) (intel ? ich8dh only) ich8dh implements intel quick resume tec hnology (qrt) to give the pc a consumer electronics device-like feel. intel qrt provides the capability to design a pc with a single power button that reliably and instantl y (user's perception) turns the pc on and off. when the system is on and the user presses the power button, the display instantly goes dark, sound is muted, and there is no response to keyboard/mouse commands (except for keyboard power button). when the system is off and the user presses the power button, picture and sound quickly return, and the keyboard/mouse return to normal functionality, allowing user input. intel ? active management technology (intel ? amt) (intel ? ich8do and ich8m-e only) intel active management technology is the next generation of client manageability via the wired network. intel amt is a set of ad vanced manageability features developed as a direct result of it customer feedback gained through intel market research. with the new implementation of system defense in ich8, the advanced manageability feature set of intel amt is further enhanced. manageability in addition to intel amt the ich8 integrates several functions designed to manage the system and lower the total cost of ownership (tco) of the system. these system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller. ? tco timer. the ich8?s integrated programmab le tco timer is used to detect system locks. the first expiration of the timer generates an smi# that the system can use to recover from a software lock. the second expiration of the timer causes a system reset to recover from a hardware lock. ? processor present indicator. the ich8 looks for the processor to fetch the first instruction after reset. if the processor does not fetch the first instruction, the ich8 will reboot the system. ? ecc error reporting. when detecting an ecc error, the host controller has the ability to send one of several messages to the ich8. the host controller can instruct the ich8 to generate either an smi#, nmi, serr#, or tco interrupt. ? function disable. the ich8 provides the ability to disable the following integrated functions: ide, lan, usb, lpc, intel hd audio, sata, or smbus. once disabled, these functions no longer decode i/o, memory, or pci configuration space. also, no interrupts or power management events are generated from the disabled functions. ? intruder detect. the ich8 provides an input signal (intruder#) that can be attached to a switch that is activated by the system case being opened. the ich8 can be programmed to generate an smi# or tco interrupt due to an active intruder# signal. note: asf functionality with the integrated ich8 asf controller requires a correctly configured system, including an approp riate (g)mch with me, me firmware, system bios support, and appropriate platform lan connect device. introduction 54 intel ? ich8 family datasheet system management bus (smbus 2.0) the ich8 contains an smbus host interface that allows the processor to communicate with smbus slaves. this interface is compatible with most i 2 c devices. special i 2 c commands are implemented. the ich8?s smbus host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves). also, the ich8 supports slave functionality, including the host notify pr otocol. hence, the host controller supports eight command protocols of the smbus interface (see system management bus (smbus) specification, version 2.0): quick command, se nd byte, receive byte, write byte/word, read byte/word, process ca ll, block read/write, and host notify. ich8?s smbus also implements hardware-based packet error checking for data robustness and the address resolution protoc ol (arp) to dynamically provide address to all smbus devices. intel ? high definition audio controller the intel ? high definition audio specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. the ich8 intel hd audio controller supports up to 4 codecs. the link can operate at either 3.3 v or 1.5 v. with the support of multi-channel audio stre am, 32-bit sample depth, and sample rate up to 192 khz, the intel hd audio controller provides audio quality that can deliver ce levels of audio experience. on the input si de, the ich8 adds support for an array of microphones. intel ? quiet system technology (desktop only) the ich8 integrates four fan speed sensors (four tach signals) and 3 fan speed controllers (three pulse width modulator (pwm) signals), which enables monitoring and controlling up to four fans on the system. with the new implementation of the single- wire simple serial transport (sst) bus and platform environmental control interface (peci), the ich8 provides an easy way to connect to sst-based thermal sensors and access the processor thermal data. in addi tion, coupled with th e new sophisticated intel ? quiet system technology algorithms, the ich8 integrated fan speed control provides effective thermal and acoustic management for the platform. note: intel ? quiet system technology functionality requires a correctly configured system, including an appropriate (g)mch with me, me firmware, and system bios support. intel ? ich8 family datasheet 55 introduction 1.2 intel ? ich8 family high-level component differences notes: 1. table above shows feature diffe rences between ich8 family components. if a feature is not listed in the table it is considered a base feat ure that is included in all family components. 2. product feature capability can be read in d31:f0, offset e4h. 3. sata ports 2 and 3 are not available in the desktop ich8 base component. notes: 1. table above shows feature diffe rences between ich8 family components. if a feature is not listed in the table it is considered a base feat ure that is included in all family components. 2. product feature capability can be read in d31:f0:offset e4h. table 3. intel ? ich8 desktop/server family product name short name sata ports (#) intel ? matrix storage technology ich8 base ich8 4 no ich8 raid ich8r 6 yes ich8 digital home ich8dh 6 yes ich8 digital office ich8do 6 yes table 4. intel ? ich8 mobile family product name short name sata ports (#) intel ? matrix storage technology raid 0/1 support intel ? active management technology ich8m base ich8m 3 no no ich8m enhanced ich8m-e 3 yes yes introduction 56 intel ? ich8 family datasheet intel ? ich8 family datasheet 57 signal description 2 signal description this chapter provides a detailed description of each signal. the signals are arranged in functional groups according to their associated interface. the ?#? symbol at the end of the signal na me indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present, the signal is asserted when at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin od o open drain output pin. i/od bi-directional input/open drain output pin. i/o bi-directional input / output pin. oc open collector output pin. signal description 58 intel ? ich8 family datasheet figure 1. intel ? ich8 interface signals block diagram (desktop) thrm# thrmtrip# sys_reset# rsmrst# mch_sync# slp_s3# slp_s4# slp_s5# slp_m# s4_state#/gpio26 pwrok clpwrok pwrbtn# ri# wake# sus_stat# / lpcpd# susclk lan_rst# vrmpwrgd pltrst# ck_pwrgd ad[31:0] c/be[3:0]# devsel# frame# irdy# trdy# stop# par perr# req0# req1# / gpio50 req2# / gpio52 req3# / gpio54 gnt0# gnt1# / gpio51 gnt2# / gpio53 gnt3# / gpio55 serr# pme# pciclk pcirst# plock# pci interface glan_clk glan_txp/pet6p; glan_txn/pet6n glan_rxp/per6p; glan_rxn/per6n glan_compo glan_compi gbe controller power mgnt. interrupt interface a20m# cpuslp# ferr# ignne# init# init3_3v# intr nmi smi# stpclk# rcin# a20gate cpupwrgd / gpio49 processor interface usb serirq pirq[d:a]# pirq[h:e]# / gpio[5:2] usb[9:0]p; usb[9:0]n oc0#; oc[9:8]# oc1#/gpio40; oc2#/gpio41 oc3#/gpio42; oc4#/gpio43 oc5#/gpio29; oc6#/gpio30 oc7#/gpio31 usbrbias usbrbias# rtcx1 rtcx2 clk14 clk48 sata_clkp, sata_clkn dmi_clkp, dmi_clkn rtc clocks misc. signals intvrmen spkr rtcrst# tp0,tp6 tp[2:1] tp[3:5] lan100_slp general purpose i/o gpio[43,33,32,25,20,18,16, 15,13,12,8] fan speed control pwm[2:0] tach0/gpio17; tach1/gpio1 tach2/gpio6; tach3/gpio7 sst peci intruder# smlink[1:0] linkalert# clgpio0/gpio24;clgpio1/gpio10 clgpio2/gpio14;wol_en/gpio9 dmi[3:0]txp, dmi[3:0]txn dmi[3:0]rxp, dmi[3:0]rxn dmi_zcomp dmi_ircomp direct media interface lpc interface smbus interface hda_rst# hda_sync hda_bit_clk hda_sdout hda_sdin[3:0] intel ? high definition audio firmware hub system mgnt. fwh[3:0] / lad[3:0] fwh4 / lframe# lad[3:0] / fwh[3:0] lframe# / fwh4 ldrq0# ldrq1# / gpio23 smbdata smbclk smbalert# / gpio11 glan_clk lan_rxd[2:0] lan_txd[2:0] lan_rstsync platform lan connect sata[5:0]txp, sata[5:0]txn sata[5:0]rxp, sata[5:0]rxn satarbias satarbias# sataled# sataclkreq# / gpio35 sata0gp /gpio21 sata1gp /gpio19 sata2gp /gpio36 sata3gp /gpio37 sata4gp sata5gp sclock/gpio22 sload/gpio38 sdataout0/gpio39 sdataout1/gpio48 serial ata interface pci express* interface petp[5:1], petn[5:1] perp[5:1], pern[5:1] glan_txp/pet6p; glan_txn/pet6n glan_rxp/per6p; glan_rxn/per6n spi spi_cs[0]# spi_cs[1]# spi_miso spi_mosi spi_clk qrt_state[1:0] / gpio[28:27] intel ? quick resume technology cl_clk ; cl_data cl_vref cl_rst# controller link intel ? ich8 family datasheet 59 signal description figure 2. intel ? ich8 interface signals block diagram (mobile) thrm# thrmtrip# sys_reset# rsmrst# mch_sync# slp_s3# slp_s4# slp_s5# slp_m# s4_state#/gpio26 pwrok clpwrok pwrbtn# ri# wake# sus_stat# / lpcpd# susclk lan_rst# vrmpwrgd pltrst# ck_pwrgd bmbusy#/gpio0 clkrun# stp_pci# stp_cpu# batlow# dprslpvr/gpio16 dprstp# ad[31:0] c/be[3:0]# devsel# frame# irdy# trdy# stop# par perr# req0# req1# / gpio50 req2# / gpio52 req3# / gpio54 gnt0# gnt1# / gpio51 gnt2# / gpio53 gnt3# / gpio55 serr# pme# pciclk pcirst# plock# pci interface glan_clk glan_txp/pet6p; glan_txn/pet6n glan_rxp/per6p; glan_rxn/per6n glan_compo glan_compi glan_dock#/gpio13 gbe controller power mgnt. interrupt interface a20m# ferr# ignne# init# intr nmi smi# stpclk# rcin# a20gate cpupwrgd / gpio49 dpslp# processor interface usb serirq pirq[d:a]# pirq[h:e]# / gpio[5:2] ideirq usb[9:0]p; usb[9:0]n oc0#; oc[9:8]# oc1#/gpio40; oc2#/gpio41 oc3#/gpio42; oc4#/gpio43 oc5#/gpio29; oc6#/gpio30 oc7#/gpio31 usbrbias usbrbias# rtcx1 rtcx2 clk14 clk48 sata_clkp, sata_clkn dmi_clkp, dmi_clkn rtc clocks misc. signals intvrmen spkr rtcrst# tp3, tp7, tp8 lan100_slp general purpose i/o gpio[43,37,20,18,17,12,8,7,6,1] ide interface intruder# smlink[1:0] linkalert#/cl_rst1# mem_led/gpio24;alert#/gpio10 netdetect/gpio14;wol_en/gpio9 dmi[3:0]txp, dmi[3:0]txn dmi[3:0]rxp, dmi[3:0]rxn dmi_zcomp dmi_ircomp direct media interface lpc interface smbus interface hda_rst# hda_sync hda_bit_clk hda_sdout hda_sdin[3:0] hda_dock_en # /gpio33 hda_doc_rst#/gpio34 intel ? high definition audio firmware hub system mgnt. fwh[3:0] / lad[3:0] fwh4 / lframe# lad[3:0] / fwh[3:0] lframe# / fwh4 ldrq0# ldrq1# / gpio23 smbdata smbclk smbalert# / gpio11 glan_clk lan_rxd[2:0] lan_txd[2:0] lan_rstsync platform lan connect sata[2:0]txp, sata[2:0]txn sata[2:0]rxp, sata[2:0]rxn satarbias satarbias# sataled# sataclkreq# / gpio35 sata0gp /gpio21 sata1gp /gpio19 sata2gp /gpio36 sclock/gpio22 sload/gpio38 sdataout0/gpio39 sdataout1/gpio48 serial ata interface pci express* interface petp[5:1], petn[5:1] perp[5:1], pern[5:1] glan_txp/pet6p; glan_txn/pet6n glan_rxp/per6p; glan_rxn/per6n spi spi_cs[0]# spi_cs[1]# spi_miso spi_mosi spi_clk qrt_state[1:0] / gpio[28:27] intel ? quick resume technology cl_clk[1:0] ; cl_data[1:0] cl_vref[1:0] cl_rst# controller link dcs1# dcs3# da[2:0] dd[15:0] ddreq ddack# dior# (dwstb / rdmardy#) diow# (dstop) iordy (drstb / wdmardy#) signal description 60 intel ? ich8 family datasheet 2.1 direct media interface (dmi) to host controller 2.2 pci express* table 5. direct media interface signals name type description dmi0txp, dmi0txn o direct media interface differential transmit pair 0 dmi0rxp, dmi0rxn i direct media interface differential receive pair 0 dmi1txp, dmi1txn o direct media interface differential transmit pair 1 dmi1rxp, dmi1rxn i direct media interface differential receive pair 1 dmi2txp, dmi2txn o direct media interface differential transmit pair 2 dmi2rxp, dmi2rxn i direct media interface differential receive pair 2 dmi3txp, dmi3txn o direct media interface differential transmit pair 3 dmi3rxp, dmi3rxn i direct media interface differential receive pair 3 dmi_zcomp i impedance compensation input: this signal determines dmi input impedance. dmi_ircomp o impedance/current compensation output: this signal determines dmi output im pedance and bias current. table 6. pci express* signals name type description petp1, petn1 o pci express* differential transmit pair 1 perp1, pern1 i pci express differential receive pair 1 petp2, petn2 o pci express differential transmit pair 2 perp2, pern2 i pci express differential receive pair 2 petp3, petn3 o pci express differential transmit pair 3 perp3, pern3 i pci express differential receive pair 3 petp4, petn4 o pci express differential transmit pair 4 perp4, pern4 i pci express differential receive pair 4 petp5, petn5 o pci express differential transmit pair 5 perp5, pern5 i pci express differential receive pair 5 petp6/glan_txp, petn6/glan_txn o pci express differential transmit pair 6: the differential pair functions as the gbe lan tran smit pair when the integrated gbe controller is enabled. perp6/glan_rxp, pern6/glan_rxn i pci express differential receive pair 6: the differential pair functions as the gbe lan receive pair when the integrated gbe controller is enabled. intel ? ich8 family datasheet 61 signal description 2.3 lan connect interface 2.4 gigabit lan connect interface table 7. lan connect interface signals name type description glan_clk i gbe input clock: this clock is driven by lan connect device. the frequency will vary depending on link speed. note: the clock is shared between lan connect interface and gigabit lan conn ect interface. lan_rxd[2:0] i received data: the platform lan connect component uses these signals to transfer data and cont rol information to the integrated lan controller. these signals ha ve integrated weak pull-up resistors. lan_txd[2:0] o transmit data : the integrated lan controller uses these signals to transfer data and control informat ion to the platfo rm lan connect device. lan_rstsync o lan reset/sync: the lan connect component?s reset and sync signals are multiplexed onto this pin. table 8. gigabit lan conn ect interface signals name type description glan_clk i gbe input clock: clock driven by lan connect device. the frequency will vary depending on link speed. note: the clock is shared between lan connect interface and gigabit lan connect interface. glan_txp/ pet6p; glan_txn/ pet6n o gigabit lan differential transmit pair: these signals can, instead, be used as pci express port 6 differential transmit pair glan_rxp/ per6p ; glan_rxn/ per6n i gigabit lan differential receive pair: these signals can, instead, be used as pci express port 6 differential receive pair. glan_compo o impedance compensation output pad: determines gigabit lan connect interface output impedance and bias current. glan_compi i impedance compensation input pad: determines gigabit lan connect interface input impedance. glan_dock# (mobile only)/ gpio12 i gbe dock/undock indication: this signal indicates if the platform is in docked or undocke d position. the platform should drive this pin low or high depending on its docked or undocked state. this signal is configured via soft straps as described in section 20.2.5.1 . this signal may instea d be used as a gpio. signal description 62 intel ? ich8 family datasheet 2.5 firmware hub interface energy_detect (mobile only) / gpio13 i energy detect (mobile only): this input detect signal indicates that power to the lan connected device must be restored. this signal connects to the output of an external link detect circuit and is required to implement the intel ? auto detect battery saver feature for lan connect device full power down savings. this signal may instead be used as a gpio. lan_rstsync o lan reset/sync: this is the reset/sy nc signal from the gbe lan interface to the physic al device. the lan connect component?s reset and sync signals are multiplexed onto this pin. note: the signal is shared between lan connect interface and gigabit lan connect interface. table 9. firmware hub interface signals name type description fwh[3:0] / lad[3:0] i/o firmware hub signals. these sign als are multiplexed with the lpc address signals. fwh4 / lframe# o firmware hub signals. th is signal is multiplexed with the lpc lframe# signal. table 8. gigabit lan connect interface signals name type description intel ? ich8 family datasheet 63 signal description 2.6 pci interface table 10. pci interface signals (sheet 1 of 3) name type description ad[31:0] i/o pci address/data : ad[31:0] is a multip lexed address and data bus. during the first clock of a transaction, ad[31:0] contain a physical address (32 bi ts). during subseque nt clocks, ad[31:0] contain data. the intel ? ich8 will drive all 0s on ad[31:0] during the address phase of all pci special cycles. c/be[3:0]# i/o bus command and byte enables : the command and byte enable signals are multiplexed on the sa me pci pins. during the address phase of a transaction, c/be[3:0]# define the bus comm and. during the data phase c/ be[3:0]# define the byte enables. all command encodings not shown are reserved. the ich8 does not decode reserved values, and therefore will not respond if a pci master generates a cycle using one of the reserved values. devsel# i/o device select : the ich8 asserts devsel# to claim a pci transaction. as an output, the ich8 asserts devsel# when a pci master peripheral attempts an acce ss to an internal ich8 address or an address destined dmi (mai n memory or graphics). as an input, devsel# indicates the response to an ich8-initiated transaction on the pci bus. devsel# is tri-stated from the leading edge of pltrst#. devsel# remain s tri-stated by the ich8 until driven by a target device. frame# i/o cycle frame: the current initiator drives frame# to indicate the beginning and duration of a pci transaction. while the initiator asserts frame#, data transfers continue. when the initiator negates frame#, the transaction is in the final data phase. frame# is an input to the ich8 when the ich8 is the target, and frame# is an output from the ich8 when the ich8 is the initiator. frame# remains tri-stated by the ich8 until driven by an initiator. c/be[3:0]# command type 0000b interrupt acknowledge 0001b special cycle 0010b i/o read 0011b i/o write 0110b memory read 0111b memory write 1010b configuration read 1011b configuration write 1100b memory read multiple 1110b memory read line 1111b memory write and invalidate signal description 64 intel ? ich8 family datasheet irdy# i/o initiator ready : irdy# indicates the ich8's ability, as an initiator, to complete the current data phase of the transaction. it is used in conjunction with trdy#. a data phase is completed on any clock both irdy# and trdy# are sample d asserted. during a write, irdy# indicates the ich8 has va lid data present on ad[31:0]. during a read, it indicates the ich8 is prepared to latch data. irdy# is an input to the ich8 when the ich8 is the target and an output from the ich8 when the ich8 is an initiator. irdy# remains tri-stated by the ich8 until driven by an initiator. trdy# i/o target ready : trdy# indicates the ich8's ability as a target to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. a data phase is completed when both trdy# and irdy# are sampled asserted. during a read, trdy# indicates that the ich8, as a ta rget, has placed valid data on ad[31:0]. during a write, trdy# in dicates the ich8, as a target is prepared to latch data. trdy# is an input to the ich8 when the ich8 is the initiator and an output from the ich8 when the ich8 is a target. trdy# is tri-stated fro m the leading edge of pltrst#. trdy# remains tri-stated by the ich8 until driven by a target. stop# i/o stop : stop# indicates that the ich8, as a target, is requesting the initiator to stop the current transaction. stop# causes the ich8, as an initiator, to stop the current transaction. stop# is an output when the ich8 is a target and an input when the ich8 is an initiator. par i/o calculated/checked parity: par uses ?even? parity calculated on 36 bits, ad[31:0] plus c/be[3:0]#. ?even? parity means that the ich8 counts the number of one within the 36 bits plus par and the sum is always even. the ich8 al ways calculates par on 36 bits regardless of the valid byte enables. the ich8 generates par for address and data phases and only assures par to be valid one pci clock after the corresponding addr ess or data phase. the ich8 drives and tri-states par identically to the ad[31:0] lines except that the ich8 delays par by exactly one pci clock. par is an output during the address phase (delayed one clock) for all ich8 initiated transactions. par is an output during the data phase (delayed one clock) when the ich8 is the initiator of a pci write transaction, and when it is the target of a read transaction. ich8 checks parity when it is the target of a pci write tr ansaction. if a parity error is detected, the ich8 will set the appr opriate internal status bits, and has the option to generate an nmi# or smi#. perr# i/o parity error : an external pci device drives perr# when it receives data that has a parity error. the ich8 drives perr# when it detects a parity error. the ich8 can either generate an nmi# or smi# upon detecting a parity error (either detected internally or reported via the perr# signal). req0# req1#/ gpio50 req2#/ gpio52 req3#/gpio54 i pci requests : the ich8 supports up to 4 masters on the pci bus. req[3:1]# pins can instead be used as gpio. table 10. pci interface signals (sheet 2 of 3) name type description intel ? ich8 family datasheet 65 signal description gnt0# gnt1#/ gpio51 gnt2# / gpio53 gnt3# /gpio55 o pci grants : the ich8 supports up to 4 masters on the pci bus. gnt[3:1]# pins can instead be used as gpio. pull-up resistors are not required on these signals. if pull-ups are used, they should be tied to the vcc3_3 power rail. note: gnt[3:0]# are sampled as a functional strap. see section 2.26 for details. pciclk i pci clock : this is a 33 mhz clock. pcic lk provides timing for all transactions on the pci bus. note: (mobile only) this clock does not stop based on stp_pci# signal. pci clock only stops based on slp_s3#. pcirst# o pci reset: this is the secondary pci bus reset signal. it is a logical or of the primary interfac e pltrst# signal and the state of the secondary bus reset bit of the bridge control register (d30:f0:3eh, bit 6). plock# i/o pci lock : this signal indicates an exclusive bus operation and may require multiple transactions to complete. ich8 asserts plock# when it performs non-exclusive transactions on the pci bus. plock# is ignored when pci masters are granted the bus in desktop configurations. note: in mobile configuration, device s on the pci bus (other than the ich8) are not permitted to assert the plock# signal. serr# i/od system error : serr# can be pulsed active by any pci device that detects a system error condition. upon sampling serr# active, the ich8 has the ability to generate an nmi, smi#, or interrupt. pme# i/od pci power management event : pci peripherals drive pme# to wake the system from low-power states s1?s5. pme# assertion can also be enabled to generate an sci from the s0 state. in some cases the ich8 may drive pme# ac tive due to an internal wake event. the ich8 will not drive pme# high, but it will be pulled up to vccsus3_3 by an intern al pull-up resistor. table 10. pci interface signals (sheet 3 of 3) name type description signal description 66 intel ? ich8 family datasheet 2.7 serial ata interface table 11. serial ata interface signals (sheet 1 of 3) name type description sata0txp sata0txn o serial ata differenti al transmit pairs: these are outbound high-speed differential signals to port 0. in compatible mode, sata port 0 is the primary master of sata controller 1. sata0rxp sata0rxn i serial ata 0 differential receive pair: these are inbound high- speed differential si gnals from port 0. in compatible mode, sata port 0 is the primary master of sata controller 1. sata1txp sata1txn o serial ata 1 differential transmit pair: these are outbound high-speed differentia l signals to port 1. in compatible mode, sata port 1 is the secondary master of sata controller 1. sata1rxp sata1rxn i serial ata 1 differential receive pair: these are inbound high- speed differential si gnals from port 1. in compatible mode, sata port 1 is the secondary master of sata controller 1 sata2txp sata2txn o serial ata 2 differential transmit pair: these are outbound high-speed differentia l signals to port 2. in compatible mode, sata port 2 is the primary slave of sata controller 1. note: this port is not functional in the desktop ich8 base component. sata2rxp sata2rxn i serial ata 2 differential receive pair: these are inbound high- speed differential si gnals from port 2. in compatible mode, sata port 2 is the primary slave of sata controller 1. note: this port is not functional in the desktop ich8 base component. sata3txp sata3txn (desktop only) o serial ata 3 differential transmit pair: these are outbound high-speed differentia l signals to port 3 in compatible mode, sata port 3 is the secondary slave of sata controller 1. note: this port is not functional in the desktop ich8 base component. sata3rxp sata3rxn (desktop only) i serial ata 3 differential receive pair: these are inbound high- speed differential si gnals from port 3 in compatible mode, sata port 3 is the secondary slave of sata controller 1. note: this port is not functional in the desktop ich8 base component. sata4txp sata4txn (desktop only) o serial ata 4 differential transmit pair: these are outbound high-speed differentia l signals to port 4. in compatible mode, sata port 4 is the primary master of sata controller 2 intel ? ich8 family datasheet 67 signal description sata4rxp sata4rxn (desktop only) i serial ata 4 differential receive pair: these are inbound high- speed differential si gnals from port 4. in compatible mode, sata port 4 is the primary master of sata controller 2 sata5txp sata5txn (desktop only) o serial ata 5 differential transmit pair: these are outbound high-speed differentia l signals to port 5. in compatible mode, sata port 5 is the secondary master of sata controller 2 sata5rxp sata5rxn (desktop only) i serial ata 5 differential receive pair: these are inbound high- speed differential si gnals from port 5. in compatible mode, sata port 5 is the secondary master of sata controller 2 satarbias o serial ata resistor bias: these are analog connection points for an external resistor to ground. satarbias# i serial ata resistor bias complement: these are analog connection points for an ex ternal resistor to ground. sata0gp / gpio21 i serial ata 0 general purpose: this is an input pin which can be configured as an interlock switch corresponding to sata port 0. when used as an interlock switch status indication, this signal should be drive to ?0? to indicate th at the switch is closed and to ?1? to indicate that the switch is open. if interlock switches are not required, this pin can be configured as gpio21. sata1gp / gpio19 i serial ata 1 general purpose: same function as sata0gp, except for sata port 1. if interlock switches are not required, this pin can be configured as gpio19. sata2gp (ich8r only) / gpio36 i serial ata 2 general purpose: same function as sata0gp, except for sata port 2. if interlock switches are not required, this pin can be configured as gpio36. note: this signal can only be used as gpio36 in the desktop ich8 base component. sata3gp (desktop only) / gpio37 i serial ata 3 general purpose: same function as sata0gp, except for sata port 3. if interlock switches are not required, this pin can be configured as gpio37. note: this signal can only be used as gpio37 in the desktop ich8 base component. sata4gp (desktop only) i serial ata 4 general purpose: same function as sata0gp, except for sata port 4. sata5gp (desktop only) i serial ata 5 general purpose: same function as sata0gp, except for sata port 5. table 11. serial ata interface signals (sheet 2 of 3) name type description signal description 68 intel ? ich8 family datasheet 2.8 ide interface (mobile only) sataled# oc serial ata led: this is an open-collector output pin driven during sata command activity. it is to be connected to external circuitry that can provide the current to dr ive a platform led. when active, the led is on. when tri-stated, the led is off. an external pull-up resistor to vcc3_3 is required. note: this is sampled as a function al strap. see strapping section for details. sataclkreq# /gpio35 od (native) / i/o (gp) serial ata clock request: this is an open-drain output pin when configured as sataclkreq#. it is to connect to the system clock chip. when active, request for sa ta clock running is asserted. when tri-stated, it tells the clock chip that sata clock can be stopped. an external pull -up resistor is required. sclock / gpio22 od (native)/ i/o (gp) sgpio reference clock: the sata controller uses rising edges of this clock to transmit serial data , and the target uses the falling edge of this clock to latch data. if sgpio interface is not used, this signal can be used as a gpio. sload /gpio38 od (native)/ i/o (gp) sgpio load: the controller drives a 1 at the rising edge of sclock to indicate either the star t or end of a bit stream. a 4-bit vendor specific pattern will be transmitted right after the signal assertion. if sgpio interface is not used, this signal can be used as a gpio. sdataout0 / gpio39 sdataout1 / gpio48 od (native)/ i/o (gp) sgpio dataout: driven by the controller to indicate the drive status in the following sequence: drive 0, 1, 2, n, 0, 1, 2, n, 2... if sgpio interface is not used, th e signals can be used as gpio. table 12. ide interface signals (mobile only) name typ e description dcs1# o ide device chip selects for 100 range: for ata command register block. this output signal is connected to the corresponding signal on the ide connector. dcs3# o ide device chip select for 300 range: for ata control register block. this output signal is connected to the corresponding signal on the ide connector. da[2:0] o ide device address: these output signals are connected to the corresponding signals on the ide connector. they are used to indicate which byte in either the ata comman d block or control block is being addressed. dd[15:0] i/o ide device data: these signals directly driv e the corresponding signals on the ide connector. there is a weak internal pull-down resistor on dd7. ddreq i ide device dma request: this input signal is directly driven from the drq signal on the ide connector. it is asserted by th e ide device to request a data transfer, and used in conjunction with the pci bus master ide function and are not associated wi th any at compatible dma channel. there is a weak internal pull-d own resistor on this signal. table 11. serial ata interface signals (sheet 3 of 3) name type description intel ? ich8 family datasheet 69 signal description 2.9 lpc interface ddack# o ide device dma acknowledge: this signal direct ly drives the dak# signal on the ide connector. dd ack# is asserted by the intel ? ich8 to indicate to ide dma slave devices that a given data transfer cycle (assertion of dior# or diow#) is a dm a data transfer cycle. this signal is used in conjunction with the pci bus master ide function and are not associated with any at -compatible dma channel. dior# / (dwstb / rdmardy#) o disk i/o read (pio and non-ultra dma) : this is the command to the ide device that it may drive data onto the dd lines. data is latched by the ich8 on the deassertion edge of dior#. the ide device is selected either by the ata register file chip selects (dcs1# or dcs3#) and the da lines, or the ide dma acknowledge (ddak#). disk write strobe (ultra dma writes to disk): this is the data write strobe for writes to disk. when writing to disk, ich8 drives valid data on rising and falling edges of dwstb. disk dma ready (ultra dma reads from disk): this is the dma ready for reads from disk. when reading from disk, ich8 deasserts rdmardy# to pause burst data transfers. diow# / (dstop) o disk i/o write (pio and non-ultra dma) : this is the command to the ide device that it may latch data from the dd lines. data is latched by the ide device on the deassertion edge of diow#. the ide device is selected either by the ata register file chip selects (dcs1# or dcs3#) and the da lines, or the ide dma acknowledge (ddak#). disk stop (ultra dma): ich8 assert s this signal to terminate a burst. iordy / (drstb / wdmardy#) i i/o channel ready (pio) : this signal will keep the strobe active (dior# on reads, diow# on writes) longer than the minimum width. it adds wait-states to pio transfers. disk read strobe (ultra dma reads from disk): when reading from disk, ich8 latches data on rising and fallin g edges of this sign al from the disk. disk dma ready (ultra dma writes to disk): when writing to disk, this is de-asserted by the disk to pause burst data transfers. table 13. lpc interface signals name type description lad[3:0] / fwh[3:0] i/o lpc multiplexed command, address, data: for lad[3:0], internal pull-ups are provided. lframe# / fwh4 o lpc frame: lframe# indicates the start of an lpc cycle, or an abort. ldrq0# ldrq1# / gpio23 i lpc serial dma/mast er request inputs: ldrq[1:0]# are used to request dma or bus master access. these signals are typically connected to external super i/o devi ce. an internal pull-up resistor is provided on these signals. ldrq1# may optionally be used as gpio. table 12. ide interface signals (mobile only) name typ e description signal description 70 intel ? ich8 family datasheet 2.10 interrupt interface table 14. interrupt signals name type description serirq i/o serial interrupt request: this pin implements the serial interrupt protocol. pirq[d:a]# i/od pci interrupt requests: in non-apic mode the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the interrupt steering section. each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirqa# is connected to irq16, pirqb# to irq17, pirqc# to irq18, and pirqd# to irq19. this frees the legacy interrupts. pirq[h:e]# / gpio[5:2] i/od pci interrupt requests: in non-apic mode the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the interrupt steering section. each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirqe# is connected to irq20, pirqf# to irq21, pirqg# to irq22, and pirqh# to irq23. this frees the legacy interrupts. if not needed for interru pts, these signals can be used as gpio. ideirq (mobile only) i ide interrupt request: this interrupt input is connected to the ide drive. intel ? ich8 family datasheet 71 signal description 2.11 usb interface table 15. usb interface signals name type description usbp0p, usbp0n, usbp1p, usbp1n i/o universal serial bus port [1:0] differential : these differential pairs are used to transmit data/address/command signals for ports 0 and 1. these ports can be routed to uhci controller #1 or the ehci controller #1. note: no external resistors are requ ired on these signals. the intel ? ich8 integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor usbp2p, usbp2n, usbp3p, usbp3n i/o universal serial bus port [3:2] differential : these differential pairs are used to transmit data /address/command signals for ports 2 and 3. these ports can be routed to uhci controller #2 or the ehci controller #1. note: no external resistors are requ ired on these signals. the ich8 integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor usbp4p, usbp4n, usbp5p, usbp5n i/o universal serial bus port [5:4] differential : these differential pairs are used to transmit data/address/command signals for ports 4 and 5. these ports can be routed to uhci controller #3 or the ehci controller #1. note: no external resistors are requ ired on these signals. the ich8 integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor usbp6p, usbp6n, usbp7p, usbp7n i/o universal serial bus port [7:6] differential: these differential pairs are used to transmit data/address/command signals for ports 6 and 7. these ports can be routed to uhci controller #4 or the ehci controller #2. note: no external resistors are requ ired on these signals. the ich8 integrates 15 kw pull-dow ns and provides an output driver impedance of 45 w which requires no external series resistor usbp8p, usbp8n, usbp9p, usbp9n i/o universal serial bus port [9:8] differential: these differential pairs are used to transmit data/address/command signals for ports 8 and 9. these ports can be routed to uhci controller #5 or the ehci controller #2. note: no external resistors are requ ired on these signals. the ich8 integrates 15 kw pull-dow ns and provides an output driver impedance of 45 w which requires no external series resistor signal description 72 intel ? ich8 family datasheet 2.12 power management interface oc0# oc1# / gpio40 oc2# / gpio41 oc3# / gpio42 oc4# / gpio43 oc5# / gpio29 oc6# / gpio30 oc7# / gpio31 oc[9:8]# i overcurrent indicators : these signals set co rresponding bits in the usb controllers to indicate th at an overcurrent condition has occurred. oc[7:1]# may optionally be used as gpios. note: oc[9:0]# are not 5 v tolerant. usbrbias o usb resistor bias: analog connection po int for an external resistor. used to set transmit cu rrents and internal load resistors. usbrbias# i usb resistor bias complement: analog connection point for an external resistor. used to set tr ansmit currents an d internal load resistors. table 16. power management interface signals (sheet 1 of 4) name type description pltrst# o platform reset: the intel ? ich8 asserts pltrst# to reset devices on the platform (e.g., sio, fwh, la n, (g)mch, tpm, etc.). the ich8 asserts pltrst# during power-up an d when s/w initiates a hard reset sequence through the rese t control register (i/o register cf9h). the ich8 drives pltrst# inactive a minimum of 1 ms after both pwrok and vrmpwrgd are driven high. th e ich8 drives pltrst# active a minimum of 1 ms when initiated thro ugh the reset control register (i/ o register cf9h). note: pltrst# is in the vccsus3_3 well. thrm# i thermal alarm: active low signal generate d by external hardware to generate an smi# or sci. thrmtrip# i thermal trip : when low, this signal indicates that a thermal trip from the processor occurred, and the ich8 will immediately transition to a s5 state. the ich8 will not wait for the processor stop grant cycle since the processor has overheated. slp_s3# o s3 sleep control: slp_s3# is for power plane control. this signal shuts off power to all non-critical systems when in s3 (suspend to ram), s4 (suspend to disk), or s5 (soft off) states. table 15. usb interface signals name type description intel ? ich8 family datasheet 73 signal description slp_s4# o s4 sleep control : slp_s4# is for power plane control. this signal shuts power to all non-critical systems when in the s4 (suspend to disk) or s5 (soft off) state. note: this pin must be used to cont rol the dram power in order to use the ich8?s dram power- cycling feature. refer to chapter 5.13.11.2 for details note: in a system with intel amt support, this signal should be used to control the dram power. in m1 state (where the host platform is in s3-s5 states an d the manageability sub-system is running) the signal is forced high along with slp_m# in order to properly maintain power to the dimm used for manageability sub-system. slp_s5# o s5 sleep control: slp_s5# is for power plane control. this signal is used to shut power off to all non-cr itical systems when in the s5 (soft off) states. slp_m# o manageability sleep state control: this signal is used to control power planes to the intel amt su b-system. if no me firmware is present, slp_m# will have the same timings as slp_s3#. s4_state# / gpio26 o s4 state indication: this signals asserts low when the host platform is in s4 or s5 state. in platform s where the manageability engine is forcing the slp_s4# high along with slp_m#, this signal can be used by other devices on the board to know when the host platform is below the s3 state. pwrok i power ok: when asserted, pwrok is an indication to the ich8 that all power rails have been stable fo r 99 ms and that pciclk has been stable for 1 ms. pwrok can be driv en asynchronously. when pwrok is negated, the ich8 asserts pltrst#. note: pwrok must deassert for a minimum of three rtc clock periods in order for the ich8 to fully reset the power and properly generate the pltrst# output. clpwrok i controller link power ok: when asserted, this signal indicates that power to the controller link subsystem ((g)mch, ich8, etc.) is stable and tells the ich8 to deassert cl_rst# to the (g)mch. notes: 1. clpwrok must not assert before rsmrst# deasserts 2. clpwrok must not asse rt after pwrok asserts pwrbtn# i power button: the power button will cause smi# or sci to indicate a system request to go to a sleep stat e. if the system is already in a sleep state, this signal will cause a wake event. if pwrbtn# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the s5 state. override will occur even if the system is in the s1-s4 states. this signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input. ri# i ring indicate: this signal is an input from a modem. it can be enabled as a wake event, and this is preserved across power failures. table 16. power management inte rface signals (sheet 2 of 4) name type description signal description 74 intel ? ich8 family datasheet sys_reset# i system reset : this pin forces an in ternal reset after being debounced. the ich8 wi ll reset immediately if the smbus is idle; otherwise, it will wait up to 25 ms 2 ms for the smbus to idle before forcing a reset on the system. rsmrst# i resume well reset: this signal is used fo r resetting the resume power plane logic. this signal must be asserted for at least 10 ms after the suspend power wells are valid. wh en deasserted, this signal is an indication that the suspend power wells are stable. lan_rst# i lan reset: when asserted, the internal lan controll er is in reset. this signal must be assert ed until the lan power wells (vcclan3_3 and vcclan1_05) and vcccl3_3 power well are valid. when deasserted, this signal is an indication th at the lan power wells are stable. notes: 1. lan_rst# must not deassert before rsmrst# deasserts 2. lan_rst# must not deas sert after pwrok asserts. 3. if integrated lan is not used lan_rst# can be tied to vss. wake# i pci express* wake event: sideband wake signal on pci express asserted by components requesting wake up. mch_sync# i mch sync: this input is internally anded with the pwrok input. this signal is connect to the ich_sync# output of (g)mch. sus_stat# / lpcpd# o suspend status: this signal is asserted by the ich8 to indicate that the system will be entering a lo w power state soon. this can be monitored by devices wi th memory that need to switch from normal refresh to suspend refresh mode. it can also be used by other peripherals as an indication that th ey should isolate their outputs that may be going to powered-off planes. this signal is called lpcpd# on the lpc interface. susclk o suspend clock: this clock is an output of the rtc generator circuit to use by other chips for refresh clock. vrmpwrgd i vrm power good: this signal should be connected to be the processor?s vrm power good signifying the vrm is stable. this signal is internally anded with the pwrok input. this signal is in the resume well. ck_pwrgd o clock generator power good : indicates to the clock generator when the main power well is valid. this signal is asserted high when both slp_s3# and vrmpwrgd are high. bmbusy# (mobile only) / gpio0 (desktop only) i bus master busy: to support the c3 state. indication that a bus master device is busy. when this sign al is asserted, the bm_sts bit will be set. if this signal go es active in a c3 state, it is tr eated as a break event. note: this signal is internally sync hronized using the pciclk and a two-stage synchronizer. it does not need to meet any particular setup or hold time. note: in desktop configurations, this signal is a gpio. clkrun# (mobile only)/ gpio32 (desktop only) i/o pci clock run: this signal is used to su pport pci clkrun protocol. it connects to peripherals that need to request clock restart or prevention of clock stopping. table 16. power management interface signals (sheet 3 of 4) name type description intel ? ich8 family datasheet 75 signal description 2.13 processor interface stp_pci# (mobile only) / gpio15 (desktop only) o stop pci clock: this signal is an outp ut to the external clock generator for it to turn off the pci clock. it is used to support pci clkrun# protocol. this pin is also used to communicate the host clock frequency select for me operation. if this functionality is not needed, this signal can be configured as a gpio. stp_cpu# (mobile only) / gpio25 (desktop only) o stop cpu clock: this signal is an output to the external clock generator for it to turn off the processor clock. it is used to support the c3 state. this pin is also used to communicate the host clock frequency select for me operation. if this functionality is not needed, this signal can be configured as a gpio. batlow# (mobile only) / tp0 (desktop only) i battery low: this signal is an input fr om battery to indicate that there is insufficient powe r to boot the system. assertion will prevent wake from s3?s5 state. this signal can also be enabled to cause an smi# when asserted. dprslpvr (mobile only) / gpio16 (desktop only) o deeper sleep - voltage regulator: this signal is used to lower the voltage of vrm during the c4 stat e. when the signal is high, the voltage regulator outputs the lower ?deeper sleep? voltage. when low (default), the voltage regulator ou tputs the higher ?normal? voltage. dprstp# (mobile only) / tp1 (desktop only) o deeper stop: this is a copy of the dprslpvr and it is active low. table 17. processor interfac e signals (sheet 1 of 2) name type description a20m# o mask a20: a20m# will go active base d on either setting the appropriate bit in the port 92h re gister, or based on the a20gate input being active. cpuslp# (desktop only) o cpu sleep: this signal puts the proces sor into a state that saves substantial power compared to stop -grant state. however, during that time, no snoops occur. the intel ? ich8 can optionally assert the cpuslp# signal when go ing to the s1 state. ferr# i numeric coprocessor error: this signal is tied to the coprocessor error signal on the processor. fe rr# is only used if the ich8 coprocessor error reporting functi on is enabled in the oic.cen register (chipset configuration re gisters:offset 31ffh: bit 1). if ferr# is asserted, the ich8 gene rates an internal irq13 to its interrupt controller unit. it is also used to gate the ignne# signal to ensure that ignne# is not asserted to the processor unless ferr# is active. ferr# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. note: ferr# can be used in some st ates for notification by the processor of pending interrupt events. this functionality is independent of the oic register bi t setting. table 16. power management inte rface signals (sheet 4 of 4) name type description signal description 76 intel ? ich8 family datasheet ignne# o ignore numeric error: this signal is connected to the ignore error pin on the processor. ignne# is on ly used if the ich8 coprocessor error reporting function is enabled in the oic.cen register (chipset configuration registers:offset 31ffh: bit 1). if ferr# is active, indicating a coprocessor error, a write to the coprocessor error register (i/o register f0h) caus es the ignne# to be asserted. ignne# remains asserted until ferr# is negated. if ferr# is not asserted when the copr ocessor error register is written, the ignne# signal is no t asserted. init# o initialization: init# is asserted by the ich8 for 16 pci clocks to reset the processor. ich8 can be co nfigured to support processor built in self test (bist). init3_3v# (desktop only) o initialization 3.3 v: this is the identical 3.3 v copy of init# intended for firmware hub. intr o cpu interrupt: intr is asserted by the ich8 to signal the processor that an interrupt request is pending and needs to be serviced. it is an asynchronous output and normally driven low. nmi o non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor. the ich8 can generate an nmi when either serr# is asserted or iochk# goes active via the serirq# stream. the processor detects an nmi when it detects a rising edge on nmi. nmi is reset by setting the corresp onding nmi source enable/disable bit in the nmi status and contro l register (i/o register 61h). smi# o system management interrupt: smi# is an active low output synchronous to pciclk. it is asserted by the ich8 in response to one of many enabled hardware or software events. stpclk# o stop clock request: stpclk# is an active low output synchronous to pciclk. it is asserted by the ich8 in response to one of many hardware or software events. wh en the processor samples stpclk# asserted, it responds by st opping its internal clock. rcin# i keyboard controller reset cpu: the keyboard controller can generate init# to the processor. this saves the external or gate with the ich8?s other sources of init #. when the ich8 detects the assertion of this signal, init# is generated for 16 pci clocks. note: the ich8 will ignore rcin# assertion during transitions to the s1, s3, s4, and s5 states. a20gate i a20 gate: a20gate is from the keyboard controller. the signal acts as an alternative method to force the a20m# signal active. it saves the external or gate needed with various other chipsets. cpupwrgd / gpio49 o cpu power good: this signal should be connected to the processor?s pwrgood input to indicate when the processor power is valid. this is an output signal that represents a logical and of the ich8?s pwrok and vrmpwrgd signals. this signal may op tionally be configured as a gpio. dpslp# (mobile only) / tp2 (desktop only) o deeper sleep: dpslp# is asserted by the ich8 to the processor. when the signal is low, the processor enters the deep sleep state by gating off the processor core cloc k inside the proc essor. when the signal is high (default ), the processor is not in the deep sleep state. table 17. processor interfac e signals (sheet 2 of 2) name type description intel ? ich8 family datasheet 77 signal description 2.14 smbus interface 2.15 system management interface table 18. sm bus interface signals name type description smbdata i/od smbus data: external pull-up resistor is required. smbclk i/od smbus clock: external pull-up re sistor is required. smbalert# / gpio11 i smbus alert: this signal is used to wa ke the system or generate smi#. if not used for smbalert#, it can be used as a gpio. table 19. system management interface signals (sheet 1 of 2) name type description intruder# i intruder detect: this signal can be set to disable system if box detected open. this signal?s status is readable , so it can be used like a gpio if the intruder detection is not needed. smlink[1:0] i/od system management link: smbus link to optional external system management asic or lan co ntroller. external pull-ups are required. note that smlink0 corresp onds to an smbus clock signal, and smlink1 corresponds to an smbus data signal. linkalert# / cl_rst1# i/od smlink alert: output of the integrated lan and input to either the integrated asf or an external ma nagement controll er in order for the lan?s smlink slave to be serviced. when used as linklert#, an extern al pull-up resist or is required. clgpio0 (mem_led) / gpio24 i/o controller link general purpose i/o 0: provides dram-powered led control. allows for the blinking of an led circuit to indicate memory activity. this signal can instead be used as gpio. suspwrack/ alert# (mobile only)/ gpio10 i/o suspwrack/alert# (mobile only) / gpio10: the primary use of this pin is for suspwrack co mmunication from the management engine (me) to the platform em bedded controller (ec). alert# functionality is provided for backup to facilitate smbus me-to-ec and ec-to-me communication and is not used in the current implementation. suspwrack signal is an output sign al used by the me in conjunction with slp_m# to indicate to th e ec that it acknowledges any suspend well power down decision by the ec. when the me asserts this signal high and slp_m# is low, this indicates to the ec it is safe to power off the suspend well. li kewise, when the me de-asserts this signal low and the suspend well is powered, this indicates to the ec that the me requires the susp end well to remain powered. (active high, level). this signal can instead be used as a gpio. this signal is used as gpio10 in desktop systems. signal description 78 intel ? ich8 family datasheet 2.16 real time clock interface ac_present (mobile only)/ gpio14 i/o ac_present (mobile only) / gpio14: ac_present is an anput signal from the platform embe dded controller (ec) to the management engine (me). the ac_present signal is used by the ec to indicate to the me the current power source of the system. when the signal is high, this indicates to the me that the system is connected to an external ac source s. when the signal is low, this indicates to the me that the system is connected to a dc (battery) source. the me uses this information in conjunction with the current system power state to determine what me power state to run in (m0, m1, or moff). (active high, level). this signal can instead be used as a gpio. this signal is used as gpio14 in desktop systems. wol_en / gpio9 o wake on lan power enable: in an intel ? amt or integrated asf enabled system, this output signal is driven high by the ich8 to control the lan subsystem power (vcclan3_3, vcccl3_3, lan phy power, and spi device) to support wake on lan (wol) when the intel ? manageability engine is powered off. this functionality is configured and controlled by the manageability engine prior to entering the powered off state. notes: 1. this signal should be or?d with the slp_m# signal on the motherboard to determine when to power the lan subsystem. 2. to support wol out of a g3 state, the wol_en pin needs to be pulled high by an external resistor until the manageability engine is initialized. if intel amt or integrated asf ar e disabled on a board that is configured for wol_en support, bi os must use gpio9 to control power to the lan subsyste m when entering s3?s5. in platforms that do not support in tel amt or integrated asf, this signal is used as gpio9. table 20. real time clock interface name type description rtcx1 special crystal input 1: this signal is connected to the 32.768 khz crystal. if no external crystal is used, then rt cx1 can be driven with the desired clock rate. rtcx2 special crystal input 2: this signal is connected to the 32.768 khz crystal. if no external crystal is used, then rtcx2 should be left floating. table 19. system management inte rface signals (sheet 2 of 2) name type description intel ? ich8 family datasheet 79 signal description 2.17 other clocks 2.18 miscellaneous signals table 21. other clocks name type description clk14 i oscillator clock: this clock is used for 8254 timers. it runs at 14.31818 mhz. this clock is permitte d to stop during s3 (or lower) states. clk48 i 48 mhz clock: this clock is used to run th e usb controller. it runs at 48.000 mhz. this clock is permitted to stop during s3 (or lower) states. sata_clkp sata_clkn i 100 mhz differential clock: these signals are used to run the sata controller at 100 mhz. th is clock is permitted to stop during s3/s4/s5 states. dmi_clkp, dmi_clkn i 100 mhz differential clock: these signals are used to run the direct media interface. ru ns at 100 mhz. table 22. miscellaneous signals (sheet 1 of 2) name type description intvrmen i internal voltage regulator enable: this signal enables the internal vccsus1_05, vccsus1_5 and vcccl1_5 regulators. this signal must be pu lled-up to vccrtc. lan100_slp i internal voltage regulator enable: this signal enables the internal voltage regulators powe ring vcclan1_05 and vcccl1_05. this signal must be pulled-up to vccrtc. spkr o speaker: the spkr signal is the ou tput of counter 2 and is internally ?anded? with port 61h bit 1 to provide speaker data enable. this signal drives an exte rnal speaker driver device, which in turn drives the system speaker. upon pltrst#, its output state is 0. note: spkr is sampled at the ri sing edge of pwrok as a functional strap. see section 2.26.1 for more details. there is a weak integrated pull-do wn resistor on spkr pin. rtcrst# i rtc reset: when asserted, this signal re sets register bits in the rtc well. notes: 1. unless cmos is being cleared (only to be done in the g3 power state), the rtcrst# input must always be high when all other rtc power planes are on. 2. in the case where the rtc ba ttery is dead or missing on the platform, the rtcrst# pi n must rise before the rsmrst# pin. tp0 (desktop only) / batlow# (mobile only) i test point 0: this signal must have an external pull-up to vccsus3_3. signal description 80 intel ? ich8 family datasheet 2.19 intel ? high definition audio link tp1 (desktop only) / dprstp# (mobile only) o test point 1: route signal to a test point. tp2 (desktop only) / dpslp# (mobile only) o test point 2: route signal to a test point. tp3 i/o test point 3: route signal to a test point. tp4 (desktop only) / cl_data1 (mobile only) i/o test point 4: route signal to a test point. tp5 (desktop only) / cl_clk1 (mobile only) i/o test point 5: route signal to a test point. tp6 (desktop only) / cl_vref1 (mobile only) i/o test point 6: route signal to a test point. tp7 (mobile only) i/o test point 7: route signal to a test point. tp8 (mobile only) i/o test point 8: route signal to a test point. table 23. intel ? high definition audio li nk signals (sheet 1 of 2) name type description hda_rst# o intel ? high definition audio reset: this signal is a master hardware reset to external codec(s). hda_sync o intel high definition audio sync: this signal is a 48 khz fixed rate sample sync to the codec(s). also used to encode the stream number. note: hda_sync is sampled at the rising edge of pwrok as a functional strap. see section 2.26.1 for more details. there is a weak integrated pull-down resistor on the hda_sync pin. hda_bit_clk o intel high definition audio bit clock output: 24.000 mhz serial data clock generated by the intel high definition audio controller (the intel ? ich8). this signal ha s a weak internal pull- down resistor. table 22. miscellaneous signals (sheet 2 of 2) name type description intel ? ich8 family datasheet 81 signal description notes: 1. some signals have integrated pull-u ps or pull-downs. consult table in section 3.1 for details. 2.20 serial peripheral interface (spi) hda_sdout o intel high definition audio serial data out: this signal is the serial tdm data output to the co dec(s). this seri al output is double-pumped for a bit rate of 48 mb/s for intel high definition audio. note: hda_sdout is sampled at the rising edge of pwrok as a functional strap. see section 2.26.1 for more details. there is a weak integrated pull-dow n resistor on the hda_sdout pin. hda_sdin[3:0] i intel high definition audio serial data in [3:0] : these signals are serial tdm data inputs from the codecs. the serial input is single-pumped for a bit rate of 24 mb/s for intel ? high definition audio. these signals have integr ated pull-down resistors, which are always enabled. hda_dock_en# (mobile only) / gpio33 i/o high definition audio dock enable: this signal controls the external intel hd audio docking isol ation logic. this is an active low signal. when deasserted the external docking switch is in isolate mode. when asserted the external docking switch electrically connects the intel hd audio dock signals to the corresponding intel ? ich8 signals. this signal is shared with gpio33 . this signal defa ults to gpio33 mode after pltrst# reset and wi ll be in the high state after pltrst# reset. bios is responsible for configuring gpio33 to hda_dock_en# mode. hda_dock_rst# (mobile only) / gpio34 i/o high definition audio dock reset: this signal is a dedicated hda_rst# signal for the codec(s) in the docking station. aside from operating independently from the normal hda_rst# signal, it otherwise works similarly to the hda_rst# signal. this signal is shared with gpio34 . this signal defa ults to gpio34 mode after pltrst# reset and wi ll be in the low state after pltrst# reset. bios is responsible for configuring gpio34 to hda_dock_rst# mode. table 23. intel ? high definition audio li nk signals (sheet 2 of 2) name type description table 24. serial peripheral interface (spi) signals name type description spi_cs0# o spi chip select 0 : used as the spi bus request signals. spi_cs1# i/o spi chip select 1 : used as the spi bus requ est signals. this signal is also used as boot bios destination selection strap with gnt0#. spi_miso i spi master in slave out : data input pin for ich8. spi_mosi o spi master out slave in : data output pin for ich8. spi_clk o spi clock : spi clock signal, du ring idle the bus owner will drive the clock signal low. 17.86 mhz and 31.25 mhz. signal description 82 intel ? ich8 family datasheet 2.21 intel ? quick resume technology (intel ? ich8dh only) 2.22 controller link table 25. intel ? quick resume technology signals name type description qrt_state[1:0] / gpio[28:27] i/o intel quick resume technology state: intel quick resume technology status signals that ma y optionally be used to drive front chassis indicators. see section 5.26.3 for details. when intel quick resume technology is enabled, the signals will function as qrt_state[1:0] only. otherwise, the signals are used as gpios. table 26. controller link signals name type description cl_clk0 i/o controller li nk clock 0 : this signal is a bi-directional clock that connects to the (g)mch. cl_data0 i/o controller link data 0: this signal is a bi-d irectional data signal that connects to the (g)mch. cl_vref0 i controller link re ference voltage 0: this signal ia an external reference voltage for controller link 0. cl_rst0# o north controller link re set that connects to the (g)mch. cl_rst1# / linkalert# od/o controller link reset: south controller link reset that connects to a device support ing intel active managment technology. when used as cl_rst1#, no external pullup or pulldown should be used. cl_clk1 (mobile only)/ tp5 (desktop only) i/o controller li nk clock 1 : this signal is a bi-directional clock that connects to a device supporting intel ? active management technology cl_data1 (mobile only) tp4 (desktop only) i/o controller link data 1: this is a bi-directional data signal that connects to a device supporting intel ? active management technology. cl_vref1 (mobile only) tp6 (desktop only) i controller link reference voltage: this signal is an external reference voltage for controller link 1. intel ? ich8 family datasheet 83 signal description 2.23 intel ? quiet system technology (desktop only) 2.24 general purpose i/o signals table 27. intel ? quiet system technology signals name type description pwm[2:0] od fan pulse width modulation outputs: this is a pulse width modulated duty cycle output sign al that is used intel quiet system technology. when controlling a 3-wire fan, this signal controls a power transistor that, in turn, cont rols power to the fan. when controlling a 4-wire fan, this sign al is connected to the ?control? signal on the fan. the polarity of this signal is programmable. the output default is low. these signals are 5 v tolerant. tach0 /gpio17 tach1 /gpio1 tach2 /gpio6 tach3 /gpio7 i fan tachometer inputs: these are tachometer pulse input signals that are used to meas ure fan speed. the signals are connected to the ?sense? signal on the fan. can instead be used as a gpio signal. sst i/o simple serial transport: single-wire, serial bus. connect to sst compliant devices such as sst thermal sensors or voltage sensors. peci i/o platform environmental control interface: single-wire, serial bus. this signal connects to the corresponding pin of the processor for accessing proc essor digital thermometer. table 28. general purpose i/ o signals (sheet 1 of 3) name type tolerance power well default description gpio55 i/o 3.3 v core native multiplexed with gnt3# gpio54 i/o 5.5 v core native multiplexed with req3# (note 5) gpio53 i/o 3.3 v core native multiplexed with gnt2# gpio52 i/o 5.5 v core native multiplexed with req2# (note 5) gpio51 i/o 3.3 v core native multiplexed with gnt1# gpio50 i/o 5.5 v core native multiplexed with req1# (note 5) gpio49 i/o v_cpu_io v_cpu_io native multiplexed with cpupwrgd (note 4) gpio48 i/o 3.3 v core gpi multiplexed with sdataout1 gpio[47:44] n/a n/a n/a n/a not implemented. gpio[43:40] i/o 3.3 v resume native multiplexed with oc[4:1]# (note 5) gpio39 i/o 3.3v core gpi multiplexed with sdataout0 gpio38 i/o 3.3 v core gpi multiplexed with sload signal description 84 intel ? ich8 family datasheet gpio37 i/o 3.3 v core gpi mobile: unmultiplexed. desktop: multiplexed with sata3gp. gpio36 i/o 3.3 v core gpi multiplexed with sata2gp. gpio35 i/o 3.3 v core gpo multiplexed with sataclkreq#. gpio34 i/o 3.3 v core gpo mobile: multiplexed with hda_dock_rst#. desktop: unmultiplexed. gpio33 i/o 3.3 v core gpo mobile: multiplexed with hda_dock_en#. desktop: unmultiplexed. gpio32 (desktop only) i/o 3.3 v core gpo mobile: this gpio is not implemented and is used instead as clkrun#. desktop: unmultiplexed. gpio31 i/o 3.3 v resume native multiplexed with oc7# (note 5) gpio30 i/o 3.3 v resume native multiplexed with oc6# (note 5) gpio29 i/o 3.3 v resume native multiplexed with oc5# (note 5) gpio28 i/o 3.3 v resume gpo digital home: multiplexed with qrt_state1 ich8 base: unmultiplexed. gpio27 i/o 3.3 v resume gpo digital home: multiplexed with qrt_state0 ich8 base: unmultiplexed. gpio26 i/o 3.3 v resume native multiplexed with s4_state# gpio25 (desktop only) i/o 3.3 v resume native mobile: this gpio is not implemented and is used instead as stp_cpu# desktop: default as stp_cpu# (note 3) gpio24 i/o 3.3 v resume gpo mobile: multiplexed with mem_led desktop: multiplexed with clgpio0. not cleared by cf9h reset event. gpio23 i/o 3.3 v core native multiplexed with ldrq1# (note 5) gpio22 i/o 3.3 v core gpi multiplexed with sclock gpio21 i/o 3.3 v core gpi multiplexed with sata0gp. gpio20 i/o 3.3 v core gpo unmultiplexed gpio19 i/o 3.3 v core gpi multiplexed with sata1gp gpio18 i/o 3.3 v core gpo unmultiplexed gpio17 i/o 3.3 v core gpi multiplexed with tach0 table 28. general purpose i/o signals (sheet 2 of 3) name type tolerance power well default description intel ? ich8 family datasheet 85 signal description notes: 1. gpi[15:0] can be configured to cause a smi# or sci. note that a gpi can be routed to either an smi# or an sci, but not both. 2. some gpios exist in the vccsus3_3 power plan e. care must be take n to make sure gpio signals are not driven high into powere d-down planes. some ich8 gpios may be connected to pins on devices that exist in the core well. if these gpios are outputs, there is a danger that a loss of core power (pwrok low) or a power button override event will result in the intel ich8 driving a pin to a lo gic 1 to another device that is powered down. 3. the functionality that is multiplexed with the gpio may not be used in desktop configuration. 4. this gpio is not capable of ac tively driving high. this gpio is tristated as an output and an external pull-up is needed to pull the signal high). gpio16 i/o 3.3 v core native (mobile) / gpo (desktop) mobile: natively used as dprslpvr. desktop: unmultiplexed. gpio15 (desktop only) i/o 3.3 v resume native mobile: gpio is not implemented and is used instead as stp_pci#. desktop: default as stp_pci# (note 3) gpio14 i/o 3.3 v resume gpi mobile: multiplexed with ac_present desktop: unmultiplexed gpio13 i/o 3.3v resume native (mobile) / gpi (desktop) mobile: natively used as energy_detect desktop: unmultiplexed gpio12 i/o 3.3 v resume native (mobile) / gpi (desktop) mobile: natively used as glan_dock# desktop: unmultiplexed. gpio11 i/o 3.3 v resume native multiplexed with smbalert# (note 5) gpio10 i/o 3.3 v resume gpi mobile: multiplexed with suspwrack/alert# desktop: unmultiplexed gpio9 i/o 3.3 v resume gpi refer to table 19 for signal description. gpio8 i/o 3.3 v resume gpi unmultiplexed gpio[7:6] i/o 3.3 v core gpi mobile: unmultiplexed desktop: multiplexed with tach[3:2] gpio[5:2] i/od 5 v core gpi multiplexed with pirq[h:e]# gpio1 i/o 3.3 v core gpi multiplexed with tach1 gpio0 i/o 3.3 v core gpi mobile: multiplexed with bm_busy# desktop: unmultiplexed table 28. general purpose i/ o signals (sheet 3 of 3) name type tolerance power well default description signal description 86 intel ? ich8 family datasheet 5. when the multiplexed gpio is used as gpio functionality, ca re should be taken to ensure the signal is stable in its inactive state of the native functionality, immediately after reset until it is initialized to gpio functionality. 2.25 power and ground table 29. power and ground signals (sheet 1 of 2) name description vcc3_3 3.3 v supply for core well i/o buffers. this power may be shut off in s3, s4, s5 or g3 states. vcc1_05 1.05 v supply for core well logic. this po wer may be shut off in s3, s4, s5 or g3 states. vcc1_5_a 1.5 v supply for logic and i/o. this power may be shut off in s3, s4, s5 or g3 states. vcc1_5_b 1.5 v supply for logic and i/o. this power may be shut off in s3, s4, s5 or g3 states. vcc_dmi power supply for dmi. 1.25v or 1. 5v depending on (g)mch?s dmi voltage. v5ref reference for 5 v tolerance on core well inputs. this power may be shut off in s3, s4, s5 or g3 states. vccsus3_3 3.3 v supply for resume well i/o buffers. this power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drai ned and ac power is not available in mobile configurations. vccsus1_5 1.5v supply for the resume well i/o. this power is not expected to be shut off unless the system is unplugged in desktop configurations. this voltage is generated internally (see section 2.26.1 for strapping option). and these pins can be left as nc unless decoupling is required. vccsus1_05 1.05 v supply for resume well logic. this power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and ac power is not available in mobile configurations. this voltage is generated internally (see section 2.26.1 for strapping option). and these pins can be left as nc unless decoupling is required. v5ref_sus reference for 5 v tolerance on resume well inputs. th is power is not expected to be shut off unless the sy stem is unplugged in desktop configurations or the main battery is removed or completely dr ained and ac power is not available in mobile configurations. vccglan1_5 1.5v supply for integrated gigabit lan i/ o buffers. this power can be turned off if the integrated gigabit lan is not used. if the integrated gigabit lan is used, the power is off in s3, s4, s5. vccglan3_3 3.3v supply for integrated gigabit lan lo gic and i/o. this power can be turned off if the integrated gigabit lan is not used. if the integrated gigabit lan is used, the power is off in s3, s4, s5. vcccl1_05 1.05v supply for controller link. this vo ltage may be generate d internally (see section 2.26.1 for strapping option). this pin mu st be connected to an external 1.05 v power supply when the integrated vrm is disabled . this pin can be left as nc if the internal vrm is used unless decoupling is required. intel ? ich8 family datasheet 87 signal description vcccl1_5 1.5v supply for controller link. this pl ane must be on in s0 and other times controller link is used. this voltage is generated internally (see section 2.26.1 for strapping option). and these pins can be left as nc unless decoupling is required. vcccl3_3 3.3v supply for controller link. this is a separate power plane that may or may not be powered in s3?s5 states. this pl ane must be on in s0 and other times controller link is used. note: vcccl3_3 must always be powered when vcclan3_3 is powered. vcclan3_3 3.3 v supply for lan connect interface bu ffers. this is a separate power plane that may or may not be powered in s3?s5 states. note: vcclan3_3 must always be powered when vcccl3_3 or vcc3_3 is powered. vcclan1_05 1.05 v supply for lan controller logic. th is is a separate power plane that may or may not be powered in s3?s5 states. this voltage is generated internally (see section 2.26.1 for strapping option). and these pins can be left as nc unless decoupling is required.. vccsushda suspend supply for intel high definition audio. this pin can be either 1.5 or 3.3 v. this power is not expected to be sh ut off unless the system is unplugged in desktop configurations or the main batt ery is removed or completely drained and ac power is not available in mobile configurations. vcchda core supply for intel high definition audio. this pin can be either 1.5 or 3.3 v. this power may be shut off in s3, s4, s5 or g3 states. vccrtc 3.3 v (can drop to 2.0 v min. in g3 st ate) supply for the rt c well. this power is not expected to be shut off unless the rtc battery is re moved or completely drained. note: implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. clearing cmos in an intel ? ich8-based platform can be done by using a jumper on rtcrst# or gpi. vccusbpll 1.5 v supply for core well logic. this sign al is used for the usb pll. this power may be shut off in s3, s4, s5 or g3 st ates. must be powere d even if usb not used. vccdmipll 1.5 v supply for core well lo gic. this signal is used for the dmi pll. this power may be shut off in s3, s4, s5 or g3 states. vccsatapll 1.5 v supply for core well logi c. this signal is used for the sata pll. this power may be shut off in s3, s4, s5 or g3 st ates. must be powere d even if sata is not used. vccglanpll 1.5v supply for core will logic. this sign al is used for the integrated gigabit lan pll. this power is shut off in s3, s4, s5 and g3 states. v_cpu_io powered by the same supply as the proces sor i/o voltage. this supply is used to drive the processor inte rface signals listed in table 17 . vss grounds. vss_ntsc (mobile only) not critical to function; balls are for im proved package reliability. these signals are connected to gnd on the chipset package, and can be connected to gnd or left as nc on the platform (c an be left as test points). note: there is no functional impact if these signals are grounded. table 29. power and ground signals (sheet 2 of 2) name description signal description 88 intel ? ich8 family datasheet 2.26 pin straps 2.26.1 functional straps the following signals are used for static configuration. they are sampled at the rising edge of pwrok to select configurations (excep t as noted), and then revert later to their normal usage. to invoke the associated mode, the signal should be driven at least four pci clocks prior to the time it is sampled. intel ? ich8 has implemented a new feature called soft straps. soft straps are used to configure specific functions within the ich8 and (g)mch very early in the boot process before bios or software intervention. when descriptor mode is enabled, the ich8 will read soft strap data out of the spi device prior to the de-assertion of reset to both the manageability engine and the host system. refer to section 5.23.1.1 for information on descriptor mode and section 20.2.5 for more information on soft straps and their settings table 30. functional strap de finitions (sheet 1 of 2) signal usage when sampled comment hda_sdout xor chain entrance / pci express* port config 1, bit 1 (port 1?4) rising edge of pwrok allows entrance to xor chain testing when tp3 pulled low at rising edge of pwrok. when tp3 not pulled low at rising edge of pwrok, sets bit 1 of rpc.pc (chipset configuration registers:offset 224h).this signal has a weak internal pull-down. hda_sync pci express port config 1, bit 0 (port 1?4) rising edge of pwrok this signal has a weak internal pull-down. sets bit 0 of rpc.pc (chipset configuration registers:offset 224h) gnt2# pci express port config 2, bit 0 (port 5?6) rising edge of pwrok this signal has a weak internal pull-up. sets bit 2 of rpc.pc2 (chipset configuration registers:offset 0224h) when sampled low. gpio20 reserved rising edge of pwrok this signal has a weak internal pull-down. note: this signal should not be pulled high gnt1#/gpio51 esi strap (server only) rising edge of pwrok tying this strap low configures dmi for esi- compatible operation. th is signal has a weak internal pull-up. note: esi compatible mode is for server platforms only. this signal should not be pulled low for desktopand mobile. gnt3# top-block swap override rising edge of pwrok the signal has a weak in ternal pull-up. if the signal is sampled low, this indicates that the system is strapped to the ?top-block swap? mode (intel ? ich8 inverts a16 for all cycles targeting bios space). the status of this strap is readable via the top swap bit (chipset configuration registers:offset 3414h:bit 0). note that software will not be able to clear the top-swap bit until the system is rebooted without gnt3# being pulled down. intel ? ich8 family datasheet 89 signal description note: 1. see section 3.1 for full details on pull-up/pull-down resistors. 2. when strapped, the spi_cs1# pin is required to be held at the strapped value for the minimum of 200 ns with respect to the rising edge of either the clpwrok pin or the lan_rst# pin, whichever rises fi rst. note that the hold time is also required to meet the minimum of 101 ms after the rsmrst# pin is de asserted in the case both ich8 me well and aux well are connected to the resume well power. gnt0#, spi_cs1# boot bios destination selection rising edge of pwrok (note 1) this field determines the destination of accesses to the bios memory range. signals have weak internal pull-ups. also controllable via boot bios destination bit (chipset configuration registers:offset 3410h:bit 11:10). (gnt0# is msb) 01 = spi 10 = pci 11 = lpc note: booting to pci is intended for debug/ testing only. boot bios destination select to lpc/pci by functional strap or via boot bios destination bit will not affect spi accesses initiated by me or integrated gbe lan. intvrmen integrated vccsus1_05, vccsus1_5, and vcccl1_5 vrm enable always enables integrated vccs us1_05, vccsus1_5 and vcccl1_5 vrms. pin must be pulled-up to vccrtc. lan100_slp integrated vcclan1_05 and vcccl1_05 vrm enable always enables integrated vcclan1_05 and vcccl1_05 vrms. pin must be pu lled-up to vccrtc. sataled# pci express lane reversal (lanes 1?4) rising edge of pwrok signal has weak internal pull-up. sets bit 27 of mpc.lr (device 28: function 0: offset d8) spkr no reboot rising edge of pwrok the signal has a weak inte rnal pull-down. if the signal is sampled high, this indicates that the system is strapped to the ?no reboot? mode (ich8 will disable the tc o timer system reboot feature). the status of th is strap is readable via the no reboot bit (chipset configuration registers:offset 3410h:bit 5). tp3 xor chain entrance rising edge of pwrok see chapter 29 for functionalit y information. this signal has a we ak internal pull-up. note: this signal should not be pulled low unless using xor chain testing. gpio33 / hda_dock_en# flash descriptor security override strap rising edge of pwrok this signal has a weak internal pull-up. if sampled low, the flash descriptor security will be overridden. if high, the security measures defined in the flash descri ptor will be in effect. note: this should only be used in manufacturing environments. table 30. functional strap de finitions (sheet 2 of 2) signal usage when sampled comment signal description 90 intel ? ich8 family datasheet 2.26.2 external rtc circuitry to reduce rtc well power consumption, the ich8 implements an internal oscillator circuit that is sensitive to step voltage changes in vccrtc. figure 3 shows an example schematic recommended to ensure correct operation of the ich8 rtc. note: c1 and c2 depend on crystal load. figure 3. example external rtc circuit 32.768 khz xtal 1 f (20% tolerance) c2 15 pf (5% tolerance) vccrtc rtcx2 rtcx1 vbatt 1 f (20% tolerance) 1 k vccsus3_3 c1 15 pf (5% tolerance) + r1 10 m ? rtcrst# 20 k schottky diodes intel ? ich8 family datasheet 91 intel ? ich8 pin states 3 intel ? ich8 pin states 3.1 integrated pull-ups and pull-downs notes: 1. simulation data shows that these resistor values can range from 10 k to 40 k . 2. simulation data shows that these resistor values can range from 9 k to 50 k . 3. simulation data shows that these resistor values can range from 15 k to 35 k 4. simulation data shows that these resistor values can range from 7.5k to 16 k . 5. simulation data shows that these resistor values can range from 14.25 k to 24.8 k 6. simulation data shows that these resistor values can range from 10 k to 30 k . 7. the pull-up or pull-down on this signal is only enabled at b oot/reset for strapping function. 8. simulation data shows that these resistor values can range from 10 k to 20 k . the internal pull-up is only enab led during pltrst# assertion. 9. the pull-down on this signal is only enabled when in s3. 10. simulation data shows that these resistor values can range from 5.7 k to 28.3 k . 11. the integrated resistors are disabled after pltrst# de-assertion. table 31. integrated pull-u p and pull-down resistors signal resistor ty nominal val notes dd[7] pull-down 15 k 10 ddreq pull-down 15 k 10 hda_bit_clk pull-down 20 k 1,9 hda_rst# none n/a hda_sdin[3:0] pull-down 20 k 2 hda_sdout pull-down 20 k 3 hda_sync pull-down 20 k 2 gnt[3:0] pull-up 20 k 3, 7 gpio[20] pull-down 20 k 3 gpio33 pull-up 20 k 3 gpio 48 pull-up 20 k 3, 11 gpio[18, 19, 21, 32, 35, 37] pull-down 20 k 3, 11 lad[3:0]# / fhw[3:0]# pull-up 20 k 3 lan_rxd[2:0] pull-up 10 k 4 ldrq[0] pull-up 20 k 3 ldrq[1] / gpio23 pull-up 20 k 3 pme# pull-up 20 k 3 pwrbtn# pull-up 20 k 3 sataled# pull-up 15 k 8 spi_cs1# pull-up 20 k 3 spi_miso pull-up 20 k 3 tach[3:0] pull-up 20 k 3 spkr pull-down 20 k 2 tp3 pull-up 20 k 6 usb[9:0] [p,n] pull-down 15 k 5 intel ? ich8 pin states 92 intel ? ich8 family datasheet 3.2 ide integrated series termination resistors (mobile only) table 32 shows the ich8m ide signals that have integrated series termination resistors. note: simulation data indicates that the integrated series termination resistors are a nominal 33 but can range from 21 to 75 . 3.3 output and i/o signals planes and states table 33 and table 34 shows the power plane associated with the output and i/o signals, as well as the state at various times. within the table, the following terms are used: ?high-z? tri-state. ich8 not driving the signal high or low. ?high? ich8 is driving the signal to a logic 1. ?low? ich8 is driving the signal to a logic 0. ?defined? driven to a level that is defined by the function or external pull- up/pull-down resistor (will be high or low). ?undefined? ich8 is driving the sign al, but the value is indeterminate. ?driven? will be high or low, will be allowed to change. ?running? clock is toggling or signal is transitioning because function not stopping. ?off? the power plane is off; ich8 is not driving when configured as an output or sampling when configured as an input. ?input? ich8 is sampling and signal state determined by external driver. note that the signal levels are the same in s4 and s5, except as noted. ich8 suspend well signal states are indete rminate and undefined and may glitch prior to rsmrst# deassertion. this does not apply to lan_rst#, slp_s3#, slp_s4#, slp_s5# and slp_m#. these signals are de terminate and defined prior to rsmrst# deassertion. ich8 core well signal states are indeterminate and undefined and may glitch prior to pwrok assertion. this does not apply to ferr# and thrmtrip#. these signals are determinate and defined prior to pwrok assertion. table 32. ide series termination resistors signal integrated series te rmination resistor value dd[15:0], diow#, dior#, dreq, ddack#, iordy, da[2:0], dcs1#, dcs3#, ideirq approximately 33 (see note) intel ? ich8 family datasheet 93 intel ? ich8 pin states table 33. power plane and states for output and i/o signals for desktop configurations (sheet 1 of 5) signal name power plane during reset 4 immediately after reset 4 s1 s3 s4/s5 pci express* petp[6:1], petn[6:1] core high high 8 defined off off dmi dmi[3:0]txp, dmi[3:0]txn core high high 8 defined off off pci bus ad[31:0] core low undefined defined off off c/be[3:0]# core low undefined defined off off devsel# core high-z high-z high-z off off frame# core high-z high-z high-z off off gnt0#, gnt[3:1]#/ gpio[55, 53, 51] core high-z with internal pull-up high high off off irdy#, trdy# core high-z high-z high-z off off par core low undefined defined off off pcirst# suspend low high high low low perr# core high-z high-z high-z off off plock# core high-z high-z high-z off off stop# core high-z high-z high-z off off lpc interface lad[3:0] / fwh[3:0] core high high high off off lframe# / fwh[4] core high high high off off platform lan connect interface lan_rstsync lan high low defined off off lan_txd[2:0] lan low low defined off off gigabit lan connect interface glan_txp, glan_txn glan high high defined off off sata interface sata[5:0]txp, sata[5:0]txn core high-z high-z defined off off sataled# core high-z high-z defined off off satarbias core high-z high-z high-z off off intel ? ich8 pin states 94 intel ? ich8 family datasheet sata5gp sata4gp sata3gp / gpio37 sata2gp / gpio36 sata1gp / gpio19 sata0gp / gpio21 core input input driven off off sataclkreq# / gpio35 core low low defined off off sclock/gpio22 core input input defined off off sload/gpio38 core input input defined off off sdataout[1:0]/ gpio[48,39] core input input defined off off interrupts pirq[a:d]#, pirq[h:e]# / gpio[5:2] core high-z high-z high-z off off serirq core high-z high-z high-z off off table 33. power plane and states for output and i/o signals for desktop configurations (sheet 2 of 5) signal name power plane during reset 4 immediately after reset 4 s1 s3 s4/s5 intel ? ich8 family datasheet 95 intel ? ich8 pin states usb interface usbp[9:0][p,n] suspend low low low low low usbrbias suspend high-z high-z defined defined defined power management pltrst# suspend low high high low low slp_m 9 suspend low high high driven driven slp_s3# suspend low high high low low slp_s4# suspend low high high high low slp_s5# suspend low high high high low 7 sus_stat# suspend low high high low low susclk suspend low running ck_pwrgd suspend low high low high high processor interface a20m# cpu dependant on a20gate signal see note 1 high off off cpupwrgd / gpio49 cpu defined high high off off cpuslp# cpu high high defined off off ignne# cpu high see note 1 high off off init# cpu high high high off off init3_3v# core high high high off off intr cpu see note 5 see note 5 low off off nmi cpu see note 5 see note 5 low off off smi# cpu high high high off off stpclk# cpu high high low off off smbus interface smbclk, smbdata suspend high-z high-z defined defined defined system management interface clgpio0 suspend high-z high -z defined defined defined wol_en suspend high-z high-z defined defined defined smlink[1:0] suspend high-z hi gh-z defined defined defined linkalert# suspend high-z high-z defined defined defined table 33. power plane and states for output and i/o signals for desktop configurations (sheet 3 of 5) signal name power plane during reset 4 immediately after reset 4 s1 s3 s4/s5 intel ? ich8 pin states 96 intel ? ich8 family datasheet miscellaneous signals spkr core high-z with internal pull-down low defined off off intel ? high definition audio interface hda_rst# hda suspend low low 8 running low low hda_sdout hda high-z with internal pull-down running low off off hda_sync hda high-z with internal pull-down running low off off hda_bit_clk hda high-z with internal pull-down low low off off unmultiplexed gpio signals gpio0 core input input driven off off gpio10 suspend high-z high-z defined defined defined gpio[13, 12, 8] suspend input input driven driven driven gpio14 suspend high-z high-z defined defined defined gpio15 suspend high high defined defined defined gpio16 core low low defined off off gpio18 core high see note 2 defined off off gpio20 core high high defined off off gpio25 core high high defined off off gpio[33:32] core high high defined off off gpio34 core low low defined off off spi interface spi_cs[1:0]# controller link high high high off off spi_mosi controller link high high high off off spi_clk controller link low low low off off intel ? quick resume technology interface (intel ? ich8dh only) qrt_state[1:0] / gpio[28:27] suspend low low defined defined defined table 33. power plane and states for output and i/o signals for desktop configurations (sheet 4 of 5) signal name power plane during reset 4 immediately after reset 4 s1 s3 s4/s5 intel ? ich8 family datasheet 97 intel ? ich8 pin states notes: 1. ich8 drives these signals hi gh after the processor reset 2. gpio[18] will toggle at a frequency of a pproximately 1 hz when the ich8 comes out of reset 3. cpupwrgd represents a logical and of th e ich8?s vrmpwrgd an d pwrok signals, and thus will be driven low by ich8 when either vrmpwrgd or pwrok are inactive. during boot, or during a hard reset wi th power cycling, cpupwrgd will be expected to transition from low to high-z. 4. the states of core and proc essor signals are evaluated at the times during pltrst# and immediately after pltrst #. the states of the lan and gl an signals are evaluated at the times during lan_rst# and immediately after lan_rst#. the states of the controller link signals are taken at th e times during cl_r st# and immediately after cl_rst#. the states of the suspend signals are evaluated at the times during rsmrst# and immediately after rsmrst#. th e states of the hda signals are evaluated at the times during hda_rst# and imme diately after hda_rst#. 5. ich8 drives these signals low before pwro k rising and low after the processor reset. 6. slp_s5# signals will be high in the s4 state. 7. low until intel high definition audio controller reset bit set (d27:f0:offset hdbar+08h:bit 0), at which time hda_rst# will be high and hda_bit_clk will be running. 8. petp/n[6:1] high until port is enabled by software. 9. the slp_m# state will be determined by intel ? amt policies. controller link cl_clk controller link low low low off off cl_data0 controller link low low low off off cl_rst# suspend low high high high high intel ? quiet system technology (desktop only) pwm[2:0] core low low defined off off sst controller link low low defined off off peci cpu low low defined off off table 33. power plane and states for output and i/o signals for desktop configurations (sheet 5 of 5) signal name power plane during reset 4 immediately after reset 4 s1 s3 s4/s5 intel ? ich8 pin states 98 intel ? ich8 family datasheet table 34. power plane and states for output and i/o signals for mobile configurations (sheet 1 of 4) signal name power plane during reset 4 immediately after reset 4 c3/c4 s1 s3 s4/s5 pci express* petp[6:1], petn[6:1] core high high 9 defined defined off off dmi dmi[3:0]txp, dmi[3:0]txn core high high 9 defined defined off off pci bus ad[31:0] core low undefined defined defined off off c/be[3:0]# core low undefined defined defined off off clkrun# core low low defined off off devsel# core high-z high-z high-z high-z off off frame# core high-z high-z high-z high-z off off gnt0#, gnt[3:1]#/ gpio[55, 53, 51] core high with internal pull- ups high high high off off irdy#, trdy# core high-z high-z high-z high-z off off par core low undefined defined defined off off pcirst# suspend low high high high low low perr# core high-z high-z high-z high-z off off plock# core high-z high-z high-z high-z off off stop# core high-z high-z high-z high-z off off lpc interface lad[3:0] / fwh[3:0] core high high high high off off lframe# / fwh[4] core high high high high off off platform lan connect interface lan_rstsync lan high low defined defined off off lan_txd[2:0] lan low low defined defined off off gigabit lan connect interface glan_txp, glan_txn glan high high defined defined off off ide interface da[2:0] core undefined undefined undefined undefined off off dcs1#, dcs3# core high high high high off off dd[15:8], dd[6:0] core high-z high-z defined high-z off off dd[7] core low low defined low off off ddack# core high high high high off off dior#, diow# core high high high high off off intel ? ich8 family datasheet 99 intel ? ich8 pin states sata interface sata[2:0]txp, sata[2:0]txn core high-z high-z de fined defined off off sataled# core high-z high -z defined defined off off satarbias core high-z high-z defined defined off off sata2gp / gpio36 sata1gp / gpio19 sata0gp / gpio21 core input input driven driven off off sataclkreq# / gpio35 core low low defined defined off off interrupts pirq[a:d]#, pirq[h:e]# / gpio[5:2] core high-z high-z defined high-z off off serirq core high-z high-z running high-z off off usb interface usb[9:0][p,n] suspend low low low low low low usbrbias suspend high-z high-z defined defined defined defined power management pltrst# suspend low high high high low low slp_m# suspend low high high high driven driven slp_s3# suspend low high high high low low slp_s4# suspend low high high high high low slp_s5# suspend low high high high high low8 stp_cpu# core high high defined high off off stp_pci# core high high defined high off off sus_stat# suspend low high high high low low dprslpvr core low low low/ high 4 high off off dprstp# core high high low/ high 4 high off off susclk suspend low running ck_pwrgd suspend low high low low high high processor interface a20m# cpu dependant on a20gate signal see note 1 defined high off off cpupwrgd / gpio49 cpu see note 3 high high high off off ignne# cpu high see note 1 high high off off init# cpu high high high high off off table 34. power plane and states for output and i/o signals for mobile configurations (sheet 2 of 4) signal name power plane during reset 4 immediately after reset 4 c3/c4 s1 s3 s4/s5 intel ? ich8 pin states 100 intel ? ich8 family datasheet intr cpu see note 6 see note 6 defined low off off nmi cpu see note 6 see note 6 defined low off off smi# cpu high high defined high off off stpclk# cpu high high low low off off dpslp# cpu high high high/low high off off smbus interface smbclk, smbdata suspend high-z high -z defined defined defined defined system management interface clgpio0/gpio24 suspend high-z high-z defined defined defined defined alert#/gpio10 suspend high-z high -z defined defined defined defined netdetect/gpio14 suspend high-z high-z defined defined defined defined wol_en/gpio9 suspend high-z high-z defined defined defined defined smlink[1:0] suspend high-z high-z defined defined defined defined linkalert# suspend high-z high-z defined defined defined defined miscellaneous signals spkr core high-z with internal pull- down low defined defined off off intel ? high definition audio interface hda_rst# hda suspend low low 8 high tbd low low hda_sdout hda high-z with internal pull- down running running low off off hda_sync hda high-z with internal pull- down running running low off off hda_bit_clk hda high-z with internal pull- down low 8 running low off off hda_dock_rst# / gpio34 hda suspend low low 9 defined defined off off hda_dock_en# / gpio33 hda high high defined defined off off unmultiplexed gpio signals gpio[12, 8] suspend input input driven driven driven driven gpio18 core high see note 2 driven driven off off gpio20 core high high defined defined off off table 34. power plane and states for output and i/o signals for mobile configurations (sheet 3 of 4) signal name power plane during reset 4 immediately after reset 4 c3/c4 s1 s3 s4/s5 intel ? ich8 family datasheet 101 intel ? ich8 pin states notes: 1. ich8 drives these signal s high after the cpu reset 2. gpio[18] will toggle at a frequency of a pproximately 1 hz when the ich8 comes out of reset 3. cpupwrgd represents a logical and of th e ich8?s vrmpwrgd an d pwrok signals, and thus will be driven low by ich8 when either vrmpwrgd or pwrok are inactive. during boot, or during a hard reset wi th power cycling, cpupwrgd will be expected to transition from low to high-z. 4. the states of core and proc essor signals are evaluated at the times during pltrst# and immediately after pltrst #. the states of the lan and gl an signals are evaluated at the times during lan_rst# and immediately after lan_rst#. the states of the controller link signals are evaluated at the times during cl_rst# an d immediately after cl_rst#. the states of the suspend signals are evaluated at the times during rsmrst# and immediately after rsmrst#. th e states of the hda signals are evaluated at the times during hda_rst# and imme diately after hda_rst#. 5. ich8 drives these signals low before pwro k rising and low after the processor reset. 6. slp_s5# signals will be high in the s4 state. 7. low until intel high definition audio controller reset bit set (d27:f0:offset hdbar+08h:bit 0), at which time hda_rst# will be high and hda_bit_clk will be running. 8. petp/n[6:1] high until port is enabled by software. 9. the slp_m# state will be determined by amt policies spi interface spi_cs[1:0]# controller link high high high high off off spi_mosi controller link high high high high off off spi_clk controller link low low low low off off controller link cl_clk 0 cl_data 0 controller link low low low low off off cl_clk 1 cl_data 1 suspend low low low low off off cl_rst# suspend low high high high high high table 34. power plane and states for output and i/o signals for mobile configurations (sheet 4 of 4) signal name power plane during reset 4 immediately after reset 4 c3/c4 s1 s3 s4/s5 intel ? ich8 pin states 102 intel ? ich8 family datasheet 3.4 power planes for input signals table 35 and table 36 shows the power plane associated with each input signal, as well as what device drives the signal at various times. valid states include: high low static: will be high or low, but will not change driven: will be high or low, and is allowed to change running: for input clocks table 35. power plane for input signals fo r desktop configurations (sheet 1 of 3) signal name power well driver during reset s1 s3 s4 / s5 dmi dmi_clkp, dmi_clkn core clock generator running off off dmi[3:0]rxp, dmi[3:0]rxn core (g)mch driven off off pci express* perp[6:1], pern[6:1] core pci express* device driven off off pci bus req0#, req1# / gpio50 1, 3 req2# / gpio52 1, 3 req3# / gpio54 1, 3 core external pull up driven off off pciclk core clock generator running off off pme# suspend internal pull-up driven driven driven serr# core pci bus peripherals high off off lpc interface ldrq0# core lpc devices high off off ldrq1# / gpio23 2 core lpc devices high off off platform lan connect interface glan_clk suspend lan connect component driven driven driven lan_rxd[2:0] suspend lan connect component driven driven driven gigabit lan connect interface glan_rxp glan_rxn suspend gigabit lan connect component driven driven driven sata interface sata_clkp, sata_clkn core clock generator running off off sata[3:0]rxp, sata[3:0]rxn core sata drive driven off off satarbias# core external pull-down driven off off sata[5:4]gp sata[3:0]gp / gpio[37,36,19] 1 core external device or external pull-up/pull-down driven off off usb interface intel ? ich8 family datasheet 103 intel ? ich8 pin states oc0#, oc[7:1]# / gpio[31, 30, 29, 43, 42,41, 40], oc[9:8]# suspend external pull-ups driven driven driven usbrbias# suspend external pull-down driven driven driven power management clpwrok suspend external circuit driven driven driven lan_rst# suspend external circuit high high high mch_sync# core (g)mch driven off off pwrbtn# suspend internal pull-up driven driven driven pwrok rtc system power supply driven off off ri# suspend serial port buffer driven driven driven rsmrst# suspend external rc circuit high high high sys_reset# suspend external circuit driven driven driven thrm# core thermal sensor driven off off thrmtrip# core thermal sensor driven off off vrmpwrgd suspend processor voltage regulator high low low wake# suspend external pull-up driven driven driven processor interface a20gate core external microcontroller static off off ferr# core processor static off off rcin# core external microcontroller high off off smbus interface smbalert# / gpio11 1 suspend external pull-up driven driven driven system management interface intruder# rtc external switch driven high high miscellaneous signals intvrmen rtc external pull-up high high high lan100_slp rtc external pull-up high high high rtcrst# rtc external rc circuit high high high tp[0] suspend external pull-up high high high tp[3] suspend internal pull-up high high high intel ? high definition audio interface hda_sdin[3:0] suspend intel ? high definition audio codec low low low table 35. power plane for input signals fo r desktop configurations (sheet 2 of 3) signal name power well driver during reset s1 s3 s4 / s5 intel ? ich8 pin states 104 intel ? ich8 family datasheet notes: 1. these signals can be configured as outputs in gpio mode. 2. the state of the dprslpvr and dprstp# signals in c4 are high if deeper sleep is enabled or low if it is disabled. 3. gpio50, gpio52, gpio54 need to be glitch free immediately after reset to when they are being initialized to gpio. multiplexed gpio sign als defaulting to a nati ve function must be glitch free immediately after reset until the time they are initialized as gpio. spi interface spi_miso suspend internal pull-up driven driven driven fan speed control tach[3:0]/ gpio[7,6,1,17] 1 core external pull-up driven off off clocks clk14 core clock generator running off off clk48 core clock generator running off off table 35. power plane for input signals fo r desktop configurations (sheet 3 of 3) signal name power well driver during reset s1 s3 s4 / s5 table 36. power plane for input signals fo r mobile configurations (sheet 1 of 3) signal name power well driver during reset c3/c4 s1 s3 s4/s5 dmi dmi_clkp dmi_clkn core clock generator running running off off dmi[3:0]rxp, dmi[3:0]rxn core (g)mch driven driven off off pci express perp[6:1], pern[6:1] core pci express* device driven driven off off pci bus pciclk core clock generator running running off off pme# suspend internal pull-up driven driven driven driven req0#, req1/gpio50 1, 3 req2/gpio52 1, 3 req3/gpio53 1, 3 core external pull up driven driven off off serr# core pci bus peripherals driven high off off lpc interface ldrq0# core lpc devices driven high off off ldrq1# / gpio23 1 core lpc devices driven high off off platform lan connect interface glan_clk suspend lan connect component driven driven driven driven intel ? ich8 family datasheet 105 intel ? ich8 pin states lan_rxd[2:0] suspend lan connect component driven driven driven driven gigabit lan connect interface glan_rxp glan_rxn suspend gigabit lan connect component driven driven driven driven sata interface sata_clkp, sata_clkn core clock generator running running off off sata[2:0]rxp, sata[2:0]rxn core sata drive driven driven off off satarbias# core external pull-down driven driven off off sata[5:4]gp sata[3:0]gp / gpio[37, 36, 19] 1 core external device or external pull-up/pull- down driven driven off off ide interface ddreq core ide device driven static off off ideirq core ide driven static off off iordy core ide device static static off off usb interface oc0#, oc[7:1]# / gpio[31, 30, 29, 43, 42,41, 40], oc[9:8]# suspend external pull-ups driven driven driven driven usbrbias# suspend external pull-down driven driven driven driven power management bmbusy# /gpio0 1 core graphics component [(g)mch] driven high off off clpwrok suspend external circuit driven driven driven driven lan_rst# suspend power supply high high static static mch_sync# core (g)mch driven driven off off pwrbtn# suspend internal pull -up driven driven driven driven pwrok rtc system power supply driven driven off off ri# suspend serial port buffer driven driven driven driven rsmrst# suspend external rc circuit high high high high sys_reset# suspend external circuit driven driven driven driven thrm# core thermal sensor driven driven off off thrmtrip# core thermal sensor driven driven off off vrmpwrgd suspend processor voltage regulator driven driven low low wake# suspend external pull-u p driven driven driven driven table 36. power plane for input signals fo r mobile configuratio ns (sheet 2 of 3) signal name power well driver during reset c3/c4 s1 s3 s4/s5 intel ? ich8 pin states 106 intel ? ich8 family datasheet note: 1. these signals can be configured as outputs in gpio mode. 2. the state of the dprslpvr and dprstp# signals in c4 are high if deeper sleep is enabled or low if it is disabled. 3. gpio50, gpio52, gpio54 need to be glitch free immediately after reset to when they are being initialized to gpio. multiplexed gpio sign als defaulting to a nati ve function must be glitch free immediately after reset until the time they are initialized as gpio. processor interface a20gate core external microcontroller static static off off ferr# core processor static static off off rcin# core external microcontroller high high off off smbus interface smbalert# / gpio11 1 suspend external pull-up driven driven driven driven system management interface intruder# rtc external switch driven driven high high miscellaneous signals batlow# suspend power supply high high high high intvrmen rtc external pull-up high high high high lan100_slp rtc external pull-up high driven high high rtcrst# rtc external rc circuit high high high high tp[3] suspend internal pull-up high high high high intel ? high definition audio interface hda_sdin[3:0] suspend intel ? high definition audio codec driven low low low spi interface spi_miso suspend internalpull-up driven driven driven driven clocks clk14 core clock generator running running off off clk48 core clock generator running running off off table 36. power plane for input signals fo r mobile configurations (sheet 3 of 3) signal name power well driver during reset c3/c4 s1 s3 s4/s5 intel ? ich8 family datasheet 107 intel ? ich8 and system clock domains 4 intel ? ich8 and system clock domains table 37 shows the system clock domains. figure 4 and figure 5 shows the assumed connection of the various system components, including the clock generator in both desktop and mobile systems. for complete deta ils of the system clocking solution, refer to the system?s clock generator component specification. table 37. intel ? ich8 and system clock domains clock domain frequency source usage ich8 sata_clkp, sata_clkn 100 mhz main clock generator differential clock pair used for sata. ich8 dmi_clkp, dmi_clkn 100 mhz main clock generator differential clock pair used for dmi. ich8 pciclk 33 mhz main clock generator free-running pci clock to intel ? ich8. this clock remains on during s0 and s1 (in desktop) state, and is expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations. system pci 33 mhz main clock generator pci bus, lpc interface. these clocks only go to external pci and lpc devi ces. these clocks will stop based on clkrun# (and stp_pci#) in mobile configurations. ich8 clk48 48.000 mhz main clock generator super i/o, usb controllers. this clock is expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations. ich8 clk14 14.31818 mhz main clock generator used for acpi timer an d multimedia timers. this clock is expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations. glan_clk 5 to 62.5 mhz lan connect component generated by the lan connect component. this clock is expected to be shut off during s3 or below in desktop configur ations or s1 or below in mobile configurations. spi_clk 17.86 mhz/ 31.25 mhz ich8 generated by the ich8. this clock is expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations. intel ? ich8 and system clock domains 108 intel ? ich8 family datasheet figure 4. desktop conceptu al system clock diagram figure 5. mobile conceptual clock diagram intel ich8 pci clocks (33 mhz) clock gen. 14.31818 mhz 48.000 mhz 32 khz xtal susclk# (32 khz) lan connect 62.5 mhz hd audio codec(s) 33 mhz 14.31818 mhz 100 mhz diff. pair 1 to 6 differential clock fan out device sata 100 mhz diff. pair dmi 100 mhz diff. pair pci express 100 mhz diff. pairs 24 mhz 48.000 mhz intel ich8-m 32 khz xtal susclk# (32 khz) 14.31818 mhz stp_cpu# stp_pci# pci clocks (33 mhz) clock gen. 14.31818 mhz 48 mhz lan connect 100 mhz diff. pair sata 100 mhz di ff. pair dmi 100 mhz diff. pair pci express 100 mhz diff. pairs hd audio codec(s) 24 mhz 62.5 mhz 48.000 mhz 33 mhz 1 to 6 differential clock fan out device intel ? ich8 family datasheet 109 functional description 5 functional description this chapter describes the functions and interfaces of the ich8 family. 5.1 pci-to-pci bridge (d30:f0) the pci-to-pci bridge resides in pci device 30, function 0 on bus #0. this portion of the ich8 implements the buffering and co ntrol logic between pci and direct media interface (dmi). the arbitration for the pci bus is handled by this pci device. the pci decoder in this device must decode the rang es for the dmi. all register contents are lost when core well power is removed. direct media interface (dmi) is the chip-to-chip connection between the memory controller hub / graphics and memory cont roller hub ((g)mch) and i/o controller hub 8 (ich8). this high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. base functionality is completely software transpar ent permitting current and legacy software to operate normally. in order to provide for true isochronous tr ansfers and configurable quality of service (qos) transactions, the ich8 supports two virtual channels on dmi: vc0 and vc1. these two channels provide a fixed arbitration scheme where vc1 is always the highest priority. vc0 is the default conduit of traffic for dmi and is always enabled. vc1 must be specifically enabled and configured at both ends of the dmi link (i.e., the ich8 and (g)mch). configuration registers for dmi, virtual ch annel support, and dmi active state power management (aspm) are in the rcrb sp ace in the chipset config registers ( section 7 ). 5.1.1 pci bus interface the ich8 pci interface supports pci local bus specification, revision 2.3 , at 33 mhz. the ich8 integrates a pci arbiter that suppor ts up to four external pci bus masters in addition to the internal ich8 requests. 5.1.2 pci bridge as an initiator the bridge initiates cycles on the pci bus wh en granted by the pci arbiter. the bridge generates the following cycle types: table 38. pci bridge initiator cycle types command c/be# notes i/o read/write 2h/3h non-posted memory read/write 6h/7h writes are posted configuration read/write ah/bh non-posted special cycles 1h posted functional description 110 intel ? ich8 family datasheet 5.1.2.1 memory reads and writes the bridge bursts memory writes on pci that are received as a single packet from dmi. i/o reads and writes the bridge generates single dw i/o read and write cycles. when the cycle completes on pci bus, the bridge generates a correspon ding completion on dmi. if the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.2 configuration reads and writes the bridge generates single dw configuration read and write cycles. when the cycle completes on pci bus, the bridge generates a corresponding completion. if the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.3 locked cycles the bridge propagates locks from dmi per the pci local bus specification . the pci bridge implements bus lock, which means the arbiter will not grant to any agent except dmi while locked. if a locked read results in a target or mast er abort, the lock is not established (as per the pci local bus specification ). agents north of the ich8 must not forward a subsequent locked read to the bridge if th ey see the first one finish with a failed completion. 5.1.2.4 target / master aborts when a cycle initiated by the bridge is ma ster/target aborted, the bridge will not re- attempt the same cycle. for multiple dw cycles, the bridge increments the address and attempts the next dw of the transaction. for all non-postable cycles, a target abort response packet is returned for each dw that was master or target aborted on pci. the bridge drops posted writes that abort. 5.1.2.5 secondary master latency timer the bridge implements a master latency timer via the slt register which, upon expiration, causes the de-assertion of frame# at the next valid clock edge when there is another active request to use the pci bus. 5.1.2.6 dual address cycle (dac) the bridge will issue full 64-bit dual a ddress cycles for device memory-mapped registers above 4 gb. intel ? ich8 family datasheet 111 functional description 5.1.2.7 memory and i/o decode to pci the pci bridge in the ich8 is a subtractive decode agent , which follows the following rules when forwarding a cycle from dmi to the pci interface: ? the pci bridge will positively decode any memory/io address within its window registers, assuming pcicmd.mse (d30:f0:offset 04h:bit 1) is set for memory windows and pcicmd.iose (d30:f0:offset 04h:bit 0) is set for io windows. ? the pci bridge will subtractively decode any 64-bit memo ry address not claimed by another agent, assuming pcicmd.mse (d30:f0:offset 04h:bit 1) is set. ? the pci bridge will subtractively decode any 16-bit i/o address not claimed by another agent assuming pcicmd.iose (d30:f0:offset 04h:bit 0) set ? if bctrl.ie (d30:f0:offset 3eh:bit 2) is set, the pci bridge will not positively forward from primary to secondary called out ranges in the io window per pci local bus specification (i/o transactions addressing the last 768 bytes in each, 1-kb block: offsets 100h to 3ffh). the pci bridge will still take them subtractively assuming the above rules. ? if bctrl.vgae (d30:f0:offset 3eh:bit 3) is set, the pci bridge will positively forward from primary to secondary i/o and memory ranges as called out in the pci bridge specificatio n, assuming the above rules are met. 5.1.3 parity error detection and generation pci parity errors can be detected and repo rted. the following behavioral rules apply: ? when a parity error is detected on pci, the bridge sets the secsts.dpe (d30:f0:offset 1eh:bit 15). ? if the bridge is a master and bctrl.pere (d30:f0:offset 3eh:bit 0) and one of the parity errors defined below is detected on pci, then the bridge will set secsts.dpd (d30:f0:offset 1eh:bit 8) and will also generate an internal serr#. ? during a write cycle, the perr# signal is active, or ? a data parity error is detected while performing a read cycle ? if an address or command parity error is detected on pci and pcicmd.see (d30:f0:offset 04h:bit 8), bctrl.pere, and bctrl.see (d30:f0:offset 3eh:bit 1) are all set, the bridge will set the psts.sse (d30:f0:offset 06h:bit 14) and generate an internal serr#. ? if the psts.sse is set because of an ad dress parity error and the pcicmd.see is set, the bridge will generate an internal serr# ? when bad parity is detected from dmi, bad parity will be driven on all data the bridge. ? when an address parity error is detected on pci, the pci bridge will never claim the cycle. this is a slight deviation from the pci bridge spec, which says that a cycle should be claimed if bctrl.pere is not se t. however, dmi does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction. 5.1.4 pcirst# the pcirst# pin is generated under two conditions: ? pltrst# active ? bctrl.sbr (d30:f0:offse t 3eh:bit 6) set to 1 the pcirst# pin is in the resume well. pcir st# should be tied to pci bus agents, but not other agents in the system. functional description 112 intel ? ich8 family datasheet 5.1.5 peer cycles the pci bridge may be the initiator of peer cycles. peer cycles include memory, io, and configuration cycle types. peer cycles are only allowed through vc0, and are enabled with the following bits: ? bpc.pde (d30:f0:offset 4ch:bit 2) ? memory and i/o cycles ? bpc.cde (d30:f0:offset 4ch:bit 1) ? configuration cycles when enabled for peer for one of the above cycle types, the pci bridge will perform a peer decode to see if a peer agent can receive the cycle. when not enabled, memory cycles (posted and/or non-posted) are sent to dmi, and i/o and/or configuration cycles are not claimed. configuration cycles have special considerations. under the pci local bus specification , these cycles are not allowed to be forwarded upstream through a bridge. however, to enable things such as manage ability, bpc.cde can be set. wh en set, type 1 cycles are allowed into the part. the address format of the type 1 cycle is slightly different from a standard pci configuration cycle to allow addr essing of extended pci space. the format is as follows: note: the ich8?s ide (mobile only) and usb contro llers cannot perform peer-to-peer traffic. 5.1.6 pci-to-pci bridge model from a software perspective, the ich8 contains a pci-to-pci bridge. this bridge connects dmi to the pci bus. by using the pci-to-p ci bridge software model, the ich8 can have its decode ranges programmed by existing plug-and-play software such that pci ranges do not conflict with graphics aperture ranges in the host controller. 5.1.7 idsel to device number mapping when addressing devices on the external pci bus (with the pci slots), the ich8 asserts one address signal as an idsel. when a ccessing device 0, the ich8 asserts ad16. when accessing device 1, the ich8 assert s ad17. this mapping continues all the way up to device 15 where the ich8 asserts ad31 . note that the ich8?s internal functions (intel high definition audio, ide (mobile only), usb, sata and pci bridge) are enumerated like they are off of a separate pci bus (dmi) from the external pci bus. table 39. type 1 address format bits definition 31:27 reserved (same as the pci local bus specification ) 26:24 extended configuration address ? allows addressing of up to 4k. these bits are combined with bits 7:2 to get the full register. 23:16 bus number (same as the pci local bus specification ) 15:11 device number (same as the pci local bus specification ) 10:8 function number (same as the pci local bus specification ) 7:2 register (same as the pci local bus specification ) 1 0 0 must be 1 to indicate a type 1 cy cle. type 0 cycles are not decoded. intel ? ich8 family datasheet 113 functional description 5.1.8 standard pci bus configuration mechanism the pci bus defines a slot based ?configuration space? that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. the pci local bus specification, revision 2.3 defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechan ism implemented within the ich8. the pci local bus specification, revision 2.3 defines two mechanisms to access configuration space, mechanism 1 and mechanism 2. the ich8 only supports mechanism 1. warning: configuration writes to internal devices, wh en the devices are disabled, are invalid and may cause undefined results. 5.2 pci express* root ports (d28:f0,f1,f2,f3,f4,f5) there are six root ports available in ich8. these all reside in device 28, and take function 0 ? 5. port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is function 3, port 5 is function 4, and port 6 is function 5. 5.2.1 interrupt generation the root port generates interrupts on behalf of hot-plug and power management events, when enabled. these interrupts can ei ther be pin based, or can be msis, when enabled. when an interrupt is generated via the legacy pin, the pin is internally routed to the ich8 interrupt controllers. the pin that is driven is based upon the setting of the chipset configuration registers. specifically, the chipset conf iguration registers used are the d28ip (base address + 310ch) and d28ir (base address + 3146h) registers. table 40 summarizes interrupt behavior for msi and wire-modes. in the table ?bits? refers to the hot-plug and pme interrupt bits. table 40. msi vs. pci irq actions interrupt register wire-mode action msi action all bits 0 wire inactive no action one or more bits set to 1 wire active send message one or more bits set to 1, new bit gets set to 1 wire active send message one or more bits set to 1, software clears some (but not all) bits wire active send message one or more bits set to 1, software clears all bits wire inactive no action software clears one or more bits, and one or more bits are set on the same clock wire active send message functional description 114 intel ? ich8 family datasheet 5.2.2 power management 5.2.2.1 s3/s4/s5 support software initiates the transition to s3/s4/s5 by performing an io write to the power management control register in the ich8. after the io write completion has been returned to the processor, each root port will send a pme_turn_off tlp (transaction layer packet) message on its downstream link. the device attached to the link will eventually respond with a pme_to_ack tlp message followed by sending a pm_enter_l23 dllp (data link layer packet) request to enter the l2/l3 ready state. when all of the ich8 root ports links are in the l2/l3 ready state, the ich8 power management control logic will proceed with the entry into s3/s4/s5. prior to entering s3, software is re quired to put each device into d3 hot . when a device is put into d3 hot it will initiate entry into a l1 link state by sending a pm_enter_l1 dllp. thus under normal operating cond itions when the root ports sends the pme_turn_off message the link will be in st ate l1. however, when the root port is instructed to send the pme_turn_off message , it will send it whether or not the link was in l1. endpoints attached to the ich8 can make no assumptions about the state of the link prior to receiving a pme_turn_off message. 5.2.2.2 resuming from suspended state the root port contains enough circuitry in the resume well to detect a wake event through the wake# signal and to wake the system. when wake# is detected asserted, an internal signal is sent to the power management controller of the ich8 to cause the system to wake up. this internal message is not logged in any register, nor is an interrupt/gpe generated due to it. 5.2.2.3 device initia ted pm_pme message when the system has returned to a working state from a previous low power state, a device requesting service will send a pm_p me message continuously, until acknowledge by the root port. the root port will take di fferent actions depending upon whether this is the first pm_pme has been received, or whether a previous message has been received but not yet serviced by the operating system. if this is the first message received (rsts.ps - d28:f0/f1/f2/f3/f4/f5:offset 60h:bit 16 is cleared), the root port will set rsts.ps, and log the pme requester id into rsts.rid (d28:f0/f1/f2/f3/f4/f5:offset 60h:bits 15:0). if an interrupt is enabled via rctl.pie (d28:f0/f1/f2/f3/f4/f5:offset 5ch: bit 3), an interrupt will be generated. this interrupt can be either a pin or an msi if msi is enabled via mc.msie (d28:f0/f1/ f2/f3/f4/f5:offset 82h:bit 0). see section 5.2.2.4 for smi/sci generation. if this is a subsequent message received (rsts.ps is already set), the root port will set rsts.pp (d28:f0/f1/f2/f3/f4/f5:offset 60h:bit 17) and log the pme requester id from the message in a hidden register. no other action will be taken. when the first pme event is cleared by softwa re clearing rsts.ps, the root port will set rsts.ps, clear rsts.pp, and move the requ ester id from the hidden register into rsts.rid. if rctl.pie is set, generate an interrupt. if rctl.pie is not set, send over to the power management controller so that a gpe can be set. if messages have been logged (rsts.ps is set), and rctl.pie is later written from a 0 to a 1, and interrupt must be generated. this last condition handles the case where the message was received prior to the operating system re-enabling interru pts after resuming from a low power state. intel ? ich8 family datasheet 115 functional description 5.2.2.4 smi/sci generation interrupts for power management events are not supported on legacy operating systems. to support power management on non-pci express aware operating systems, pm events can be routed to generate sci. to generate sci, mpc. pmce must be set. when set, a power management event will cause smscs.pmcs (d28:f0/f1/f2/f3/f4/ f5:offset dch:bit 31) to be set. additionally, bios workarounds for power management can be supported by setting mpc.pmme (d28:f0/f1/f2/f3/f4/f5:offset d8 h:bit 0). when this bit is set, power management events will set smscs.pmms (d28:f0/f1/f2/f3/f4/f5:offset dch:bit 0), and smi # will be generated. this bit will be set regardless of whether interrupts or sci is enabled. the smi# may occur conc urrently with an interrupt or sci. 5.2.3 serr# generation serr# may be generated via two paths ? thro ugh pci mechanisms involving bits in the pci header, or through pci express mechan isms involving bits in the pci express capability structure. 5.2.4 hot-plug each root port implements a hot-plug controller which performs the following: ? messages to turn on / off / blink leds ? presence and attention button detection ? interrupt generation the root port only allows hot-plug with mo dules (e.g., expresscard*). edge-connector based hot-plug is not supported. 5.2.4.1 presence detection when a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root port sets slsts.pds (d28:f0/f1/f2/f3/f4/ f5:offset 5ah:bit 6) and slsts.pdc (d28:f0/f1/f2/f3:offset 6h:bit 3). if slctl.pde (d28:f0/f1/f2/f3f4/f5:offset 58h:bit 3) and slctl.hpe (d28:f0/f1/f2/f3f4/ f5:offset 58h:bit 5) are both set, the root port will also generate an interrupt. when a module is removed (via the physical layer detection), the root port clears slsts.pds and sets slsts.pdc. if slctl.pde and slctl.hpe are both set, the root port will also generate an interrupt. figure 6. generation of serr# to platform psts.sse serr# pcicmd.see secondary parity error primary parity error secondary serr# correctable serr# fatal serr# non-fatal serr# pci pci express functional description 116 intel ? ich8 family datasheet 5.2.4.2 message generation when system software writes to slctl.aic (d28:f0/f1/f2/f3f4/f5:offset 58h:bits 7:6) or slctl.pic (d28:f0/f1/f2/f3f4/f5:offset 58h:bits 9:8), the root port will send a message down the link to change the state of leds on the module. writes to these fields are non-postable cycles, and the resulting message is a postable cycle. when receiving one of these writes , the root port performs the following: ? changes the state in the register. ? generates a completion into the upstream queue ? formulates a message for the downstream port if the field is written to regardless of if the field changed. ? generates the message on the downstream port ? when the last message of a command is transmitted, sets slsts.cce (d28:f0/f1/ f2/f3f4/f5:offset 58h:bit 4) to indi cate the command has completed. if slctl.cce and slctl.hpe (d28:f0/f1/f2/f3f4/f5:offset 58h:bit 5) are set, the root port generates an interrupt. the command completed register (slsts.cc) applies only to commands issued by software to control the attention indicator (slctl.aic), power in dicator (slctl.pic), or power controller (slctl.pcc). however, wr ites to other parts of the slot control register would invariably end up writing to the indicators, power controller fields; hence, any write to the slot control register is considered a command and if enabled, will result in a command complete interrupt. the only exception to this rule is a write to disable the command complete interrupt whic h will not result in a command complete interrupt. a single write to the slot control register is considered to be a single command, and hence receives a single command complete, even if the write affects more than one field in the slot control register. 5.2.4.3 attention button detection when an attached device is ejected, an a ttention button could be pressed by the user. this attention button press will result in a the pci express message ?attention_button_pressed? from the device . upon receiving this message, the root port will set slsts.abp (d28:f0/f 1/f2/f3f4/f5:offset 5ah:bit 0). if slctl.abe (d28:f0/f1/f2/f3f4/f5:offset 58h:bit 0) and slctl.hpe (d28:f0/f1/f2/ f3f4/f5:offset 58h:bit 5) are set, the ho t-plug controller will also generate an interrupt. the interrupt is generated on an edge-event. for example, if slsts.abp is already set, a new interrupt will not be generated. intel ? ich8 family datasheet 117 functional description 5.2.4.4 smi/sci generation interrupts for hot-plug events are not supp orted on legacy operating systems. to support hot-plug on non-pci express aware operating systems, hot-plug events can be routed to generate sci. to generate sc i, mpc.hpce (d28:f0/f1/f2/f3f4/f5:offset d8h:bit 30) must be set. when set, enab led hot-plug events will cause smscs.hpcs (d28:f0/f1/f2/f3f4/f5:offset dch:bit 30) to be set. additionally, bios workarounds for hot-plug can be supported by setting mpc.hpme (d28:f0/f1/f2/f3f4/f5:offset d8h:bit 1). when this bit is set, hot-plug events can cause smi status bits in smscs to be se t. supported hot-plug events and their corresponding smscs bit are: ? command completed - scscs.hpccm (d28:f0/f1/f2/f3/f4/f5:offset dch:bit 3) ? presence detect changed - smscs.hppdm (d28:f0/f1/f2/f3/f4/f5:offset dch:bit 1) ? attention button pressed - smscs.hpabm (d28:f0/f1/f2/f3/f4/f5:offset dch:bit 2) ? link active state changed - smscs.hplas (d28:f0/f1/f2/f3/f4/f5:offset dch:bit 4) when any of these bits are set, smi # will be generated. these bits are set regardless of whether interrupts or sci is enabled for hot-plug events. the smi# may occur concurrently with an interrupt or sci. functional description 118 intel ? ich8 family datasheet 5.3 gigabit ethernet controller (b0:d25:f0) the ich8 integrates a gigabit ethernet cont roller. the integrated gbe controller is compatible with intel 10/100 phy (intel? 82562v platform lan connect device) and gbe phy (intel ? 82566 gigabit platform lan connect device). the integrated gbe controller provides two interfaces: lci for 10/100 operation and glci for gbe operation. the glci is shared with the ich8?s pci express port 6 and can be enabled via a soft strap that is stored in system spi flash. the ich8 integrated gbe controller supports multi speed operation, 10/100/1000 mb/s. the integrated gbe can operate in full-duplex at all supported speed or half-duplex at 10/100 mb/s, and adheres with the ieee 802.3x flow control specification . the controller provides a system interface via a pci function. a full memory-mapped or i/o-mapped interface is provided to the so ftware, along with dma mechanisms for high performance data transfer. the following summarizes the ich8 integrated gbe controller features: ? configurable led operation for customization of led display. ? ipv4 and ipv6 checksum offload support (receive, transmit, and large send) ? 64-bit address master support for system using more than 4 gb of physical memory. ? configurable receive and transmit data fifo, programmable in 1 kb increments. ? intelligent interrupt generation to enhance driver performance ? compliance with advanced configuration and power interface and pci power management standards ? acpi register set and power down func tionality supporting d0 & d3 states ? full wake-up support (acpi) ? magic packet wake-up enable with unique mac address ? fragmented udp checksum off load for package reassembly 5.3.1 gbe pci bus interface the gbe controller has a pci interface to the host processor and host memory. the following sections detail the transaction on the bus. 5.3.1.1 transaction layer the upper layer of the host architecture is the transaction layer. the transaction layer connects to the device core using an implem entation specific protocol. through this core-to-transaction-layer protocol, the applicat ion-specific parts of the device interact with the subsystem and transmit and receive requests to or from the remote agent, respectively. 5.3.1.2 data alignment 5.3.1.2.1 4k boundary pci requests must never specify an address/ length combination that causes a memory space access to cross a 4k boundary. it is the hw responsibility to break requests into 4k-aligned requests (if needed). this does not pose any requirement on sw. however, if sw allocates a buffer across a 4k boundary, hw will issue multiple requests for the buffer. sw should consider aligning buffers to 4kb boundary in cases where it improves performance. the alignment to the 4k boundaries is done in the core. the transaction layer will not do any alignment according to these boundaries. intel ? ich8 family datasheet 119 functional description 5.3.1.2.2 64 bytes pci requests are multiples of 64 bytes an d aligned to make better use of memory controller resources. writes, however, can be on any boundary and can cross a 64 byte alignment boundary 5.3.1.3 configuration request retry status the lan controller might have a delay in in itialization due to nvm read. if the nvm configuration read operation is not complete d and the device receives a configuration request, the device will respond with a conf iguration request retry completion status to terminate the request, and thus effectivel y stall the configuration request until such time that the subsystem has completed local initialization and is ready to communicate with the host. 5.3.2 error events and error reporting 5.3.2.1 data parity error the pci host bus does not provide parity prot ection, but it does forward parity errors from bridges. the lan controller recognizes parity errors through the internal bus interface and will set the parity error bit in pc i configuration space. if parity errors are enabled in configuration space, a system erro r will be indicated on the pci host bus to the chipset. the offending cycle with a pari ty error will be dropped and not processed by the lan controller. 5.3.2.2 completion with unsu ccessful completion status a completion with unsuccessful completion st atus (any status other than "000") will be dropped and not processed by the lan cont roller. furthermore, the request that corresponds to the unsuccessful completion will not be retried. when this unsuccessful completion status is received, the system error bit in the pci configuration space will be set. if the system errors are enabled in configuration space, a system error will be indicated on the pci host bus to the chipset. 5.3.3 ethernet interface the integrated lan controller provides a co mplete csma/cd function supporting ieee 802.3 (10mb/s), 802.3u (100mb/s) implementa tions. it also supports the ieee 802.3z and 802.3ab (1000mb/s) implementations. th e device performs all of the functions required for transmission, reception and co llision handling called out in the standards. the mode used to communicate between the lan controller and the lan connect device supports 10/100/1000 mbps operation, with both half- and full-duplex operation at 10/100 mbps, and full-duplex operation at 1000 mbps 5.3.3.1 mac/lan connect interface the integrated lan controller and lan connect device communicate through either the platform lan connect interface (lci) or gbe lan connect interface (glci). all controller configuration is performed using device control registers mapped into system memory or i/o space. the lan connect devi ce is configured via the lci or gbe lan connect interface. the integrated mac supports various modes as summarized in table 41 . functional description 120 intel ? ich8 family datasheet 5.3.4 pci power management the lan controller supports the advanced configuration and power interface (acpi) specification as well as advanced power manage ment (apm). this allows the host to be awoken (i.e. from sx to s0) by network-related activity via an internal host wake signal. the lan controller contains power management registers for pci, and supports d0 and d3 states. pci transactions are only allowed in the d0 state, except for host accesses to the lan controller?s pci configuration registers. 5.3.4.1 wake-up the lan controller supports two types of wakeup mechanisms: 1) advanced power management (apm) wakeup 2) acpi power management wakeup both mechanisms use an internal wake# signal to wake the system up. this signal is connected to the resume wake logic in the ich8. the wake-up steps are as follows: 1) host wake event occurs (note that packet is not delivered to host) 2) pme_status bit is set 3) internal wake# signal asserted by host lan function 4) system wakes from sx state to s0 state 5) the host lan function is transitioned to d0 6) the host clears the pme_status bit 7) internal wake# signal is deasserted by host lan function 5.3.4.1.1 advanced power management wakeup "advanced power management wakeup", or "apm wakeup", was previously known as "wake on lan". it is a feature that has existed in the 10/100 mbps nics for several generations. the basic premise is to receive a broadcast or unicast packet with an explicit data pattern, and then to assert a signal to wake-up the system. in the earlier generations, this was accomplished by using special signal that ran across a cable to a defined connector on the motherboard. the nic would assert the signal for approximately 50ms to signal a wakeup. the lan controller uses (if configured to) an in-band pm_pme message for this. on power-up, the lan controller will read the apm enable bits from the nvm pci init control word into the apm enable (apme) bi ts of the wakeup control register (wuc). these bits control enabling of apm wakeup. when apm wakeup is enabled, the lan controller checks all incoming packets for "magic packets". table 41. lan mode support mode interface active connections legacy 10/100 lci 82562 normal 10/100/1000 lci, glci 82566 intel ? ich8 family datasheet 121 functional description once the lan controller receives a matching magic packet, it will: ? set the magic packet received bit in the wake up status register (wus). ? set the pme_status bit in the power management control / status register (pmcsr) and assert the internal wake# signal. "apm wakeup" is supported in all power stat es and only disabled if a subsequent nvm read results in the apm wake up bit being cleared or the software explicitly writes a 0 to the apm wake up (apm) bit of the wuc register. 5.3.4.1.2 acpi power management wakeup the lan controller supports acpi power management based wakeups. it can generate system wake-up events from three sources: ? reception of a "magic packet". ? reception of a network wakeup packet. ? detection of a link change of state. activating acpi power management wakeup requires the following steps: ? the driver programs the wake up filter control register (wufc) to indicate the packets it wishes to wake up and supplie s the necessary data to the ipv4 address table (ip4at) and the flexible filter mask table (ffmt), flexible filter length table (fflt), and the flexible filter value table (ffvt). it can also set the link status change wake up enable (lnkc) bit in the wake up filter control register (wufc) to cause wakeup when the link changes state. ? the os (at configuration time) writes a 1 to the pme_en bit of the power management control / status register (pmcsr.8). normally, after enabling wakeup, the os will write 11b to the lower two bits of the pmcsr to put the lan controller into low-power mode. once wakeup is enabled, the lan controller monitors incoming packets, first filtering them according to its standard address filter ing method, then filtering them with all of the enabled wakeup filters. if a packet pa sses both the standard address filtering and at least one of the enabled wakeup filters, the lan controller will: ? set the pme_status bit in the power management control / status register (pmcsr) ? if the pme_en bit in the power management control / status register (pmcsr) is set, assert the internal wake# signal. ? set one or more of the "received" bits in the wake up status register (wus). (more than one bit will be set if a packet matches more than one filter.) if enabled, a link state change wakeup will cause similar results, setting pme_status, asserting the internal wake# signal and setti ng the link status changed (lnkc) bit in the wake up status register (wus) when the link goes up or down. the internal wake# signal will remain assert ed until the os either writes a 1 to the pme_status bit of the pmcsr register or writes a 0 to the pme_en bit. after receiving a wakeup packet, the lan co ntroller will ignore any subsequent wakeup packets until the driver clears all of the "recei ved" bits in the wake up status register (wus). it will also ignore link change events until the driver clears the link status changed (lnkc) bit in the wake up status register (wus). functional description 122 intel ? ich8 family datasheet 5.3.5 configurable leds the lan controller supports 3 controllable and configurable leds that are driven from the lan connect device. each of the three le d outputs can be individually configured to select the particular event, state, or ac tivity, which will be indicated on that output. in addition, each led can be individually co nfigured for output polarity as well as for blinking versus non-blinking (steady-state) indication. the configuration for led outputs is specified via the ledctl register. furthermore, the hardware-default configuration for all the le d outputs, can be specified via nvm fields, thereby supporting led displays configurable to a particular oem preference. each of the 3 leds may be configured to use one of a variety of sources for output indication. the mode bits control the led source: ? link_100/1000 is asserted when link is established at either 100 or 1000 mbps. ? link_10/1000 is asserted when link is established at either 10 or 1000 mbps. ? link_up is asserted when any spee d link is established and maintained. ? activity is asserted when link is established and packets are being transmitted or received. ? link/activity is asserted when link is established and there is no transmit or receive activity ? link_10 is asserted when a 10 mbps link is established and maintained. ? link_100 is asserted when a 100 mbps link is established and maintained. ? link_1000 is asserted when a 1000 mbps link is established and maintained. ? full_duplex is asserted when the link is configured for full duplex operation. ? collision is asserted when a collision is observed. ? paused is asserted when the device's transmitter is flow controlled. ? led_on is always asserted; led_off is always de-asserted. the ivrt bits allow the led source to be inverted before being output or observed by the blink-control logic. led outputs are a ssumed to normally be connected to the negative side (cathode) of an external led. the blink bits control whether the led shou ld be blinked while the led source is asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and 83 ms off). the blink control may be especia lly useful for ensuring that certain events, such as activity indication, cause led transitions, which are sufficiently visible to a human eye. the same blinking rate is shared by all leds. 5.3.6 intel ? auto connect battery saver (mobile only) intel ? auto connect battery saver (acbs) is a power saving feature that completely or partially shuts down the intel ? 82566 gigabit platform lan connect (plc) device. this power saving mode, if enabled, is en tered upon link loss due to lan cable disconnection in s0. the plc device will auto matically resume power and reestablish its connection when link pulses from a link partner are detected in s0. the intel ? acbs feature is controlled by the lan driver. the sw driver is responsible for the plc transitioning into intel acbs mode and the ich8m gigabit lan controller hw is responsible for detecting the presence of a link partner which indicates that the intel acbs mode should be terminated. intel ? ich8 family datasheet 123 functional description 5.3.6.1 partial and full power down options intel auto connect battery saver has two power saving implementations: partial or full power down of the plc device. both options require an external discrete energy detection circuit and the use of the ich8m energy_detect signal. partial power down: upon link loss the lan controller sends an in-band message to power down the internal 1.8v and 1.0v voltage regulators of the plc device. full power down: the lan phy power control feature can be used to signal to an external power supply controller or a fet switch to power down all the externally supplied voltage rails of the plc device. 5.3.6.1.1 energy detect energy detection is essential to intel acbs operation. energy detection uses an on- board discrete circuit to indicate a link partner is connected to the lan cable. when in intel acbs mode and a link is reestablished the energy_detect signal will indicate to the ich8m gigabit lan controller (gpio13 inpu t) to exit intel acbs mode and restore power to the plc device using the lan phy power control feature. refer to mobile design guides for further information on the energy detection circuit. 5.3.6.1.2 lan phy power control the lan phy power control function controls the power supplies to the plc device. the lan phy power control function can be rout ed to a power supply controller or fet switch using either the ich8m glan_dock# or spi_cs1# signals configured by the appropriate soft straps described in section 24.2.5. the polarity of the signal associated with the lan phy power control func tion can be configured in the nvm, refer to the intel ? i/o controller hub 8 (ich8) nvm map and programming information application note (ap-496) for details. the lan phy power control feature is required to fully power down the plc device. this feature is also used to restore power to the plc device when the energy_detect signal is asserted and the plc device is in intel acbs mode. a platform designer may choose to implem ent intel acbs without the lan phy power control feature. in such a case, the plc device will only be able to be partially powered down when the internal voltage regulators are used. 5.3.6.2 intel ? acbs signal configurations both partial and full power down implementa tions of intel acbs require the use of gpio13 of the ich8m as the energy_detect signal. there are no additional ich8m configuration requirements for partial power down functionality. for full power down capability two configurat ions are available for implementation of intel acbs: 1. the recommended implementation is to use the glan_dock# signal for lan phy power control functionality. 2. if glan_dock# is a required signal, sp i_cs1# can be configured to support the lan phy power control feature. both configurations are set by the use of ich8m soft straps located in the flash descriptor memory mapped configuration re gisters. see section 24.2.5.1. if both glan_dock# and spi_cs1# are required sign als, only intel acbs with partial power down functionality can be enabled. functional description 124 intel ? ich8 family datasheet 5.4 lpc bridge (w/ system and management functions) (d31:f0) the lpc bridge function of the ich8 resides in pci device 31:function 0. in addition to the lpc bridge function, d31:f0 contains other functional units including dma, interrupt controllers, timers, power management, system management, gpio, and rtc. in this chapter, registers and functi ons associated with other functional units (power management, gpio, usb, ide (mobile only), etc.) are described in their respective sections. 5.4.1 lpc interface the ich8 implements an lpc in terface as described in the low pin count interface specification, revision 1.1. the lpc interfac e to the ich8 is shown in figure 7 . note that the ich8 implements all of the signals that are shown as optional, but peripherals are not required to do so. figure 7. lpc interface diagram intel ? ich8 family datasheet 125 functional description 5.4.1.1 lpc cycle types the ich8 implements all of th e cycle types described in the low pin count interface specification, revision 1.0. table 42 shows the cycle types supported by the ich8. notes: 1. for memory cycles below 16 mb that do not target enabled firmware hub ranges, the ich8 performs standard lpc memory cycles. it only attempts 8-bit transfers. for larger transfers, the ich8 performs multiple 8-bit tr ansfers. if the cycle is not claimed by any peripheral, it is subsequently aborted, and the ich8 return s a value of all 1s to the processor. this is done to maintain compatibility with isa memory cycles where pull-up resistors would keep the bus hi gh if no device responds. 2. bus master read or write cycles must be naturally aligned. for example, a 1-byte transfer can be to any address. however, the 2-byte tr ansfer must be word-ali gned (i.e., with an address where a0=0). a dword transfer must be dword-aligned (i.e ., with an address where a1 and a0 are both 0). 5.4.1.2 start field definition note: all other encodings are reserved. table 42. lpc cycl e types supported cycle type comment i/o read 1 byte only. intel ? ich8 breaks up 16- and 32- bit processor cycles into multiple 8-bit transfers. i/o write 1 byte only. ich8 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. dma read can be 1, or 2 bytes dma write can be 1, or 2 bytes bus master read can be 1, 2, or 4 bytes. (see note 2 below) bus master write can be 1, 2, or 4 bytes. (see note 2 below) table 43. start field bit definitions bits[3:0] encoding definition 0000 start of cycle for a generic target 0010 grant for bus master 0 0011 grant for bus master 1 1111 stop/abort: end of a cycle for a target. functional description 126 intel ? ich8 family datasheet 5.4.1.3 cycle type / di rection (cyctype + dir) the ich8 always drives bit 0 of this field to 0. peripherals running bus master cycles must also drive bit 0 to 0. table 44 shows the valid bit encodings. 5.4.1.4 size bits[3:2] are reserved. the ich8 always drives them to 00. peripherals running bus master cycles are also supposed to drive 00 for bits 3:2; however, the ich8 ignores those bits. bits[1:0] are encoded as listed in table 45 . table 44. cycle type bit definitions bits[3:2] bit1 definition 00 0 i/o read 00 1 i/o write 10 0 dma read 10 1 dma write 11 x reserved. if a peripheral performing a bus master cycle generates this value, the intel ? ich8 aborts the cycle. table 45. transfer size bit definition bits[1:0] size 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) 10 reserved. the intel ? ich8 never drives this combination. if a peripheral running a bus master cycle drives this combination, the ich8 may abort the transfer. 11 32-bit transfer (4 bytes) intel ? ich8 family datasheet 127 functional description 5.4.1.5 sync valid values for the sync field are shown in table 46 . notes: 1. all other combinations are reserved. 2. if the lpc controller receives any sync retu rned from the device other than short (0101), long wait (0110), or ready (0000) when running a fwh cycle, indeterminate results may occur. a fwh device is not allo wed to assert an error sync. 5.4.1.6 sync time-out there are several error cases that can occur on the lpc interface. the ich8 responds as defined in section 4.2.1.9 of the low pin count interface specification , revision 1.1 to the stimuli described therein. there ma y be other peripheral failure conditions; however, these are not handled by the ich8. 5.4.1.7 sync error indication the ich8 responds as defined in section 4.2.1.10 of the low pin count interface specification, revision 1.1. upon recognizing the sync field indicating an error, the ich8 treats this as an serr by reporting this into the device 31 error reporting logic. 5.4.1.8 lframe# usage the ich8 follows the usage of lframe# as defined in the low pin count interface specification, revision 1.1. the ich8 performs an abort for the following cases (possible failure cases): ? ich8 starts a memory, i/o, or dma cycle, but no device drives a valid sync after four consecutive clocks. ? ich8 starts a memory, i/o, or dma cycle, and the peripheral drives an invalid sync pattern. ? a peripheral drives an invalid address when performing bus master cycles. ? a peripheral drives an invalid value. table 46. sync bit definition bits[3:0] indication 0000 ready: sync achieved with no error. for dma transfers, this also indicates dma request deassertion and no more tr ansfers desired for that channel. 0101 short wait: part indicating wait-states. fo r bus master cycles, the intel ? ich8 does not use this encoding. instead, the ich8 uses the long wait encoding (see next encoding below). 0110 long wait: part indicating wait-states, and ma ny wait-states will be added. this encoding driven by the ich8 for bus master cycles, rather than the short wait (0101). 1001 ready more (used only by peripheral for dma cycle): sync achieved with no error and more dma transfers desired to continue after this transfer. this value is valid only on dma transfers and is not allowed for any other type of cycle. 1010 error: sync achieved with error. this is ge nerally used to re place the serr# or iochk# signal on the pci/isa bus. it indica tes that the data is to be transferred, but there is a serious error in this tran sfer. for dma transfers, this not only indicates an error, but also indicate s dma request deasse rtion and no more transfers desired for that channel. functional description 128 intel ? ich8 family datasheet 5.4.1.9 i/o cycles for i/o cycles targeting registers specified in the ich8?s decode ranges, the ich8 performs i/o cycles as defined in the low pin count interface specification, revision 1.1. these are 8-bit transfers. if the processo r attempts a 16-bit or 32-bit transfer, the ich8 breaks the cycle up into multiple 8-bit transfers to consecutive i/o addresses. note: if the cycle is not claimed by any peripheral (and subsequently aborted), the ich8 returns a value of all 1s (ffh) to the processor. this is to maintain compatibility with isa i/o cycles where pull-up resistors would keep the bus high if no device responds. 5.4.1.10 bus master cycles the ich8 supports bus master cycles and requests (using ldrq#) as defined in the low pin count interface specification, revision 1.1. the ich8 has two ldrq# inputs, and thus supports two separate bus master de vices. it uses the associated start fields for bus master 0 (0010b) or bus master 1 (0011b). note: the ich8 does not support lpc bus masters performing i/o cycles. lpc bus masters should only perform memory read or memory write cycles. 5.4.1.11 lpc power management clkrun# protocol (mobile only) the clkrun# protocol is same as the pci local bus specification . stopping the pci clock stops the lpc clock. lpcpd# protocol same timings as for sus_stat#. upon driving sus_stat# low, lpc peripherals drive ldrq# low or tri-state it. ich8 shuts o ff the ldrq# input buffers. after driving sus_stat# active, the ich8 drives lframe # low, and tri-states (or drive low) lad[3:0]. note: the low pin count interface specification, revision 1.1 defines the lpcpd# protocol where there is at least 30 s from lpcpd# assertion to lrst# assertion. this specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. the ich8 asserts both sus_stat# (connects to lpcpd#) and pltrst# (connects to lrst#) at the same time when the core logic is reset (via cf9h, pw rok, or sys_reset#, etc.). this is not inconsistent with the lpc lpcpd# protocol. 5.4.1.12 configuration and intel ? ich8 implications lpc i/f decoders to allow the i/o cycles and memory mapped cycles to go to the lpc interface, the ich8 includes several decoders. during configurat ion, the ich8 must be programmed with the same decode ranges as the peripheral. the decoders are programmed via the device 31:function 0 configuration space. note: the ich8 cannot accept pci write cycles from pci-to-pci bridges or devices with similar characteristics (specifically those with a ?retry read? feature which is enabled) to an lpc device if there is an outstandin g lpc read cycle towards the same pci device or bridge. these cycles are not part of normal system operation, but may be encountered as part of platform validat ion testing using custom test fixtures. intel ? ich8 family datasheet 129 functional description bus master device mapping and start fields bus masters must have a unique start field. in the case of the ich8 that supports two lpc bus masters, it drives 0010 for the start field for grants to bus master #0 (requested via ldrq0#) and 0011 for grants to bus master #1 (requested via ldrq1#.). thus, no registers are needed to configure the start fields for a particular bus master. 5.5 dma operation (d31:f0) the ich8 supports lpc dma us ing the ich8?s dma controller. the dma controller has registers that are fixed in the lower 64 kb of i/o space. the dma controller is configured using registers in the pci configuration space. these registers allow configuration of the channels for use by lpc dma. the dma circuitry incorporates the functi onality of two 82c37 dma controllers with seven independently programmable channels ( figure 8 ). dma controller 1 (dma-1) corresponds to dma channels 0?3 and dma controller 2 (dma-2) corresponds to channels 5?7. dma channel 4 is used to cascade the two controllers and defaults to cascade mode in the dma channel mode (dcm ) register. channel 4 is not available for any other purpose. in addition to accepting requests from dma slaves, the dma controller also responds to requests that so ftware initiates. software may initiate a dma service request by setting any bit in the dma channel request register to a 1. each dma channel is hardwired to the co mpatible settings for dma device size: channels [3:0] are hardwired to 8-bit, count -by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. ich8 provides 24-bit addressing in complianc e with the isa-compatible specification. each channel includes a 16-bit isa-compatible current register which holds the 16 least-significant bits of the 24-bit address, an isa-compatible page register which contains the eight next most significant bits of address. the dma controller also features refresh address generation, and auto-initialization following a dma termination. 5.5.1 channel priority for priority resolution, the dma consists of two logical channel groups: channels 0?3 and channels 4?7. each group may be in either fixed or rotate mode, as determined by the dma command register. dma i/o slaves normally assert their dreq line to arbitrate for dma service. however, a software request for dma service can be presented through each channel's dma request register. a software request is subject to the same prioritization as any hardware request. see the detailed register description for request register programming information in section 9.2 . figure 8. intel ? ich8 dma controller channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 dma-1 dma-2 functional description 130 intel ? ich8 family datasheet 5.5.1.1 fixed priority the initial fixed priority structure is as follows: the fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. in this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. channels [3:0] of dma-1 assume the priority position of channel 4 in dma-2, th us taking priority over channels 5, 6, and 7. 5.5.1.2 rotating priority rotation allows for ?fairness? in priority resolution. the priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0?3, 5?7). channels 0?3 rotate as a group of 4. they are always placed between channel 5 and channel 7 in the priority list. channel 5?7 rotate as part of a group of 4. that is, channels (5?7) form the first three positions in the rotation, while channel group (0?3) comprises the fourth position in the arbitration. 5.5.2 address compatibility mode when the dma is operating, the addresses do not increment or decrement through the high and low page registers. therefore, if a 24-bit address is 01ffffh and increments, the next address is 010000h, not 020000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 02ffffh, not 01ffffh. however, when the dma is operating in 16-bit mode, the addresses st ill do not increment or decrement through the high and low page registers but the page boundary is now 128 k. therefore, if a 24-bit address is 01fffeh and increments, the next address is 000000h, not 0100000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 03fffeh, not 02fffeh. this is compatible with the 82c37 and page register implementation used in the pc-at. this mode is set after cpurst is valid. high priority low priority 0, 1, 2, 3 5, 6, 7 intel ? ich8 family datasheet 131 functional description 5.5.3 summary of dma transfer sizes table 47 lists each of the dma device transfer sizes. the column labeled ?current byte/ word count register? indicates that the regist er contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. the column labeled ?current address increment/decrement? indi cates the number added to or taken from the current address register after each dm a transfer cycle. the dma channel mode register determines if the current ad dress register will be incremented or decremented. 5.5.3.1 address shifting when programm ed for 16-bit i/o count by words the ich8 maintains compatibility with the impl ementation of the dma in the pc at that used the 82c37. the dma shifts the addre sses for transfers to/from a 16-bit device count-by-words. note: the least significant bit of the low page register is dropped in 16-bit shifted mode. when programming the current address regi ster (when the dma channel is in this mode), the current address must be progra mmed to an even address with the address value shifted right by one bit. the address shifting is shown in table 48 . note: the least significant bit of the page register is droppe d in 16-bit shifted mode. 5.5.4 autoinitialize by programming a bit in the dma channel mode register, a channel may be set up as an autoinitialize channel. when a channel undergoes auto initialization, the original values of the current page, current address and current byte/word count registers are automatically restored from the base page, address, and byte/word count registers of that channel following tc. the base registers are loaded simultaneously with the current registers by the microprocessor when the dma channel is programmed and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize. follo wing autoinitialize, the channel is ready to perform another dma service, without processo r intervention, as soon as a valid dreq is detected. table 47. dma transfer size dma device date size and word count current byte/word count register current address increment/ decrement 8-bit i/o, count by bytes bytes 1 16-bit i/o, count by words (address shifted) words 1 table 48. address shifting in 16-bit i/o dma transfers output address 8-bit i/o programmed address (ch 0?3) 16-bit i/o programmed address (ch 5?7) (shifted) a0 a[16:1] a[23:17] a0 a[16:1] a[23:17] 0 a[15:0] a[23:17] functional description 132 intel ? ich8 family datasheet 5.5.5 softwar e commands there are three additional special software commands that the dma controller can execute. the three software commands are: ? clear byte pointer flip-flop ? master clear ? clear mask register they do not depend on any specific bit pattern on the data bus. 5.6 lpc dma dma on lpc is handled through the use of the ldrq# lines from peripherals and special encodings on lad[3:0] from the ho st. single, demand, verify, and increment modes are supported on the lpc interface. channels 0?3 are 8 bit channels. channels 5?7 are 16-bit channels. channel 4 is reserved as a generic bus master request. 5.6.1 asserting dma requests peripherals that need dma service encode their requested channel number on the ldrq# signal. to simplify the protocol, each peripheral on the lpc i/f has its own dedicated ldrq# signal (they may not be sh ared between two separate peripherals). the ich8 has two ldrq# inputs, allowing at least two devices to support dma or bus mastering. ldrq# is synchronous with lclk (pci clock). as shown in figure 9 , the peripheral uses the following serial encoding sequence: ? peripheral starts the sequence by assert ing ldrq# low (start bit). ldrq# is high during idle conditions. ? the next three bits contain the encoded dma channel number (msb first). ? the next bit (act) indicates whether the request for the indicated dma channel is active or inactive. the act bit is 1 (high) to in dicate if it is active and 0 (low) if it is inactive. the case where act is low is rare, and is only used to indicate that a previous request for that channel is being abandoned. ? after the active/inactive indication, the ldrq# signal must go high for at least 1 clock. after that one clock, ldrq# signal can be brought low to the next encoding sequence. if another dma channel also needs to reques t a transfer, another sequence can be sent on ldrq#. for example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channe l 2 is run on the interface, the peripheral can send the encoded request for channel 3. th is allows multiple dma agents behind an i/o device to request use of the lpc interface, and the i/o device does not need to self- arbitrate before sending the message. figure 9. dma request assertion through ldrq# start msb lsb act start lclk ldrq# intel ? ich8 family datasheet 133 functional description 5.6.2 abandoning dma requests dma requests can be deasserted in two fashions: on error conditions by sending an ldrq# message with the ?act? bit set to 0, or normally through a sync field during the dma transfer. this section describes boundary conditions where the dma request needs to be removed prior to a data transfer. there may be some special cases where the peripheral desires to abandon a dma transfer. the most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its fifo, or software stopping a device prematurely. in these cases, the peripheral wishes to stop further dma activity. it may do so by sending an ldrq# message with the act bit as 0. however, since the dma request was seen by the ich8, there is no assurance that the cycle has not been granted and will shortly run on lpc. therefore, peripherals mu st take into account that a dma cycle may still occur. the peripheral can choose not to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle normally with any random data. this method of dma deassertion should be prevented whenever possible, to limit boundary conditions both on the ich8 and the peripheral. 5.6.3 general flow of dma transfers arbitration for dma channels is performed th rough the 8237 within the host. once the host has won arbitration on behalf of a dma channel assigned to lpc, it asserts lframe# on the lpc i/f and begins the dma transfer. the general flow for a basic dma transfer is as follows: 1. ich8 starts transfer by asserting 00 00b on lad[3:0] with lframe# asserted. 2. ich8 asserts ?cycle type? of dma, di rection based on dma transfer direction. 3. ich8 asserts channel number and, if applicable, terminal count. 4. ich8 indicates the size of the transfer: 8 or 16 bits. 5. if a dma read? ? the ich8 drives the first 8 bits of data and turns the bus around. ? the peripheral acknowledges the data with a valid sync. ? if a 16-bit transfer, the process is repeated for the next 8 bits. 6. if a dma write? ? the ich8 turns the bus around and waits for data. ? the peripheral indicates data ready th rough sync and transfers the first byte. ? if a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. the peripheral turns around the bus. 5.6.4 terminal count terminal count is communicated through lad[3] on the same clock that dma channel is communicated on lad[2:0]. this field is th e channel field. terminal count indicates the last byte of transfer, based upon the size of the transfer. for example, on an 8-bit transfer size (size fiel d is 00b), if the tc bit is set, then this is the last byte. on a 16-bit transfer (size fiel d is 01b), if the tc bit is set, then the second byte is the last byte. the peripheral, therefore, must internalize the tc bit when the channel field is communicated, and only signal tc when the last byte of that transfer size has been transferred. functional description 134 intel ? ich8 family datasheet 5.6.5 verify mode verify mode is supported on the lpc interfac e. a verify transfer to the peripheral is similar to a dma write, where the peripheral is transferring data to main memory. the indication from the host is the same as a dma write, so the peripheral will be driving data onto the lpc interface. however, the ho st will not transfer this data into main memory. 5.6.6 dma request deassertion an end of transfer is communicated to the ich8 through a special sync field transmitted by the peripheral. an lpc device must not attempt to signal the end of a transfer by deasserting ldreq#. if a dma tr ansfer is several bytes (e.g., a transfer from a demand mode device) the ich8 ne eds to know when to deassert the dma request based on the data currently being transferred. the dma agent uses a sync encoding on each byte of data being transferred, which indicates to the ich8 whether this is the la st byte of transfer or if more bytes are requested. to indicate the last byte of transfer, the peripheral uses a sync value of 0000b (ready with no error), or 1010b (ready with error). these encodings tell the ich8 that this is the last piece of data transferred on a dma read (ich8 to peripheral ), or the byte that follows is the last piece of data transferred on a dma write (peripheral to ich8). when the ich8 sees one of these two encodi ngs, it ends the dma transfer after this byte and deasserts the dma request to the 823 7. therefore, if the ich8 indicated a 16- bit transfer, the peripheral can end the transfer after one byte by indicating a sync value of 0000b or 1010b. the ich8 does not attempt to transfer the second byte, and deasserts the dma request internally. if the peripheral indicates a 0000b or 1010 b sync pattern on the last byte of the indicated size, then the ich8 only deassert s the dma request to the 8237 since it does not need to end the transfer. if the peripheral wishes to keep the dma request active, then it uses a sync value of 1001b (ready plus more data). this tells the 8237 that more data bytes are requested after the current byte has been transferred, so the ich8 keeps the dma request active to the 8237. therefore, on an 8-bit transfer size, if the peripheral indicates a sync value of 1001b to the ich8, the data w ill be transferred and the dma request will remain active to the 8237. at a later time, the ich8 will then come back with another start?cyctype?channel?size etc. combination to initiate another transfer to the peripheral. the peripheral must not assume that the next start indication from the ich8 is another grant to the peripheral if it had in dicated a sync value of 1001b. on a single mode dma device, the 8237 will re-arbitrate after every transfer. only demand mode dma devices can be assured that they will receive the next start indication from the ich8. note: indicating a 0000b or 1010b encoding on th e sync field of an odd byte of a 16-bit channel (first byte of a 16-bit transfer) is an error condition. note: the host stops the transfer on the lpc bus as indicated, fills the upper byte with random data on dma writes (peripheral to memory), and indicates to the 8237 that the dma transfer occurred, incrementing the 8 237?s address and decrementing its byte count. intel ? ich8 family datasheet 135 functional description 5.6.7 sync field / ldrq# rules since dma transfers on lpc are requested through an ldrq# assertion message, and are ended through a sync field during the dma transfer, the peripheral must obey the following rule when initiating back-t o-back transfers from a dma channel. the peripheral must not assert another message for eight lclks after a deassertion is indicated through the sync field. this is n eeded to allow the 8237, that typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next agent. under default operation, the host only perf orms 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. the method by which this communication be tween host and peripheral through system bios is performed is beyond the scope of th is specification. sinc e the lpc host and lpc peripheral are motherboard devices, no ?plug-n-play? registry is required. the peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the dma cha nnel, and be willing to accept a size field that is smaller than what it may currently have buffered. to that end, it is recommended that future devices that may appear on the lpc bus, that require higher bandwidth than 8-bit or 16-bit dma allow, do so with a bus mastering interface and not rely on the 8237. 5.7 8254 timers (d31:f0) the ich8 contains three counters that have fixed uses. all registers and functions associated with the 8254 timers are in the core well. the 8254 unit is clocked by a 14.31818 mhz clock. counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value 1 counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by tw o each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0. counter 1, refresh request signal this counter provides the refresh request si gnal and is typically programmed for mode 2 operation and only impacts the period of the ref_toggle bit in port 61. the initial count value is loaded one counter period afte r being written to the counter i/o address. the ref_toggle bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. programming the counter to anything other than mode 2 will result in undefined behavior for the ref_toggle bit. counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initia l count value. the speaker must be enabled by a write to port 061h (see nmi status and control ports). functional description 136 intel ? ich8 family datasheet 5.7.1 timer programming the counter/timers are programmed in the following fashion: 1. write a control word to select a counter. 2. write an initial count for that counter. 3. load the least and/or most significant byte s (as required by control word bits 5, 4) of the 16-bit counter. 4. repeat with other counters. only two conventions need to be observed when programming the counters. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). a new initial count may be written to a counter at any time without affecting the counter's programmed mode. counting is affect ed as described in the mode definitions. the new count must follow the programmed count format. if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer contro l between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. the control word register at port 43h controls the operation of all three counters. several commands are available: ? control word command. specifies which counter to read or write, the operating mode, and the count format (binary or bcd). ? counter latch command. latches the current count so that it can be read by the system. the countdown process continues. ? read back command. reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. table 49 lists the six operating modes for the interval counters. intel ? ich8 family datasheet 137 functional description 5.7.2 reading from the interval timer it is often desirable to read the value of a counter without disturbing the count in progress. there are three methods for reading the counters: a simple read operation, counter latch command, and the read-back command. each is explained below. with the simple read and counter latch co mmand methods, the count must be read according to the programmed format; specifica lly, if the counter is programmed for two byte counts, two bytes must be read. the tw o bytes do not have to be read one right after the other. read, write, or programmi ng operations for other counters may be inserted between them. 5.7.2.1 simple read the first method is to perform a simple read operation. the counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). note: performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. however, in the case of counter 2, the count can be stopped by writing to the gate bit in port 61h. 5.7.2.2 counter latch command the counter latch command, written to port 43h, latches the count of a specific counter at the time the command is received. this command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. the count value is then read from each counter?s count register as was programmed by the control register. the count is held in the latch until it is re ad or the counter is reprogrammed. the count is then unlatched. this allows reading the contents of the counters on the fly without affecting counting in progress. multiple co unter latch commands may be used to latch more than one counter. counter latch comma nds do not affect the programmed mode of the counter in any way. table 49. counter operating modes mode function description 0 out signal on end of count (=0) output is 0. when count goes to 0, output goes to 1 and stays at 1 until co unter is reprogrammed. 1 hardware retriggerable one-shot output is 0. when count goes to 0, output goes to 1 for one clock time. 2 rate generator (divide by n counter) output is 1. output goes to 0 for one clock time, then back to 1 and counter is reloaded. 3 square wave output output is 1. output goes to 0 when counter rolls over, and counter is reloaded. output goes to 1 when counter rolls over, and counter is reloaded, etc. 4 software triggered strobe output is 1. output goes to 0 when count expires for one clock time. 5 hardware triggered strobe output is 1. output goes to 0 when count expires for one clock time. functional description 138 intel ? ich8 family datasheet if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ig nored. the count read is the count at the time the first counter latch command was issued. 5.7.2.3 read back command the read back command, written to port 43h, latches the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the value of the counter and its status may then be read by i/o access to the counter address. the read back command may be used to latch multiple counter outputs at one time. this single command is functionally equiva lent to several counter latch commands, one for each counter latched. each counter's la tched count is held until it is read or reprogrammed. once read, a counter is unlat ched. the other counters remain latched until they are read. if multiple count read back commands are issued to the same counter without reading the count, all but the first are ignored. the read back command may additionally be used to latch status information of selected counters. the status of a counter is accessed by a read from that counter's i/ o port address. if multiple counter status latch operations are performed without reading the status, all but the first are ignored. both count and status of the selected counters may be latched simultaneously. this is functionally the same as issuing two consecutive, separate read back commands. if multiple count and/or status read back commands are issued to the same counters without any intervening reads, all but the first are ignored. if both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. the next one or two reads, depending on whether the co unter is programmed for one or two type counts, returns the latched count. subsequent reads return unlatched count. intel ? ich8 family datasheet 139 functional description 5.8 8259 interrupt controllers (pic) (d31:f0) the ich8 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the isa compatible interrupts. these interrupts are: system timer, keyboard controller, serial ports, pa rallel ports, floppy disk, ide (mobile only), mouse, and dma channels. in addition, this interrupt controller can support the pci based interrupts, by mapping the pci interrupt onto the compatible isa interrupt line. each 8259 core supports eight interrupts, numbered 0?7. table 50 shows how the cores are connected. . the ich8 cascades the slave controller onto the master controller through master controller interrupt input 2. this means th ere are only 15 possible interrupts for the ich8 pic. interrupts can individually be programmed to be edge or level, except for irq0, irq2, irq8#, and irq13. note: active-low interrupt sources (e.g., the pirq #s) are inverted inside the ich8. in the following descriptions of the 8259s, the interru pt levels are in reference to the signals at the internal interface of the 8259s, afte r the required inversions have occurred. therefore, the term ?high? indicates ?act ive,? which means ?low? on an originating pirq#. table 50. interrupt controller core connections 8259 8259 input typical interrupt source connected pin / function master 0 internal internal timer / counter 0 output / hpet #0 1 keyboard irq1 via serirq 2 internal slave controller intr output 3 serial port a irq3 via serirq, pirq# 4 serial port b irq4 via serirq, pirq# 5 parallel port / generic irq5 via serirq, pirq# 6 floppy disk irq6 via serirq, pirq# 7 parallel port / generic irq7 via serirq, pirq# 0 internal real time clock internal rtc / hpet #1 1 generic irq9 via serirq, sci, tco, or pirq# 2 generic irq10 via serirq, sci, tco, or pirq# slave 3 generic irq11 via serirq, sci, tco, or pirq# 4 ps/2 mouse irq12 via serirq, sci, tco, or pirq# 5 internal state machine output ba sed on processor ferr# assertion. may optionally be used for sci or tco interrupt if ferr# not needed. 6 sata, ide cable (mobile only) sata primary (legacy mode), or serirq, or pirq#. mobile only: ideirq (legacy mode, non-combined or combined mapped as primary). 7 sata, ide cable (mobile only) sata secondary (legacy mode), or serirq, or pirq#. mobile only: ideirq (legacy mode ? combined, mapped as secondary). functional description 140 intel ? ich8 family datasheet 5.8.1 interrupt handling 5.8.1.1 generating interrupts the pic interrupt sequence involves three bits, from the irr, isr, and imr, for each interrupt level. these bits are used to de termine the interrupt vector returned, and status of any other pending interrupts. table 51 defines the irr, isr, and imr. 5.8.1.2 acknowledging interrupts the processor generates an interrupt acknowle dge cycle that is translated by the host bridge into a pci interrupt acknowledge cy cle to the ich8. the pic translates this command into two internal inta# pulses expe cted by the 8259 cores. the pic uses the first internal inta# pulse to freeze the state of the interrupts for priority resolution. on the second inta# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code. this code is based upon bits [7:3] of the corresponding icw2 register, combined wi th three bits representing the interrupt within that controller. table 51. interrupt status registers bit description irr interrupt request register. this bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. this bit is set whether or not the interrupt is masked. however, a ma sked interrupt will not generate intr. isr interrupt service register. this bit is set, and the co rresponding irr bit cleared, when an interrupt acknowledge cycle is seen, and the vect or returned is for that interrupt. imr interrupt mask register. this bit determines whethe r an interrupt is masked. masked interrupts will not generate intr. table 52. content of interrupt vector byte master, slave interrupt bits [7:3] bits [2:0] irq7,15 icw2[7:3] 111 irq6,14 110 irq5,13 101 irq4,12 100 irq3,11 011 irq2,10 010 irq1,9 001 irq0,8 000 intel ? ich8 family datasheet 141 functional description 5.8.1.3 hardware/softwa re interrupt sequence 1. one or more of the interrupt request lines (irq) are raised high in edge mode, or seen high in level mode, setting the corresponding irr bit. 2. the pic sends intr active to the processor if an asserted interrupt is not masked. 3. the processor acknowledges the intr and responds with an interrupt acknowledge cycle. the cycle is translated into a pc i interrupt acknowledge cycle by the host bridge. this command is broadcast over pci by the ich8. 4. upon observing its own interrupt acknowle dge cycle on pci, the ich8 converts it into the two cycles that the internal 825 9 pair can respond to. each cycle appears as an interrupt acknowledge pulse on the internal inta# pin of the cascaded interrupt controllers. 5. upon receiving the first internally genera ted inta# pulse, the highest priority isr bit is set and the corresponding irr bit is reset. on the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. the slave controller uses these bits to determine if it must respond with an interrupt vector during the second inta# pulse. 6. upon receiving the second internally ge nerated inta# pulse, the pic returns the interrupt vector. if no interrupt request is present because the request was too short in duration, the pic returns vector 7 from the master controller. 7. this completes the interrupt cycle. in aeoi mode the isr bit is reset at the end of the second inta# pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. 5.8.2 initialization command words (icwx) before operation can begin, each 8259 must be initialized. in the ich8, this is a four byte sequence. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each 8259 initialization command word is a fixed location in the i/o memory space: 20h for the master controller, and a0h for the slave controller. 5.8.2.1 icw1 an i/o write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to icw1. upon sensin g this write, the ich8 pic expects three more byte writes to 21h for the master controller, or a1h for the slave controller, to complete the icw sequence. a write to icw1 starts the initializati on sequence during which the following automatically occur: 1. following initialization, an interrupt request (irq) input must make a low-to-high transition to generate an interrupt. 2. the interrupt mask register is cleared. 3. irq7 input is assigned priority 7. 4. the slave mode address is set to 7. 5. special mask mode is cleared and status read is set to irr. functional description 142 intel ? ich8 family datasheet 5.8.2.2 icw2 the second write in the sequence (icw2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. a different base is selected for each interrupt controller. 5.8.2.3 icw3 the third write in the sequence (icw3) has a different meaning for each controller. ? for the master controller, icw3 is used to indicate which irq input line is used to cascade the slave controller. within the ic h8, irq2 is used. therefore, bit 2 of icw3 on the master controller is set to a 1, and the other bits are set to 0s. ? for the slave controller, icw3 is the sl ave identification code used during an interrupt acknowledge cycle. on interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. the slave controller compares this identification code to the value stored in its icw3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 5.8.2.4 icw4 the final write in the sequence (icw4) must be programmed for both controllers. at the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an intel architecture-based system. 5.8.3 operation command words (ocw) these command words reprogram the interru pt controller to operate in various interrupt modes. ? ocw1 masks and unmasks interrupt lines. ? ocw2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the eoi function. ? ocw3 is sets up isr/irr reads, enables/disables the special mask mode (smm), and enables/disables polled interrupt mode. intel ? ich8 family datasheet 143 functional description 5.8.4 modes of operation 5.8.4.1 fully nested mode in this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. when an interrupt is acknow ledged, the highest priority request is determined and its vector placed on the bus. additionally, the isr for the interrupt is set. this isr bit remains set until: the processor issues an eoi command immediately before returning from the service routine; or if in aeoi mode, on the trailing edge of the second inta#. while the isr bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels ge nerate another interrupt. interrupt priorities can be changed in the rotating priority mode. 5.8.4.2 special fully-nested mode this mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. in this case, the special fully-nested mode is programmed to the master controller. this mode is similar to the fully-nested mode with the following exceptions: ? when an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor. in the normal-nested mode, a slave is masked out when its request is in service. ? when exiting the interrupt service routine, software has to check whether the interrupt serviced was the only one from th at slave. this is done by sending a non- specific eoi command to the slave and then reading its isr. if it is 0, a non- specific eoi can also be sent to the master. 5.8.4.3 automatic rotation mode (equal priority devices) in some applications, there are a number of interrupting devices of equal priority. automatic rotation mode provides for a sequential 8-way rotation. in this mode, a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. there are two ways to accomplish automatic rotation using ocw2; the rotation on non-specific eoi command (r=1, sl=0, eoi=1) and the rotate in automatic eoi mode which is set by (r=1, sl=0, eoi=0). 5.8.4.4 specific rotation mode (specific priority) software can change interrupt priorities by programming the bottom priority. for example, if irq5 is programmed as the bottom priority device, then irq6 is the highest priority device. the set priority command is issued in ocw2 to accomplish this, where: r=1, sl=1, and lo?l2 is the binary priority level code of the bottom priority device. in this mode, internal status is updated by software control during ocw2. however, it is independent of the eoi command. priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r=1, sl=1, eoi=1 and lo?l2=irq level to receive bottom priority. functional description 144 intel ? ich8 family datasheet 5.8.4.5 poll mode poll mode can be used to conserve space in the interrupt vector table. multiple interrupts that can be serviced by one inte rrupt service routine do not need separate vectors if the service routine uses the poll command. poll mode can also be used to expand the number of interrupts. the pollin g interrupt service routine can call the appropriate service routine, instead of prov iding the interrupt vectors in the vector table. in this mode, the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, disablin g its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p=1 in ocw3. the pic treats its next i/o read as an interrupt acknowledge, sets the appropriate isr bit if there is a request, and reads the priority level. interrupts are frozen from the ocw3 write to the i/o read. the byte returned during the i/o read contains a 1 in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. 5.8.4.6 cascade mode the pic in the ich8 has one master 825 9 and one slave 8259 cascaded onto the master through irq2. this configuration can handle up to 15 separate priority levels. the master controls the slaves through a thr ee bit internal bus. in the ich8, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. an eoi command must be issued twice: once for the master and once for the slave. 5.8.4.7 edge and level triggered mode in isa systems this mode is programmed using bit 3 in icw1, which sets level or edge for the entire controller. in the ich8, this bi t is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. th is is the edge/level control registers elcr1 and elcr2. if an elcr bit is 0, an interrupt request w ill be recognized by a low-to-high transition on the corresponding irq input. the irq in put can remain high without generating another interrupt. if an elcr bit is 1, an in terrupt request will be recognized by a high level on the corresponding irq input and ther e is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first internal in ta#. if the irq input goes inactive before this time, a default irq7 vector is returned. 5.8.4.8 end of interrupt (eoi) operations an eoi can occur in one of two fashions: by a command word write issued to the pic before returning from a service routine, th e eoi command; or automatically when aeoi bit in icw4 is set to 1. 5.8.4.9 normal end of interrupt in normal eoi, software writes an eoi co mmand before leaving the interrupt service routine to mark the interrupt as complete d. there are two forms of eoi commands: specific and non-specific. when a non-specif ic eoi command is issued, the pic clears the highest isr bit of those that are set to 1. non-specific eoi is the normal mode of operation of the pic within the ich8, as th e interrupt being serviced currently is the interrupt entered with the interrupt acknowle dge. when the pic is operated in modes that preserve the fully nested structure, software can determine which isr bit to clear intel ? ich8 family datasheet 145 functional description by issuing a specific eoi. an isr bit that is masked is not cleared by a non-specific eoi if the pic is in the special mask mode. an eoi command must be issued for both the master and slave controller. 5.8.4.10 automatic end of interrupt mode in this mode, the pic automatically performs a non-specific eoi operation at the trailing edge of the last interrupt acknowle dge pulse. from a system standpoint, this mode should be used only when a nested mu lti-level interrupt structure is not required within a single pic. the aeoi mode can only be used in the master controller and not the slave controller. 5.8.5 masking interrupts 5.8.5.1 masking on an indi vidual interr upt request each interrupt request can be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr masks one interrupt channel. masking irq2 on the master controller masks all requests for service from the slave controller. 5.8.5.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. for example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. the special mask mode enables all interrupts not masked by a bit set in the mask register. normally, when an interrupt servic e routine acknowledges an interrupt without issuing an eoi to clear the isr bit, the interrupt controller inhibits all lower priority requests. in the special mask mode, any interrupts may be selectively enabled by loading the mask register with the appropriate pattern. the special mask mode is set by ocw3 where: ssmm=1, smm=1, and cleared where ssmm=1, smm=0. 5.8.6 steering pci interrupts the ich8 can be programmed to allow pirq a#-pirqh# to be internally routed to interrupts 3?7, 9?12, 14, or 15. the assign ment is programmable through the through the pirqx route control registers, located at 60?63h and 68?6bh in device 31:function 0. one or more pirqx# lines can be routed to the same irqx input. if interrupt steering is not required, the route registers can be programmed to disable steering. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a pci board to share a single line across the connector. when a pirqx# is routed to specified irq line, software must change the irq's corresponding elcr bit to level sensitive mode. the ich8 internally inverts the pirqx# line to send an active high level to the pic. when a pci interrupt is routed on to the pic, the selected irq can no longer be used by an active high device (through serirq). however, active low interrupts can share their interrupt with pci interrupts. internal sources of the pirqs, including sci and tco interrupts, cause the external pirq to be asserted. the ich8 receives the pirq input, like all of the other external sources, and routes it accordingly. functional description 146 intel ? ich8 family datasheet 5.9 advanced programmable interrupt controller (apic) (d31:f0) in addition to the standard isa-compatible pic described in the previous chapter, the ich8 incorporates the apic. while the standa rd interrupt controller is intended for use in a uni-processor system, apic can be used in either a uni-processor or multi- processor system. 5.9.1 interrupt handling the i/o apic handles interrupts very differently than the 8259. briefly, these differences are: ? method of interrupt transmission. the i/o apic transmits interrupts through memory writes on the normal datapath to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. ? interrupt priority. the priority of interrupts in th e i/o apic is independent of the interrupt number. for example, interrupt 10 can be given a higher priority than interrupt 3. ? more interrupts. the i/o apic in the ich8 supports a total of 24 interrupts. ? multiple interrupt controllers. the i/o apic architecture allows for multiple i/o apic devices in the system with their own interrupt vectors. 5.9.2 interrupt mapping the i/o apic within the ich8 supports 24 apic interrupts. each interrupt has its own unique vector assigned by software. the interrupt vectors are mapped as follows, and match ?config 6? of the multi-processor specification . table 53. apic interrupt mapping (sheet 1 of 2) irq # via serirq direct from pin via pci message internal modules 0 no no no cascade from 8259 #1 1 yes no yes 2 no no no 8254 counter 0, hpet #0 (legacy mode) 3 yes no yes 4 yes no yes 5 yes no yes 6 yes no yes 7 yes no yes 8 no no no rtc, hpet #1 (legacy mode) 9 yes no yes option for sci, tco 10 yes no yes option for sci, tco 11 yes no yes hpet #2, option for sci, tco 12 yes no yes 13 no no no ferr# logic 14 yes yes 1 yes mobile only: ideirq (legacy mode, non- combined or combined mapped as primary), sata primary (legacy mode) intel ? ich8 family datasheet 147 functional description notes: 1. mobile only: ideirq can only be driven di rectly from the pin when in legacy ide mode. 2. when programming the polarity of internal interrupt sources on the apic, interrupts 0 through 15 receive active-high internal interrupt sources, while interrupts 16 through 23 receive active-low inte rnal interrupt sources. 3. if irq 11 is used for hpet #2, software should ensure irq 11 is not shared with any other devices to assure the proper operation of hpet #2. ich8 hardware does not prevent sharing of irq 11. 5.9.3 pci / pci express* message-based interrupts when external devices through pci / pci expr ess wish to generate an interrupt, they will send the message defined in the pci express* base specification, revision 1.0a for generating inta# - intd#. these will be transl ated internal assertions/de-assertions of inta# - intd#. 5.9.4 front side bus interrupt delivery for processors that support front side bus (fsb) interrupt delivery, the ich8 requires that the i/o apic deliver interrupt message s to the processor in a parallel manner, rather than using the i/o apic serial scheme. this is done by the ich8 writing (via dmi) to a memory location that is snooped by the processor(s). the processor(s) snoop the cycle to know which interrupt goes active. the following sequence is used: 1. when the ich8 detects an interrupt even t (active edge for edge-triggered mode or a change for level-triggered mode), it sets or resets the internal irr bit associated with that interrupt. 2. internally, the ich8 requests to use the bus in a way that automatically flushes upstream buffers. this can be internally implemented similar to a dma device request. 3. the ich8 then delivers the message by pe rforming a write cycle to the appropriate address with the appropriate data. the address and data formats are described below in section 5.9.4.4 . note: fsb interrupt delivery compatibility with processor clock control depends on the processor, not the ich8. 15 yes yes yes mobile only: ideirq (legacy mode ? combined, mapped as secondary), sata secondary (legacy mode) 16 pirqa# pirqa# yes internal devices are routable; see section 7.1.52 though section 7.1.58 . 17 pirqb# pirqb# 18 pirqc# pirqc# 19 pirqd# pirqd# 20 n/a pirqe# yes option for sci, tco, hpet #0,1,2. other internal devices are routable; see section 7.1.52 through section 7.1.58 . 21 n/a pirqf# 22 n/a pirqg# 23 n/a pirqh# table 53. apic interrupt mapping (sheet 2 of 2) irq # via serirq direct from pin via pci message internal modules functional description 148 intel ? ich8 family datasheet 5.9.4.1 edge-triggered operation in this case, the ?assert message? is sent when there is an inactive-to-active edge on the interrupt. 5.9.4.2 level-triggered operation in this case, the ?assert message? is sent when there is an inactive-to-active edge on the interrupt. if after the eoi the interrupt is still active, then another ?assert message? is sent to indicate that the interrupt is still active. 5.9.4.3 registers associated with front side bus interrupt delivery capabilities indication: the capability to support front side bus interrupt delivery is indicated via acpi configuration techniques. this involves the bios creating a data structure that gets reported to the acpi configuration software. 5.9.4.4 interrupt message format the ich8 writes the message to pci (and to the host controller) as a 32-bit memory write cycle. it uses the formats shown in table 54 and table 55 for the address and data. the local apic (in the processor) has a delivery mode option to interpret front side bus messages as a smi in which case the processor treats the incoming interrupt as a smi instead of as an interrupt. this does not mean that the ich8 has any way to have a smi source from ich8 power management logic cause the i/o apic to send an smi message (there is no way to do this). the ich8?s i/o apic can only send interrupts due to interrupts which do not include smi, nmi or init. this means that in ia32/ia64 based platforms, front side bus interrupt message format delivery modes 010 (smi/pmi), 100 (nmi), and 101 (init) as indicated in this section, must not be used and is not supported. only the hardware pin connection is supported by ich8. : table 54. interrupt message address format bit description 31:20 will always be feeh 19:12 destination id: this is the same as bits 63:56 of the i/o redirection table entry for the interrupt associated with this message. 11:4 extended destination id : this is the same as bits 55:48 of the i/o redirection table entry for the interrupt as sociated with this message. 3 redirection hint: this bit is used by the processor host bridge to allow the interrupt message to be redirected. 0 = the message will be deli vered to the agent (process or) listed in bits 19:12. 1 = the message will be delivered to an agen t with a lower interrupt priority this can be derived from bits 10:8 in the data field (see below). the redirection hint bit will be a 1 if bits 10:8 in the delivery mode field associated with corresponding interrupt are encoded as 001 (lowest priority). otherwise, the redirection hint bit will be 0 2 destination mode: this bit is used only the redirect ion hint bit is set to 1. if the redirection hint bit and the destination mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical id. 1:0 will always be 00. intel ? ich8 family datasheet 149 functional description 5.10 serial interrupt (d31:f0) the ich8 supports a serial irq scheme. this allo ws a single signal to be used to report interrupt requests. the signal used to transm it this information is shared between the host, the ich8, and all peripherals that support serial interrupts. the signal line, serirq, is synchronous to pci clock, and follows the sustained tri-state protocol that is used by all pci signals. this means that if a device has driven serirq low, it will first drive it high synchronous to pci clock and release it the following pci clock. the serial irq protocol defines this sustained tri-state signaling in the following fashion: ? s ? sample phase. signal driven low ? r ? recovery phase. signal driven high ? t ? turn-around phase. signal released the ich8 supports a message for 21 serial interrupts. these represent the 15 isa interrupts (irq0?1, 2?15), the four pci inte rrupts, and the control signals smi# and iochk#. the serial irq protocol does no t support the additional apic interrupts (20?23). note: mobile only: when the ide controller is enabled or the sata controller is configured for legacy ide mode, irq14 and irq15 are expect ed to behave as isa legacy interrupts, which cannot be shared (i.e., through the se rial interrupt pin). if irq14 and irq15 are shared with serial interrupt pin, then abnormal system behavior may occur. for example, irq14/15 may not be detect ed by ich8's interrupt controller. 5.10.1 start frame the serial irq protocol has two modes of operation which affect the start frame. these two modes are: continuous, where the ich8 is solely responsible for generating the start frame; and quiet, where a serial irq peripheral is responsible for beginning the start frame. table 55. interrupt message data format bit description 31:16 will always be 0000h. 15 trigger mode: 1 = level, 0 = edge. same as the corresponding bit in the i/o redirection table for that interrupt. 14 delivery status: 1 = assert, 0 = deassert. only assert messages are sent. this bit is always 1. 13:12 will always be 00 11 destination mode: 1 = logical. 0 = physical. same as the correspondi ng bit in the i/o redirection table for that interrupt. 10:8 delivery mode: this is the same as the correspo nding bits in the i/o redirection table for that interrupt. 000 = fixed 100 = nmi 001 = lowest priority 101 = init 010 = smi/pmi 110 = reserved 011 = reserved 111 = extint 7:0 vector: this is the same as th e corresponding bits in the i/o redirection table for that interrupt. functional description 150 intel ? ich8 family datasheet the mode that must first be entered when enabling the serial irq protocol is continuous mode. in this mode, the ich8 asse rts the start frame. this start frame is 4, 6, or 8 pci clocks wide based upon the serial irq control register, bits 1:0 at 64h in device 31:function 0 configuratio n space. this is a polling mode. when the serial irq stream enters quiet mode (signaled in the stop frame), the serirq line remains inactive and pulled up between the stop and start frame until a peripheral drives the serirq signal low. th e ich8 senses the line low and continues to drive it low for the remainder of the start fr ame. since the first pci clock of the start frame was driven by the peripheral in this mode, the ich8 drives the serirq line low for 1 pci clock less than in continuous mode. this mode of operation allows for a quiet, and therefore lower power, operation. 5.10.2 data frames once the start frame has been initiated, all of the serirq peripherals must start counting frames based on the rising edge of serirq. each of the irq/data frames has exactly 3 phases of 1 clock each: ? sample phase. during this phase, the serirq device drives serirq low if the corresponding interrupt signal is low. if the corresponding interrupt is high, then the serirq devices tri-state the serirq signal. the serirq line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). a low le vel during the irq0?1 and irq2?15 frames indicates that an active-high isa interrupt is not being requested, but a low level during the pci int[a:d], smi#, and iochk# frame indicates that an active-low interrupt is being requested. ? recovery phase. during this phase, the device drives the serirq line high if in the sample phase it was driven low. if it was not driven in the sample phase, it is tri-stated in this phase. ? turn-around phase. the device tri-states the serirq line 5.10.3 stop frame after all data frames, a stop frame is driven by the ich8. the serirq signal is driven low by the ich8 for 2 or 3 pci clocks. the number of clocks is determined by the serirq configuration register. the number of clocks determines the next mode: 5.10.4 specific interrupts not supported via serirq there are three interrupts seen through the se rial stream that are not supported by the ich8. these interrupts are generated intern ally, and are not sharable with other devices within the system. these interrupts are: ? irq0. heartbeat interrupt generated off of the internal 8254 counter 0. ? irq8#. rtc interrupt can only be generated internally. ? irq13. floating point error interrupt gene rated off of the processor assertion of ferr#. table 56. stop frame explanation stop frame width next mode 2 pci clocks quiet mode. any serirq device may initiate a start frame 3 pci clocks continuous mode. only the host (intel ? ich8) may initiate a start frame intel ? ich8 family datasheet 151 functional description the ich8 ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. 5.10.5 data frame format table 57 shows the format of the data frames. for the pci interrupts (a?d), the output from the ich8 is and?d with the pci input signal. this way, the interrupt can be signaled via both the pci interrupt input signal and via the serirq signal (they are shared). table 57. data frame format data frame # interrupt clocks past start frame comment 1 irq0 2 ignored. irq0 can only be generated via the internal 8524 2 irq1 5 3 smi# 8 causes smi# if low. wi ll set the serirq_smi_sts bit. 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 irq8 26 ignored. irq8# can only be generated internally. 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 ignored. irq13 can only be generated from ferr# 15 irq14 44 not attached to pata (mobile only) or sata logic 16 irq15 47 not attached to pata (mobile only) or sata logic 17 iochck# 50 same as isa iochck# going active. 18 pci inta# 53 drive pirqa# 19 pci intb# 56 drive pirqb# 20 pci intc# 59 drive pirqc# 21 pci intd# 62 drive pirqd# functional description 152 intel ? ich8 family datasheet 5.11 real time clock (d31:f0) the real time clock (rtc) module provides a battery backed-up date and time keeping device with two banks of static ram with 128 bytes each, although the first bank has 114 bytes for general purpose usage. three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 s to 500 ms, and end of update cycle notification. seconds, minutes, hours, days, day of week, month, and year are counted. daylight savings compensation is available. the hour is represented in twelve or twenty-four hour format, and data can be represented in bcd or binary format. the design is functiona lly compatible with the motorola ms146818b. the time keeping comes from a 32.768 khz oscillating source, which is divided to achieve an update every second. the lower 14 bytes on the lower ram block has very specific functions. the first ten are for time and date information. the next four (0ah to 0dh) are registers, which configure and report rtc functions. the time and calendar data should match the data mode (bcd or binary) and hour mode (12 or 24 hour) as selected in regist er b. it is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. the exception to these ranges is to store a value of c0?ffh in the alarm bytes to indicate a don?t care situation. all alarm conditions must match to trigger an alarm flag, which co uld trigger an alarm interrupt if enabled. the set bit must be 1 while programming these locations to avoid clashes with an update cycle. access to time and date inform ation is done through the ram locations. if a ram read from the ten time and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. any ram writes under the same conditions are ignored. note: the leap year determination for adding a 29th day to february does not take into account the end-of-the-century exceptions. the logic simply assumes that all years divisible by 4 are leap years. according to the royal observatory greenwich, years that are divisible by 100 are typically not leap year s. in every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. note that the year 2100 will be the first time in which the current rtc implementation would incorrectly calculate the leap-year. the ich8 does not implement month/year alarms. 5.11.1 update cycles an update cycle occurs once a second, if th e set bit of register b is not asserted and the divide chain is properly configured. during this procedure, the stored time and date are incremented, overflow is checked, a ma tching alarm condition is checked, and the time and date are rewritten to the ram locations. the update cycle will start at least 488 s after the uip bit of register a is asserted, and the entire cycle does not take more than 1984 s to complete. the time and date ram locations (0?9) are disconnected from the external bus during this time. to avoid update and data corruption conditions, external ram access to these locations can safely occur at two times. when a upda ted-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date data. if the uip bit of register a is detected to be low, there is at least 488 s before the update cycle begins. warning: the overflow conditions for leap years and daylight savings adjustments are based on more than one date or time item. to ensure proper operation when adjusting the time, the new time and data values should be se t at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. intel ? ich8 family datasheet 153 functional description 5.11.2 interrupts the real-time clock interrupt is internally routed within the ich8 both to the i/o apic and the 8259. it is mapped to interrupt ve ctor 8. this interrupt does not leave the ich8, nor is it shared with any other interrupt. irq8# from the serirq stream is ignored. however, the high performance event timers can also be mapped to irq8#; in this case, the rtc interrupt is blocked. 5.11.3 lockable ram ranges the rtc?s battery-backed ram supports two 8- byte ranges that can be locked via the configuration space. if the locking bits are set, the corresponding range in the ram will not be readable or writable. a write cycle to those locations will have no effect. a read cycle to those locations will not return the location?s actual value (resultant value is undefined). once a range is locked, the range can be unlocked only by a hard reset, which will invoke the bios and allow it to relock the ram range. 5.11.4 century rollover the ich8 detects a rollover when the year byte (rtc i/o space, index offset 09h) transitions form 99 to 00. upon dete cting the rollover, the ich8 sets the newcentury_sts bit (tcobase + 04h, bit 7). if the system is in an s0 state, this causes an smi#. the smi# handler can update registers in the rtc ram that are associated with century value. if the system is in a sleep state (s1?s5) when the century rollover occurs, the ich8 also sets the newcentury_sts bit, but no smi# is generated. when the system resumes from the sleep state, bios should check the newcentury_sts bit and update the century value in the rtc ram. 5.11.5 clearing battery-backed rtc ram clearing cmos ram in an ich8-based plat form can be done by using a jumper on rtcrst# or gpi. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. using rtcrst# to clear cmos a jumper on rtcrst# can be used to clear cmos values, as well as reset to default, the state of those configuration bits that reside in the rtc power well. when the rtcrst# is strapped to ground, the rtc_pw r_sts bit (d31:f0:a4h bit 2) will be set and those configuration bits in the rtc powe r well will be set to their default state. bios can monitor the state of this bit, and manually clear the rtc cmos array once the system is booted. the normal position would cause rtcrst# to be pulled up through a weak pull-up resistor. table 58 shows which bits are set to their default state when rtcrst# is asserted. this rtcrst# jumper technique allows the jumper to be moved and then replaced?all while the system is powered off. then, once booted, the rtc_pwr_sts can be detected in the set state. functional description 154 intel ? ich8 family datasheet table 58. configuration bits reset by rtcrst# assertion (sheet 1 of 2) bit name register location bit(s) default state alarm interrupt enable (aie) register b (general configuration) (rtc_regb) i/o space (rtc index + 0bh) 5 x alarm flag (af) register c (flag register) (rtc_regc) i/o space (rtc index + 0ch) 5 x swsmi_rate_sel general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 7:6 0 slp_s4# minimum assertion width general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 5:4 0 slp_s4# assertion stretch enable general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 3 0 rtc power status (rtc_pwr_sts) general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 2 0 power failure (pwr_flr) general pm configuration 3 register (gen_pmcon_3) d31:f0:a4h 1 0 afterg3_en general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 0 0 power button override status (prbtnor_sts) power management 1 status register (pm1_sts) pmbase + 00h 11 0 rtc event enable (rtc_en) power management 1 enable register (pm1_en) pmbase + 02h 10 0 sleep type (slp_typ) power management 1 control (pm1_cnt) pmbase + 04h 12:10 0 pme_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 11 0 batlow_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 10 0 ri_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 8 0 intel ? ich8 family datasheet 155 functional description using a gpi to clear cmos a jumper on a gpi can also be used to clear cmos values. bios would detect the setting of this gpi on system boot-u p, and manually clear the cmos array. note: the gpi strap technique to clear cmos requires multiple steps to implement. the system is booted with the jumper in ne w position, then powered back down. the jumper is replaced back to the normal posi tion, then the system is rebooted again. warning: clearing cmos, using a jumper on vccrtc, must not be implemented. 5.12 processor interface (d31:f0) the ich8 interfaces to the processor with a variety of signals ? standard outputs to processor: a20m#, smi#, nmi, init#, intr, stpclk#, ignne#, cpuslp#, cpupwrgd ? standard input from processor: ferr# ? intel speedstep ? technology output to processor: cpupwrgood (in mobile configurations) most ich8 outputs to the processor use standard buffers. the ich8 has separate v _cpu_io signals that are pulled up at the syst em level to the processor voltage, and thus determines voh for the outputs to the processor. 5.12.1 processor interface signals this section describes each of the signal s that interface between the ich8 and the processor(s). note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping. 5.12.1.1 a20m# (mask a20) the a20m# signal is active (low) when both of the following conditions are true: ? the alt_a20_gate bit (bit 1 of port92 register) is a 0 ? the a20gate input signal is a 0 the a20gate input signal is expected to be generated by the external microcontroller (kbc). newcentury_sts tco1 status register (tco1_sts) tcobase + 04h 7 0 intruder detect (intrd_det) tco2 status register (tco2_sts) tcobase + 06h 0 0 top swap (ts) backed up control register (buc) chipset configuration registers:offset 3414h 0 x pata reset state (prs) (mobile only) backed up control register (buc) chipset configuration registers:offset 3414h 1 1 table 58. configuration bits reset by rtcrst# assertion (sheet 2 of 2) bit name register location bit(s) default state functional description 156 intel ? ich8 family datasheet 5.12.1.2 init# (initialization) the init# signal is active (driven low) base d on any one of several events described in table 59 . when any of these events occur, init# is driven low for 16 pci clocks, then driven high. note: the 16-clock counter for init# assertion halt s while stpclk# is active. therefore, if init# is supposed to go active while stpclk# is asserted, it actually goes active after stpclk# goes inactive. this section refers to init#, but applies to two signals: init# and init3_3v# (desktop only), as init3_3v# (desktop only) is functionally identical to init#, but signaling at 3.3 v. table 59. init# going active cause of init# going active comment shutdown special cycle from processor observed on ich-gmch interc onnect (from gmch). init# assertion based on value of shutdown policy select register (sps) port92 write, where init_now (bit 0) transitions from a 0 to a 1. portcf9 write, where sys_rst (bit 1) was a 0 and rst_cpu (bit 2) transitions from 0 to 1. rcin# input signal goes low. rcin# is expected to be driven by the external microcontroller (kbc). 0 to 1 transition on rcin# must occur before the intel ? ich8 will arm init# to be generated again. note: rcin# signal is expected to be low during s3, s4, and s5 states. transition on the rcin# signal in those states (or the transition to those states) may not necessarily cause the init# signal to be generated to the processor. cpu bist to enter bist, software sets cpu_bist_en bit and then does a full processor reset using the cf9 register. intel ? ich8 family datasheet 157 functional description 5.12.1.3 ferr#/ignne# (numeric coproc essor error/ ignore numeric error) the ich8 supports the coprocessor error fu nction with the ferr#/ignne# pins. the function is enabled via the coproc_err_en bit (chipset config registers:offset 31ffh:bit 1). ferr# is tied directly to the co processor error signal of the processor. if ferr# is driven active by the processor, irq13 goes active (internally). when it detects a write to the coproc_err register (i/o register f0h), the ich8 negates the internal irq13 and drives ignne# active. ig nne# remains active until ferr# is driven inactive. ignne# is never driven active unless ferr# is active. if coproc_err_en is not set, the assertio n of ferr# will not generate an internal irq13, nor will the write to f0h generate ignne#. 5.12.1.4 nmi (non-maskable interrupt) non-maskable interrupts (nmis) can be genera ted by several sources, as described in table 60 . 5.12.1.5 stop clock request and cpu sleep (stpclk# and cpuslp#) the ich8 power management logic controls these active-low signals. refer to section 5.13 for more information on the functionality of these signals. 5.12.1.6 cpu power good (cpupwrgood) this signal is connected to the processor? s pwrgood input. this signal represents a logical and of the ich8?s pwrok and vrmpwrgd signals. figure 10. coprocessor error timing diagram ferr# internal irq13 i/o write to f0h ignne# table 60. nmi sources cause of nmi comment serr# goes active (either internally, externally via serr# signal, or via message from (g)mch) can instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, tco base + 08h, bit 11). iochk# goes active via serirq# stream (isa system error) can instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, tco base + 08h, bit 11). functional description 158 intel ? ich8 family datasheet 5.12.1.7 deeper sleep (dpslp#) (mobile only) this active-low signal controls the internal gating of the processor?s core clock. this signal asserts before and deasserts after th e stp_cpu# signal to effectively stop the processor?s clock (internally) in the states in which stp_cpu# can be used to stop the processor?s clock externally. 5.12.2 dual-processor is sues (desktop only) 5.12.2.1 signal differences in dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. 5.12.2.2 power management for multiple-processor (or multiple-core) conf igurations in which more than one stop grant cycle may be generated, the (g)mch is expected to count stop grant cycles and only pass the last one through to the ich8. th is prevents the ich8 from getting out of sync with the processor on multiple stpclk# assertions. because the s1 state will have the stpclk# signal active, the stpclk# signal can be connected to both processors. however, fo r acpi implementations, the bios must indicate that the ich8 only supports the c1 state for dual-processor designs. in going to the s1 state for desktop, multiple stop-grant cycles will be generated by the processors. the intel ich8 also has the op tion to assert the processor?s slp# signal (cpuslp#). it is assumed that prior to setting the slp_en bit (which causes the transition to the s1 state), the processors will not be executing code that is likely to delay the stop-grant cycles. in going to the s3, s4, or s5 states, the system will appear to pass through the s1 state; thus, stpclk# and slp# are also used . during the s3, s4, and s5 states, both processors will lose power. upon exit from those states, the processors will have their power restored. table 61. dp signal differences signal difference a20m# / a20gate generally not used, but still supported by intel ? ich8. stpclk# used for s1 state as well as preparation for entry to s3?s5 also allows for therm# based throttling (not via acpi control methods). should be connected to both processors. ferr# / ignne# generally not used , but still supported by ich8. intel ? ich8 family datasheet 159 functional description 5.13 power management (d31:f0) 5.13.1 features ? support for advanced configuration and powe r interface, version 2.0 (acpi) providing power and thermal management ? acpi 24-bit timer ? software initiated throttling of processor performance for thermal and power reduction ? hardware override to throttle processor performance if system too hot ? sci and smi# generation ? pci pme# signal for wake up from low-power states ? system clock control ? (mobile only) acpi c2 state: stop grant (using stpclk# signal) halts processor?s instruction stream ? (mobile only) acpi c3 state: ability to halt processor clock (but not memory clock) ? (mobile only) acpi c4 state: ability to lower processor voltage. ? (mobile only) clkrun# protocol for pci clock starting/stopping ? system sleep state control ? acpi s1 state: stop grant (using stpc lk# signal) halts processor?s instruction stream (only stpclk# active, and cpuslp# optional) ? acpi s3 state ? suspend to ram (str) ? acpi s4 state ? suspend-to-disk (std) ? acpi g2/s5 state ? soft off (soff) ? power failure detection and recovery ? manageability engine power management support ? new wake events from the me (enabled from all s-states including catastrophic s5 conditions) ? streamlined legacy power management for apm-based systems functional description 160 intel ? ich8 family datasheet 5.13.2 intel ? ich8 and system power states table 62 shows the power states defined for ic h8-based platforms. the state names generally match the corresponding acpi states. table 63 shows the transitions rules among the various states. note that transitions among the various states may appear to te mporarily transition through intermediate states. for example, in going from s0 to s1, it may appear to pass through the g0/s0/ c2 states. these intermediate transitions and states are not listed in the table. table 62. general power states for systems using intel ? ich8 state/ substates legacy name / description g0/s0/c0 full on: processor operating. individual de vices may be shut down to save power. the different processor operating levels are defined by cx states, as shown in table 63 . within the c0 state, the intel ? ich8 can throttle the processor using the stpclk# signal to re duce power consumptio n. the throttling can be initiated by software or by the operating system or bios. g0/s0/c1 auto-halt: processor has executed an autohalt instruction and is not executing code. the processor snoops the bus and maintains cache coherency. g0/s0/c2 (mobile only) stop-grant: the stpclk# signal goes active to the processor. the processor performs a stop-grant cycle, halts its in struction stream, an d remains in that state until the stpclk# signal goes inactive. in the stop-grant state, the processor snoops the bus and maintains cache coherency. g0/s0/c3 (mobile only) stop-clock: the stpclk# signal goes active to the processor. the processor performs a stop-grant cycle, halts its instruction stream. ich8 then asserts dpslp# followed by stp_cpu#, which fo rces the clock generator to stop the processor clock. this is al so used for intel speedstep ? technology support. accesses to memory (by graphics, pci, or internal units) is not permitted while in a c3 state. g0/s0/c4 (mobile only) stop-clock with lower processor voltage: this closely resembles the g0/ s0/c3 state. however, after the ich8 has asserted stp_cpu#, it then lowers the voltage to the processor. this reduces the leakage on the processor. prior to exiting the c4 state, the ich8 increases the voltage to the processor. g1/s1 stop-grant: similar to g0/s0/c2 state. ich8 also has the option to assert the cpuslp# signal to further redu ce processor power consumption. note: the behavior for this state is slig htly different when supporting ia64 processors. g1/s3 suspend-to-ram (str): the system context is maintained in system dram, but power is shut off to non-critical ci rcuits. memory is re tained, and refreshes continue. all clocks stop except rtc clock. g1/s4 suspend-to-disk (std): the context of the system is maintained on the disk. all power is then shut off to the system except for th e logic required to resume. g2/s5 soft off (soff): system context is not maintained. all power is shut off except for the logic required to restart. a full boot is required when waking. g3 mechanical off (moff): system context not maintained. all power is shut off except for the rtc. no ?wake? events are possible, because the system does not have any power. this state occurs if the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the ?waking? logic. when system power returns, tran sition will depends on the state just prior to the entry to g3 and the afterg3 bit in the gen_pmcon3 register (d31:f0, offset a4). refer to table 70 for more details. intel ? ich8 family datasheet 161 functional description notes: 1. some wake events can be pr eserved through power failure. 2. transitions from the s1?s5 or g3 states to the s0 state are defe rred until batlow# is inactive in mobile configurations. table 63. state transition rules for intel ? ich8 present state transition trigger next state g0/s0/c0 ? processor halt instruction ? level 2 read (mobile only) ? level 3 read (mobile only) level 4 read (mobile only) ? slp_en bit set ? power button override ? mechanical off/power failure ? g0/s0/c1 ? g0/s0/c2 ? g0/s0/c2, g0/s0/c3 or g0/s0/c4 - depending on c4onc3_en bit (d31:f0:offset a0h:bit 7) and bm_sts_zero_en bit (d31:f0:offset a9h:bit 2) (mobile only) ? g1/sx or g2/s5 state ? g2/s5 ? g3 g0/s0/c1 ? any enabled break event ? stpclk# goes active ? power button override ? power failure ? g0/s0/c0 ? g0/s0/c2 ? g2/s5 ? g3 g0/s0/c2 (mobile only) ? any enabled break event ? power button override ? power failure ? previously in c3/c4 and bus masters idle ? g0/s0/c0 ? g2/s5 ? g3 ? c3 or c4 - depending on pdme bit (d31:f0: offset a9h: bit 4) g0/s0/c3 (mobile only) ? any enabled break event ? any bus master event ? power button override ? power failure ? previously in c4 and bus masters idle ? g0/s0/c0 ? g0/s0/c2 - if pume bit (d31:f0: offset a9h: bit 3) is set, else g0/s0/c0 ? g2/s5 ? g3 ? c4 - depending on pdme bit (d31:f0: offset a9h: bit 4 g0/s0/c4 (mobile only) ? any enabled break event ? any bus master event ? power button override ? power failure ? g0/s0/c0 ? g0/s0/c2 - if pume bit (d31:f0: offset a9h: bit 3) is set, else g0/s0/c0 ? g2/s5 ? g3 g1/s1, g1/s3, or g1/s4 ? any enabled wake event ? power button override ? power failure ? g0/s0/c0 (see note 2) ? g2/s5 ? g3 g2/s5 ? any enabled wake event ? power failure ? g0/s0/c0 (see note 2) ? g3 g3 ? power returns ? optional to go to s0/c0 (reboot) or g2/s5 (stay off until power button pressed or other wake event). (see note 1 and 2) functional description 162 intel ? ich8 family datasheet 5.13.3 system power planes the system has several independent power planes, as described in table 64 . note that when a particular power plane is shut off, it should go to a 0 v level. s 5.13.4 smi#/sci generation on any smi# event taking place, ich8 assert s smi# to the processor, which causes it to enter smm space. smi# remains active unt il the eos bit is set. when the eos bit is set, smi# goes inactive for a minimum of 4 pciclk. if another smi event occurs, smi# is driven active again. the sci is a level-mode interrupt that is ty pically handled by an acpi-aware operating system. in non-apic systems (which is the de fault), the sci irq is routed to one of the 8259 interrupts (irq 9, 10, or 11). the 8259 interrupt controller must be programmed to level mode for that interrupt. in systems using the apic, the sci can be rout ed to interrupts 9, 10, 11, 20, 21, 22, or 23. the interrupt polarity changes depending on whether it is on an interrupt shareable with a pirq or not (see section 9.1.3 ). the interrupt remains asserted until all sci sources are removed. table 65 shows which events can cause an smi# and sci. note that some events can be programmed to cause either an smi# or sci. the usage of the event for sci (instead of smi#) is typically associated wi th an acpi-based system. each smi# or sci source has a corresponding enable and status bit. table 64. system power plane plane controlled by description cpu slp_s3# signal the slp_s3# signal can be used to cut the power to the processor completely. the dprslpvr support allows lowering the processor?s voltage during the c4 state. main slp_s3# signal when slp_s3# goes active, power can be shut off to any circuit not required to wake the system from the s3 state. since the s3 state requires that the memory co ntext be preserved, power must be retained to the main memory. the processor, devices on the pci bus, lpc i/f, and graphics will typically be shut off when the ma in power plane is shut, although there may be small subsections powered. memory slp_s4# signal slp_s5# signal when the slp_s4# goes active, power can be shut off to any circuit not required to wake the system from the s4. since the memory context does not need to be preserved in the s4 state, the power to the memory can also be shut down. when slp_s5# goes active, power can be shut to any circuit not required to wake the system from the s5 state. since the memory context does not need to be preserved in the s5 state, the power to the memory can also be shut. link controller slp_m# this pin is asserted when the mana geability platform goes to moff. depending on the platfo rm, this pin may be used to control the (g)mch, ich8 controller link powe r planes, the clock chip power, and the spi flash power. device[n] gpio individual subsystems may have their own power plane. for example, gpio signals may be used to control the power to disk drives, audio amplifiers, or the display screen. intel ? ich8 family datasheet 163 functional description table 65. causes of smi# and sci (sheet 1 of 2) cause sci smi additional enables where reported pme# yes yes pme_en=1 pme_sts pme_b0 (internal ehci controller) yes yes pme_b0_en=1 pme_b0_sts pci express* pme messages yes yes pci_exp_en=1 (not enabled for smi) pci_exp_sts pci express hot plug message yes yes hot_plug_en=1 (not enabled for smi) hot_plug_sts power button press yes yes pwrbtn_en=1 pwrbtn_sts power button override (note 7) yes no none prbtnor_sts rtc alarm yes yes rtc_en=1 rtc_sts ring indicate yes yes ri_en=1 ri_sts usb#1 wakes yes yes usb1_en=1 usb1_sts usb#2 wakes yes yes usb2_en=1 usb2_sts usb#3 wakes yes yes usb3_en=1 usb3_sts usb#4 wakes yes yes usb4_en=1 usb4_sts usb#5 wakes yes yes usb5_en=1 usb5_sts thrm# pin active yes yes thrm_en=1 thrm_sts acpi timer overflow (2.34 sec.) yes yes tmrof_en=1 tmrof_sts any gpi yes yes gpi[x]_route=10 (sci) gpi[x]_route=01 (smi) gpe0[x]_en=1 gpi[x]_sts gpe0_sts tco sci logic yes no tcosci_en=1 tcosci_sts tco sci message from (g)mch yes no none mchsci_sts tco smi logic no yes tco_en=1 tco_sts tco smi ? year 2000 rollover no yes none newcentury_sts tco smi ? tco timerout no yes none timeout tco smi ? os writes to tco_dat_in register no yes none os_tco_smi tco smi ? message from (g)mch no yes none mchsmi_sts tco smi ? nmi occurred (and nmis mapped to smi) no yes nmi2smi_en=1 nmi2smi_sts tco smi ? intruder# signal goes active no yes intrd_sel=10 intrd_det tco smi ? change of the bioswp bit from 0 to 1 no yes bld=1 bioswr_sts functional description 164 intel ? ich8 family datasheet notes: 1. sci_en must be 1 to enable sci. sci_en must be 0 to enable smi. 2. sci can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in apic mode). 3. gbl_smi_en must be 1 to enable smi. 4. eos must be written to 1 to re-enable smi for the next 1. 5. ich8 must have smi# fully enabled when ich8 is also enabled to trap cycles. if smi# is not enabled in conjunction with the trap enab ling, then hardware behavior is undefined. 6. only gpi[15:0] may generate an smi# or sci. 7. when a power button override first occurs, the system will transition immediately to s5. the sci will only occur after the next wake to s0 if the residual status bit (prbtnor_sts) is not cleared prior to setting sci_en. tco smi ? write attempted to bios no yes bioswp=1 bioswr_sts bios_rls written to yes no gbl_en=1 gbl_sts gbl_rls written to no yes bios_en=1 bios_sts write to b2h register no yes apmc_en = 1 apm_sts periodic timer expires no yes periodic_en=1 periodic_sts 64 ms timer expires no yes sw smi_tmr_en=1 swsmi_tmr_sts enhanced usb legacy support event no yes legacy_usb2_en = 1 legacy_usb2_sts enhanced usb intel specific event no yes intel_usb2_en = 1 intel_usb2_sts uhci usb legacy logic no yes legacy_usb_en=1 legacy_usb_sts serial irq smi reported no yes none serirq_smi_sts device monitors match address in its range no yes none devmon_sts, devact_sts smbus host controller no yes smb_smi_en host controller enabled smbus host status reg. smbus slave smi message no yes none smbus_smi_sts smbus smbalert# signal active no yes none smbus_smi_sts smbus host notify message received no yes host_notify_intre n smbus_smi_sts host_notify_sts (mobile only) batlow# assertion yes yes batlow_en=1. batlow_sts access microcontroller 62h/ 66h no yes mcsmi_en mcsmi_sts slp_en bit written to 1 no yes sm i_on_slp_en=1 smi_on_slp_en_sts usb per-port registers write enable bit changes to 1. no yes usb2_en=1, write_enable_smi_en able=1 usb2_sts, write enable status table 65. causes of smi# and sci (sheet 2 of 2) cause sci smi additional enables where reported intel ? ich8 family datasheet 165 functional description 5.13.4.1 pci express* sci pci express ports and the (g)mch (via dmi) have the ability to cause pme using messages. when a pme message is received, ich8 will set the pci_exp_sts bit. if the pci_exp_en bit is also set, the ich8 can cause an sci via the gpe1_sts register. 5.13.4.2 pci express* hot-plug pci express has a hot-plug mechanism and is capable of generating a sci via the gpe1 register. it is also capable of generating an smi. however, it is not capable of generating a wake event. 5.13.5 dynamic processor clock control the ich8 has extensive control for dynamically starting and stopping system clocks. the clock control is used for transitions am ong the various s0/cx states, and processor throttling. each dynamic clock control method is described in this section. the various sleep states may also perform types of non-dynamic clock control. the ich8 supports the acpi c0 and c1 states (in desktop) or c0, c1, c2, c3, and c4 (in mobile) states. the dynamic processor clock control is handled using the following signals: ? stpclk#: used to halt processor instruction stream. ? (mobile only) stp_cpu#: used to stop processor?s clock ? (mobile only) cpuslp#: asserted prior to stp_cpu# (in stop grant mode) ? (mobile only) dpslp#: used to force deeper sleep for processor. ? (mobile only) dprslpvr: used to lower voltage of vrm during c4 state. ? (mobile only) dprstp#: used to alert the processor of c4 state. also works in conjunction with dprslpvr to communicate to the vrm whether a slow or fast voltage ramp should be used. the c1 state is entered based on the processor performing an auto halt instruction. (mobile only) the c2 state is entered ba sed on the processor reading the level 2 register in the ich8. it can also be entered from c3 or c4 states if bus masters require snoops and the pume bit (d31:f0: offset a9h: bit 3) is set. (mobile only) the c3 state is entered ba sed on the processor reading the level 3 register in the ich8 and when the c4onc3_e n bit is clear (d31:f0:offset a0:bit 7). this state can also be entered after a tempor ary return to c2 from a prior c3 or c4 state. (mobile only) the c4 state is entered ba sed on the processor reading the level 4 register in the ich8, or by reading the leve l 3 register when the c4onc3_en bit is set. this state can also be entered after a temp orary return to c2 from a prior c4 state. a c1 state in desktop or a c1, c2, c3 or c4 state in mobile ends due to a break event. based on the break event, the ich8 returns the system to c0 state. (mobile only) table 66 lists the possible break events from c2, c3, or c4. the break events from c1 are indicated in the processor?s datasheet. functional description 166 intel ? ich8 family datasheet 5.13.5.1 slow c4 exit (mobile only) to eliminate the audible noise caused by aggressive voltage ramps when exiting c4 states at a regular, periodic frequency, th e ich8 supports a method to slow down the voltage ramp at the processor vr for certain break events. if enabled for this behavior, the ich8 treats irq0 and irq8 as ?slow? break events since both of these can be the system timer tick interrupt. rather than carefully tracking the interrupt and timer configuration information to track the one correct interrupt, it was deemed acceptable to simplify the logic and slow the break exit sequence for both interrupts. other break event sources invoke the normal exit timings. the ich8 indicates that a slow voltage ramp is desired by deasserting dprstp# (high) and leaving dprslpvr asserted (high). the normal voltage ramp rate is communicated by deasserting dprstp# (high) and deasserting dprslpvr (low). the ich8 waits an additional delay before starting the normal voltage ramp timer during the c4 exit sequence. if a ?fast? br eak event occurs during the additional, slow- exit time delay, the ich8 quickly deassert s dprslpvr (low), thereby speeding up the voltage ramp and reducing the delay to a valu e that is typically seen by the device in the past. in the event that a fast break ev ent and a slow break event occur together, the fast flow is taken. the ich8 provides enable for slow c4 ex it as well as a programmable delay time. table 66. break events (mobile only) event breaks from comment any unmasked interrupt goes active c2, c3, c4 irq[0:15] when using the 8259s, irq[0:23] for i/o apic. since sci is an interrupt, any sci will also be a break event. any internal event that cause an nmi or smi# c2, c3, c4 many possible sources any internal event that cause init# to go active c2, c3, c4 could be indicated by th e keyboard controller via the rcin input signal. any bus master request (internal, external or dma, or bmbusy#) goes active and bm_rld=1 (d31:f0:offset pmbase+04h: bit 1) c3, c4 need to wake up processor so it can do snoops note: if the pume bit (d31:f0: offset a9h: bit 3) is set, then bus master activity will not be treated as a break event. instead, there will be a return only to the c2 state. processor pending break event indication c2, c3, c4 only available if ferr# enabled for break event indication (see ferr# mux enable in gcs, chipset config registers:offset 3410h:bit 6) intel ? ich8 family datasheet 167 functional description 5.13.5.2 transition rules among s0/cx and throttling states the following priority rules and assumptions apply among the various s0/cx and throttling states: ? entry to any s0/cx state is mutually exclusive with entry to any s1?s5 state. this is because the processor can only perform one register access at a time and sleep states have higher priority than thermal throttling. ? when the slp_en bit is set (system going to a s1 - s5 sleep state), the thtl_en and force_thtl bits can be internally treated as being disabled (no throttling while going to sleep state). ? (mobile only) if the thtl_en or force_thtl bits are set, and a level 2, level 3, or level 4 read then occurs, the system should immediately go and stay in a c2, c3, or c4 state until a break event occurs. a level 2, level 3, or level 4 read has higher priority than the software initiated throttling. ? (mobile only) after an exit from a c2, c3 or c4 state (due to a break event), and if the thtl_en or force_thtl bits are still se t, the system will continue to throttle stpclk#. depending on the time of break event, the first transition on stpclk# active can be delayed by up to one thrm period (1024 pci clocks = 30.72 s). ? the host controller must post stop-grant cycles in such a way that the processor gets an indication of the end of the special cycle prior to the ich8 observing the stop-grant cycle. this ensures that the stpclk# signals stays active for a sufficient period after the proce ssor observes the response phase. ? (mobile only) if in the c1 state and the stpclk# signal goes active, the processor will generate a stop-grant cycle, and the sy stem should go to the c2 state. when stpclk# goes inactive, it should return to the c1 state. 5.13.5.3 deferred c3 /c4 (mobile only) due to the new dmi protocol, if there is any bu s master activity (other than true isoch), then the c0 to c3 transition will pause at th e c2 state. ich8 will keep the processor in a c2 state until: ? ich8 sees no bus master activity. ? a break event occurs. in this case, the ich8 will perform the c2 to c0 sequence. note that bus master traffic is not a break event in this case. to take advantage of the deferred c3/c4 mode, the bm_sts_zero_en bit must be set. this will cause the bm_sts bit to read as 0 even if some bus master activity is present. if this is not done, then the software may avoid even attempting to go to the c3 or c4 state if it sees the bm_sts bit as 1. if the pume bit (d31:f0: offset a9h: bit 3) is 0, then the ich8 will treat bus master activity as a break event. when reaching the c2 state, if there is any bus master activity, the ich8 will return the processor to a c0 state. 5.13.5.4 popup (auto c3/c 4 to c2) (mobile only) when the pume bit (d31:f0: offset a9h: bi t 3) is set, the ich8 enables a mode of operation where standard (non-isoch) bus master activity will not be treated as a full break event from the c3 or c4 states. instead, these will be treated merely as bus master events and return the platform to a c2 state, and thus allow snoops to be performed. after returning to the c2 state, the bus mast er cycles will be sent to the (g)mch, even if the arb_dis bit is set. functional description 168 intel ? ich8 family datasheet 5.13.5.5 popdown (auto c2 to c3/c4) (mobile only) after returning to the c2 state from c3/c4, it the pdme bit (d31:f0: offset a9h: bit 4) is set, the platform can return to a c3 or c4 state (depending on where it was prior to going back up to c2). this behaves simila r to the deferred c3/c4 transition, and will keep the processor in a c2 state until: ? bus masters are no longer active. ? a break event occurs. note that bus master traffic is not a break event in this case. 5.13.6 dynamic pci clock control (mobile only) the pci clock can be dynamically controlled independent of any other low-power state. this control is accomplished using the clkrun# protocol as described in the pci mobile design guide, and is transparent to software. the dynamic pci clock control is handled using the following signals: ? clkrun#: used by pci and lpc peripherals to request the system pci clock to run ? stp_pci#: used to stop the system pci clock note: the 33 mhz clock to the ich8 is ?free-runni ng? and is not affected by the stp_pci# signal. 5.13.6.1 conditions for checking the pci clock when there is a lack of pci activity, the ic h8 has the capability to stop the pci clocks to conserve power. ?pci activity? is defined as any activity that would require the pci clock to be running. any of the following conditions will indicate that it is not okay to stop the pci clock: ? cycles on pci or lpc ? cycles of any internal device that would need to go on the pci bus ? serirq activity behavioral description ? when there is a lack of activity (as defined above) for 29 pci clocks, the ich8 deasserts (drive high) clkrun# for 1 clock and then tri-states the signal. 5.13.6.2 conditions for ma intaining the pci clock pci masters or lpc devices that wish to ma intain the pci clock running will observe the clkrun# signal deasserted, and then must re-assert if (drive it low) within 3 clocks. ? when the ich8 has tri-stated the clkrun # signal after deasserting it, the ich8 then checks to see if the signal has been re-asserted (externally). ? after observing the clkrun# signal asserted for 1 clock, the ich8 again starts asserting the signal. ? if an internal device needs the pci bus, the ich8 asserts the clkrun# signal. 5.13.6.3 conditions for stopping the pci clock ? if no device re-asserts clkrun# once it has been deasserted for at least 6 clocks, the ich8 stops the pci clock by assert ing the stp_pci# signal to the clock synthesizer. intel ? ich8 family datasheet 169 functional description 5.13.6.4 conditions for re -starting the pci clock ? a peripheral asserts clkrun# to indicate that it needs the pci clock re-started. ? when the ich8 observes the clkrun# signal asserted for 1 (free running) clock, the ich8 deasserts the stp_pci# signal to the clock synthesizer within 4 (free running) clocks. ? observing the clkrun# signal asserted ex ternally for 1 (free running) clock, the ich8 again starts driv ing clkrun# asserted. if an internal source requests the clock to be re-started, the ich8 re-asserts clkrun#, and simultaneously deasserts the stp_pci# signal. 5.13.6.5 lpc devices and clkrun# if an lpc device (of any type) needs the 33 mhz pci clock, such as for lpc dma or lpc serial interrupt, then it can assert clkrun#. note that lpc devices running dma or bus master cycles will not need to assert clkrun#, since the ich8 asserts it on their behalf. the ldrq# inputs are ignored by the ich8 when the pci clock is stopped to the lpc devices in order to avoid misinterpreting th e request. the ich8 assumes that only one more rising pci clock edge occurs at the lpc device after the assertion of stp_pci#. upon deassertion of stp_pci#, the ich8 assumes that the lpc device receives its first clock rising edge corresponding to the ich8 ?s second pci clock rising edge after the deassertion. 5.13.7 sleep states 5.13.7.1 sleep state overview the ich8 directly supports different sleep st ates (s1?s5), which are entered by setting the slp_en bit, or due to a power button press. the entry to the sleep states is based on several assumptions: ? entry to a cx state is mutually exclusive with entry to a sleep state. this is because the processor can only perform one register access at a time. a request to sleep always has higher priority than throttling. ? prior to setting the slp_en bit, the software turns off processor-controlled throttling. note that thermal throttling ca nnot be disabled, but setting the slp_en bit disables thermal throttling (since s1?s5 sleep state has higher priority). ? the g3 state cannot be entered via any software mechanism. the g3 state indicates a complete loss of power. 5.13.7.2 initiating sleep state sleep states (s1?s5) are initiated by: ? masking interrupts, turning off all bus master enable bits, setting the desired type in the slp_typ field, and then setting the slp_en bit. the hardware then attempts to gracefully put the system into the corresponding sleep state. ? pressing the pwrbtn# signal for more than 4 seconds to cause a power button override event. in this case the transiti on to the s5 state is less graceful, since there are no dependencies on observing st op-grant cycles from the processor or on clocks other than the rtc clock ? assertion of the thrmtrip# signal will cause a transition to the s5 state. this can occur when system is in s0 or s1 state. functional description 170 intel ? ich8 family datasheet 5.13.7.3 exiting sleep states sleep states (s1?s5) are exited based on wake events. the wake events forces the system to a full on state (s0), although some non-critical subsystems might still be shut off and have to be brought back manually. for example, the hard disk may be shut off during a sleep state, and have to be en abled via a gpio pin before it can be used. upon exit from the ich8-controlled sleep st ates, the wak_sts bit is set. the possible causes of wake events (and th eir restrictions) are shown in table 68 . note: (mobile only) if the batlow# signal is asserted, ich8 does not attempt to wake from an s1?s5 state, even if the power button is pressed. this prevents the system from waking when the battery power is insufficient to wake the system. wake events that occur while batlow# is asserted are latched by the ich8, and the system wakes after batlow# is deasserted. table 67. sleep types sleep type comment s1 intel ? ich8 asserts the stpclk# si gnal. it also has the op tion to assert cpuslp# signal. this lowers the processor?s power consumption. no snooping is possible in this state. s3 ich8 asserts slp_s3#. the slp_s3# signal controls the power to non-critical circuits. power is only retain ed to devices needed to wake from this sleeping state, as well as to the memory. s4 ich8 asserts slp_s3# and slp_s4#. the slp_s4# signal shuts off the power to the memory subsystem. only devices need ed to wake from this state should be powered. s5 same power state as s4. ich8 asse rts slp_s3#, slp_s4# and slp_s5#. table 68. causes of wake events (sheet 1 of 2) cause states can wake from how enabled rtc alarm s1?s5 (note 1) set rtc_en bit in pm1_en register power button s1?s5 always enabled as wake event gpi[0:15] s1?s5 (note 1) gpe0_en register note: gpi?s that are in the core well are not capable of waking the system from sleep states where the core well is not powered. classic usb s1?s5 set usb1_en, usb 2_en, usb3_en, and usb4_en bits in gpe0_en register lan s1?s5 will use pme#. wake enable set with lan logic. ri# s1?s5 (note 1) set ri_en bit in gpe0_en register intel ? high definition audio s1?s5 event sets pme_b0_sts bit; pm_b0_en must be enabled. can not wake from s5 state if it was entered due to power failure or power button override. primary pme# s1?s5 (note 1) pme_b0_en bit in gpe0_en register secondary pme# s1?s5 set pme_en bit in gpe0_en register. intel ? ich8 family datasheet 171 functional description notes: 1. this is a wake event from s5 only if the sleep state was entered by setting the slp_en and slp_typ bits via software, or if there is a power failure. 2. if in the s5 state due to a power button over ride or thrmtrip#, the possible wake events are due to power button, hard reset wi thout cycling (see command type 3 in table 93 ), and hard reset system (see command type 4 in table 93 ). 3. when the wake# pin is active and the pci ex press device is enabled to wake the system, the ich8 will wake the platform. it is important to understand that the various gpis have different levels of functionality when used as wake events. the gpis that reside in the core power well can only generate wake events from sleep states where the core well is powered. also, only certain gpis are ?acpi compliant,? meaning that their status and enable bits reside in acpi i/o space. table 69 summarizes the use of gpis as wake events. the latency to exit the various sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the ich8 are insignificant. pci_exp_wake# s1?s5 pci_exp_wake bit (note 3) pci_exp pme message s1 must use the pci express* wake# pin rather than messages for wake from s3,s4, or s5. smbalert# s1?s5 always enabled as wake event smbus slave message s1?s5 wake/smi# command always enabled as a wake event. note: smbus slave message can wake the system from s1? s5, as well as from s5 due to power button override. smbus host notify message received s1?s5 host_notify_wken bit smbus slave command register. reported in the smb_wak_sts bi t in the gpeo_sts register. table 68. causes of wake events (sheet 2 of 2) cause states can wake from how enabled table 69. gpi wake events gpi power well wake from notes gpi[7:0] core s1 acpi compliant gpi[15:8] resume s1?s5 acpi compliant functional description 172 intel ? ich8 family datasheet 5.13.7.4 pci express* wake# signal and pme event message pci express ports can wake the platform from any sleep state (s1, s3, s4, or s5) using the wake# pin. wake# is treated as a wake event, but does not cause any bits to go active in the gpe_sts register. pci express ports and the (g)mch (via dm i) have the ability to cause pme using messages. when a pme message is receiv ed, ich8 will set the pci_exp_sts bit. 5.13.7.5 sx-g3-sx, handling power failures depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. the after_g3 bit provides the ability to program whether or not the system should boot once power returns after a power loss event. if the policy is to not boot, the system remains in an s5 state (unless previo usly in s4). there are only three possible events that will wake the system after a power failure. 1. pwrbtn#: pwrbtn# is always enabled as a wake event. when rsmrst# is low (g3 state), the pwrbtn_sts bit is reset. when the ich8 exits g3 after power returns (rsmrst# goes high), the pwrbtn# signal is already high (because v cc - standby goes high before rsmrst# goes high) and the pwrbtn_sts bit is 0. 2. ri#: ri# does not have an internal pull-up. th erefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. if this signal goes low (active), wh en power returns the ri_sts bit is set and the system interprets that as a wake event. 3. rtc alarm: the rtc_en bit is in the rtc well and is preserved after a power loss. like pwrbtn_sts the rtc_sts bit is cleared when rsmrst# goes low. the ich8 monitors both pwrok and rsmrst# to detect for power failures. if pwrok goes low, the pwrok_flr bit is set. if rsmrst# goes low, pwr_flr is set. note: although pme_en is in the rtc well, this signal cannot wake the system after a power loss. pme_en is cleared by rtcrst#, and pme_sts is cleared by rsmrst#. table 70. transitions due to power failure state at power failure afterg3_en bit transition when power returns s0, s1, s3 1 0 s5 s0 s4 1 0 s4 s0 s5 1 0 s5 s0 intel ? ich8 family datasheet 173 functional description 5.13.8 thermal management the ich8 has mechanisms to assist with managing thermal problems in the system. 5.13.8.1 thrm# signal the thrm# signal is used as a status inpu t for a thermal sensor. based on the thrm# signal going active, the ich8 generates an smi# or sci (depending on sci_en). if the thrm_pol bit is set low, when the thrm# signal goes low, the thrm_sts bit will be set. this is an indicator that the thermal threshold has been exceeded. if the thrm_en bit is set, then when thrm_sts go es active, either an smi# or sci will be generated (depending on the sci_en bit being set). the power management software (bios or acpi) can then take measures to start reducing the temperature. examples include shutting off unwanted subsystems, or halting the processor. by setting the thrm_pol bit to high, anothe r smi# or sci can optionally be generated when the thrm# signal goes back high. this allows the software (bios or acpi) to turn off the cooling methods. note: thrm# assertion does not cause a tco event message in s3 or s4. the level of the signal is not reported in the heartbeat message. 5.13.8.2 software initiated passive cooling this mode is initiated by software setting the thtl_en or force_thtl bits. software sets the thtl_dty or thrm_dty bi ts to select throttle ratio and thtl_en or force_thtl bit to enable the throttling. throttling results in stpclk# active for a minimum time of 12.5% and a maximum of 87.5%. the period is 1024 pci clocks. thus, the stpclk# signal can be active for as little as 128 pci clocks or as much as 896 pci clocks. the actual slowdown (and cooling) of the processor depends on the instruction stream, because the processor is allowed to finish the current instruction. furthermore, the ich8 waits for the stop- grant cycle before starting the count of the time the stpclk# signal is active. 5.13.8.3 thrm# override software bit the force_thtl bit allows the bios to forc e passive cooling, independent of the acpi software (which uses the thtl_en and thtl_d ty bits). if this bit is set, the ich8 starts throttling using the ratio in the thrm_dty field. when this bit is cleared the ich8 stops throttling, unless the thtl_en bit is set (indicating that acpi software is attempting throttling). if both the thtl_en and force_thtl bits ar e set, then the ich8 should use the duty cycle defined by the thrm_dty field, not the thtl_dty field. 5.13.8.4 active cooling active cooling involves fans. the gpio signals from the ich8 can be used to turn on/off a fan. functional description 174 intel ? ich8 family datasheet 5.13.9 event input sign als and their usage the ich8 has various input signals that tri gger specific events. this section describes those signals and how they should be used. 5.13.9.1 pwrbtn# (power button) the ich8 pwrbtn# signal operates as a ?f ixed power button? as described in the advanced configuration and power interface, version 2.0b. pwrbtn# signal has a 16 ms de-bounce on the input. the state transition descriptions are included in table 71 . note that the transitions start as soon as the pwrbtn# is pressed (but after the debounce logic), and does not depend on when the power button is released. note: during the time that the slp_s4# signal is stretched for the minimum assertion width (if enabled), the power button is not a wake event. refer to power button override function section below for further detail. power button override function if pwrbtn# is observed active for at least four consecutive seconds, the state machine should unconditionally transition to the g2/s5 state, regardless of present state (s0?s4), even if pwrok is not active. in th is case, the transition to the g2/s5 state should not depend on any particular respon se from the processor (e.g., a stop-grant cycle), nor any similar dependency from any other subsystem. the pwrbtn# status is readable to check if the button is currently being pressed or has been released. the status is taken after the de-bounce, and is readable via the pwrbtn_lvl bit. note: the 4-second pwrbtn# assertion should only be used if a system lock-up has occurred. the 4-second timer starts counting when the ich8 is in a s0 state. if the pwrbtn# signal is asserted and held active when the system is in a suspend state (s1?s5), the assertion causes a wake event. once the system has resumed to the s0 state, the 4-second timer starts. note: during the time that the slp_s4# signal is stretched for the minimum assertion width (if enabled by d31:f0:a4h bit 3), the power button is not a wake event. as a result, it is conceivable that the user will press and continue to hold the power button waiting for the system to awake. since a 4-second press of the power button is already defined as an unconditional power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. once the power-cycle timer has expired, the table 71. transitions due to power button present state event transition/action comment s0/cx pwrbtn# goes low smi# or sci generated (depending on sci_en, pwrbtn_init_en, pwrbtn_en and glb_smi_en) software typically initiates a sleep state s1?s5 pwrbtn# goes low wake event. transitions to s0 state standard wakeup g3 pwrbtn# pressed none no effect since no power not latched nor detected s0?s4 pwrbtn# held low for at least 4 consecutive seconds unconditional transition to s5 state no dependence on processor (e.g., stop-grant cycles) or any other subsystem intel ? ich8 family datasheet 175 functional description power button awakes the system. once the minimum slp_s4# power cycle expires, the power button must be pressed for another 4 to 5 seconds to create the override condition to s5. sleep button the advanced configuration and power interface, version 2.0b defines an optional sleep button. it differs from the power button in that it only is a request to go from s0 to s1?s4 (not s5). also, in an s5 state, the power button can wake the system, but the sleep button cannot. although the ich8 does not include a specific signal designated as a sleep button, one of the gpio signals can be used to create a ?control method? sleep button. see the advanced configuration and power interface, version 2.0b for implementation details. 5.13.9.2 ri# (ring indicator) the ring indicator can cause a wake event (if enabled) from the s1?s5 states. table 72 shows when the wake event is generated or ignored in different states. if in the g0/s0/cx states, the ich8 generates an interrupt based on ri# active, and the interrupt will be set up as a break event. note: filtering/debounce on ri# will not be done in ich8. can be in modem or external. 5.13.9.3 pme# (pci power management event) the pme# signal comes from a pci device to request that the system be restarted. the pme# signal can generate an smi#, sci, or optionally a wake event. the event occurs when the pme# signal goes from high to low. no event is caused when it goes from low to high. there is also an internal pme_b0 bit. this is separate from the external pme# signal and can cause the same effect. 5.13.9.4 sys_reset# signal when the sys_reset# pin is detected as active after the 16 ms debounce logic, the ich8 attempts to perform a ?graceful? reset, by waiting up to 25 ms for the smbus to go idle. if the smbus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter starts. if at any point during the count the smbus goes idle the reset occurs. if, however, the counter expires and the smbus is still active, a reset is forced upon the system ev en though activity is still occurring. once the reset is asserted, it remains assert ed for 5 to 6 ms regardless of whether the sysreset# input remains asserted or not. it cannot occur again until sys_reset# has been detected inactive after the debounce logic, and the system is back to a full s0 state with pltrst# inactive. note that if bit 3 of the cf9h i/o register is set then sys_reset# will result in a full power cycle reset. table 72. transitions due to ri# signal present state event ri_en event s0 ri# active x ignored s1?s5 ri# active 0 1 ignored wake event functional description 176 intel ? ich8 family datasheet 5.13.9.5 thrmtrip# signal if thrmtrip# goes active, the processor is indicating an overheat condition, and the ich8 immediately transitions to an s5 state. however, since the processor has overheated, it does not respond to the ich8?s stpclk# pin with a stop grant special cycle. therefore, the ich8 does not wait for one. immediately upon seeing thrmtrip# low, the ich8 initiates a transition to the s5 state, drive slp_s3#, slp_s4#, slp_s5# low, and set the cts bit. the transiti on looks like a power button override. it is extremely important that when a thrmtrip# event occurs, the ich8 power down immediately without following the normal s0 -> s5 path. this path may be taken in parallel, but ich8 must immediately enter a po wer down state. it does this by driving slp_s3#, slp_s4#, and slp_s5# immediately after sampling thrmtrip# active. if the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the ich8, are no longer executing cycles properly. therefore, if thrmtrip# goes ac tive, and the ich8 is relying on state machine logic to perform the power down, th e state machine may not be working, and the system will not power down. the ich8 follows this flow for thrmtrip#. 1. at boot (pltrst# low), thrmtrip# ignored. 2. after power-up (pltrst# high), if thrmtrip# sampled active, slp_s3#, slp_s4#, and slp_s5# assert, and normal sequence of sleep machine starts. 3. until sleep machine enters the s5 state, slp_s3#, slp_s4#, and slp_s5# stay active, even if thrmtrip# is now inactive. this is the equivalent of ?latching? the thermal trip event. 4. if s5 state reached, go to step #1, othe rwise stay here. if the ich8 never reaches s5, the ich8 does not reboot until power is cycled. during boot, thrmtrip# is ignored until slp_s3#, pwrok, vrmpwrgd/vgate, and pltrst# are all ?1?. during entry into a powered-down state (due to s3, s4, s5 entry, power cycle reset, etc.) thrmtrip# is igno red until either slp_s3# = 0, or pwrok = 0, or vrmpwrgd/vgate = 0. note: a thermal trip event will: ? set the afterg3_en bit ? clear the pwrbtn_sts bit ? clear all the gpe0_en register bits ? clear the smb_wak_sts bit only if smb_sak_sts was set due to smbus slave receiving message and not set due to smbalert 5.13.9.6 bmbusy# (mobile only) the bmbusy# signal is an input from a graphics component to indicate if it is busy. if prior to going to the c3 state, the bmbusy# signal is active, then the bm_sts bit will be set. if after going to the c3 state, th e bmbusy# signal goes back active, the ich8 will treat this as if one of the pci req# sign als went active. this is treated as a break event. intel ? ich8 family datasheet 177 functional description 5.13.10 alt access mode before entering a low power state, severa l registers from powered down parts may need to be saved. in the majority of cases, this is not an issue, as registers have read and write paths. however, several of the isa compatible registers are either read only or write only. to get data out of write-only registers, and to restore data into read-only registers, the ich8 implements an alt access mode. if the alt access mode is entered and exited after reading the registers of the ich8 timer (8254), the timer starts counting faster (13.5 ms). the following steps listed below can cause problems: 1. bios enters alt access mode for re ading the ich8 timer related registers. 2. bios exits alt access mode. 3. bios continues through the execution of other needed steps and passes control to the operating system. after getting control in step #3, if the oper ating system does not reprogram the system timer again, the timer ticks may be happen ing faster than expected. for example dos and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. operating systems (e.g., microsoft window s* 98, windows* 2000, and windows nt*) reprogram the system timer and theref ore do not encounter this problem. for some other loss (e.g., microsoft ms-dos*) the bios should restore the timer back to 54.6 ms before passing control to the op erating system. if the bios is entering alt access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from alt access mode. 5.13.10.1 write only registers with read paths in alt access mode the registers described in table 73 have read paths in alt access mode. the access number field in the table indicates which register will be returned per access to that port. functional description 178 intel ? ich8 family datasheet table 73. write only registers with read paths in alt access mode (sheet 1 of 2) restore data restore data i/o addr # of rds access data i/o addr # of rds access data 00h 2 1 dma chan 0 base address low byte 40h 7 1 timer counter 0 status, bits [5:0] 2 dma chan 0 base address high byte 2 timer counter 0 base count low byte 01h 2 1 dma chan 0 base count low byte 3 timer counter 0 base count high byte 2 dma chan 0 base count high byte 4 timer counter 1 base count low byte 02h 2 1 dma chan 1 base address low byte 5 timer counter 1 base count high byte 2 dma chan 1 base address high byte 6 timer counter 2 base count low byte 03h 2 1 dma chan 1 base count low byte 7 timer counter 2 base count high byte 2 dma chan 1 base count high byte 41h 1 timer counter 1 status, bits [5:0] 04h 2 1 dma chan 2 base address low byte 42h 1 timer counter 2 status, bits [5:0] 2 dma chan 2 base address high byte 70h 1 bit 7 = nmi enable, bits [6:0] = rtc address 05h 2 1 dma chan 2 base count low byte c4h 2 1 dma chan 5 base address low byte 2 dma chan 2 base count high byte 2 dma chan 5 base address high byte 06h 2 1 dma chan 3 base address low byte c6h 2 1 dma chan 5 base count low byte 2 dma chan 3 base address high byte 2 dma chan 5 base count high byte 07h 2 1 dma chan 3 base count low byte c8h 2 1 dma chan 6 base address low byte 2 dma chan 3 base count high byte 2 dma chan 6 base address high byte intel ? ich8 family datasheet 179 functional description notes: 1. the ocw1 register must be read before entering alt access mode. 2. bits 5, 3, 1, and 0 return 0. 5.13.10.2 pic reserved bits many bits within the pic are reserved, and must have certain values written in order for the pic to operate properly. therefore, there is no need to return these values in alt access mode. when reading pic registers from 20h and a0h, the reserved bits shall return the values listed in table 74 . 08h 6 1 dma chan 0?3 command 2 cah 2 1 dma chan 6 base count low byte 2 dma chan 0?3 request 2 dma chan 6 base count high byte 3 dma chan 0 mode: bits(1:0) = 00 cch 2 1 dma chan 7 base address low byte 4 dma chan 1 mode: bits(1:0) = 01 2 dma chan 7 base address high byte 5 dma chan 2 mode: bits(1:0) = 10 ceh 2 1 dma chan 7 base count low byte 6 dma chan 3 mode: bits(1:0) = 11. 2 dma chan 7 base count high byte 20h 12 1 pic icw2 of master controller d0h 6 1 dma chan 4?7 command 2 2 pic icw3 of master controller 2 dma chan 4?7 request 3 pic icw4 of master controller 3 dma chan 4 mode: bits(1:0) = 00 4 pic ocw1 of master controller 1 4 dma chan 5 mode: bits(1:0) = 01 5 pic ocw2 of master controller 5 dma chan 6 mode: bits(1:0) = 10 6 pic ocw3 of master controller 6 dma chan 7 mode: bits(1:0) = 11. 7 pic icw2 of slave controller 8 pic icw3 of slave controller 9 pic icw4 of slave controller 10 pic ocw1 of slave controller 1 11 pic ocw2 of slave controller 12 pic ocw3 of slave controller table 73. write only registers with read paths in alt access mo de (sheet 2 of 2) restore data restore data i/o addr # of rds access data i/o addr # of rds access data functional description 180 intel ? ich8 family datasheet 5.13.10.3 read only registers with write paths in alt access mode the registers described in table 75 have write paths to them in alt access mode. software restores these values after retu rning from a powered down state. these registers must be handled special by softwa re. when in normal mode, writing to the base address/count register also writes to the current address/count register. therefore, the base address/count must be wr itten first, then the part is put into alt access mode and the current address/count register is written. 5.13.11 system power suppli es, planes, and signals 5.13.11.1 power plane control with slp_s3#, slp_s4#, slp_s5# and slp_m# the slp_s3# output signal can be used to cut power to the system core supply, since it only goes active for the str state (typical ly mapped to acpi s3). power must be maintained to the ich8 resume well, and to any other circuits that need to generate wake signals from the str state. cutting power to the core may be done via the power supply, or by external fets to the motherboard. the slp_s4# or slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the memo ry may be done via the power supply, or by external fets to the motherboard. the slp_s4# output signal is used to remove power to additional subsystems that are powered during slp_s3#. slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the memory may be done via the power supply, or by external fets to the motherboard. slp_m# output signal can be used to cut powe r to the link controller, clock chip or spi flash on a platform that supports intel amt. table 74. pic reserved bits return values pic reserved bits value returned icw2(2:0) 000 icw4(7:5) 000 icw4(3:2) 00 icw4(0) 0 ocw2(4:3) 00 ocw3(7) 0 ocw3(5) reflects bit 6 ocw3(4:3) 01 table 75. register write acce sses in alt access mode i/o address register write value 08h dma status regist er for channels 0?3. d0h dma status regist er for channels 4?7. intel ? ich8 family datasheet 181 functional description 5.13.11.2 slp_s4# and suspend-to-ram sequencing the system memory suspend voltage regulator is controlled by the glue logic. the slp_s4# signal should be used to remove power to system memory rather than the slp_s5# signal. the slp_s4# logic in the ic h8 provides a mechanism to fully cycle the power to the dram and/or detect if the power is not cycled for a minimum time. note: to utilize the minimum dram power-down feature that is enabled by the slp_s4# assertion stretch enable bit (d31:f0:a4h bit 3), the dram power must be controlled by the slp_s4# signal. 5.13.11.3 pwrok signal the pwrok input should go active based on the core supply voltages becoming valid. pwrok should go active no sooner than 100 ms after vcc3_3 and vcc1_5 have reached their nominal values. note: 1. sysreset# is recommended for implementi ng the system reset button. this saves external logic that is needed if the pwrok input is used. additionally, it allows for better handling of the smbus and processor resets, and avoids improperly reporting power failures. 2. if the pwrok input is used to implemen t the system reset button, the ich8 does not provide any mechanism to limit the amount of time that the processor is held in reset. the platform must externally assu re that maximum reset assertion specs are met. 3. if a design has an active-low reset button electrically and?d with the pwrok signal from the power supply and the processo r?s voltage regulator module the ich8 pwrok_flr bit will be set. the ich8 treats this internally as if the rsmrst# signal had gone active. however, it is not treated as a full power failure. if pwrok goes inactive and then active (but rsmrst# stays high), then the ich8 reboots (regardless of the state of the afterg3 bi t). if the rsmrst# signal also goes low before pwrok goes high, then this is a full power failure, and the reboot policy is controlled by the afterg3 bit. 4. pwrok and rsmrst# are sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the ich8. 5. in the case of true pwrok failure, pw rok goes low first before the vrmpwrgd. 6. when pwrok goes inactive, a host power cycle and global reset will occur. a host power cycle is the assertion of slp_s3#, slp_s4#, and slp_s5#, and the deassertion of these signals 3-5 seconds later. the me remains powered throughout this cycle. 5.13.11.4 cpupwrgd signal this signal is connected to the processor?s vrm via the vrmpwrgd signal and is internally and?d with the pwrok signal that comes from the system power supply. 5.13.11.5 vrmpwrgd signal vrmpwrgd is an input from the regulator indicating that all of the outputs from the regulator are on and within specification. vr mpwrgd may go active before or after the pwrok from the main power supply. ich8 ha s no dependency on the order in which these two signals go active or inactive. however, platforms that use the vrmpwrgd signal to start the clock chip plls assume that it does assert milliseconds before pwrok in order to provide valid clocks in time for the pwrok rising. functional description 182 intel ? ich8 family datasheet note: when vrmpwrgd goes inactive, a host power cycle and global reset will occur. 5.13.11.6 batlow# (batte ry low) (mobile only) the batlow# input can inhibit waking from s3, s4, and s5 states if there is not sufficient power. it also causes an smi# if the system is already in an s0 state. 5.13.11.7 controlling leakag e and power consumption during low-power states to control leakage in the system, various signals tri-state or go low during some low- power states. general principles: ? all signals going to powered down planes (e ither internally or externally) must be either tri-stated or driven low. ? signals with pull-up resistors should not be low during low-power states. this is to avoid the power consumed in the pull-up resistor. ? buses should be halted (and held) in a known state to avoid a floating input (perhaps to some other device). floating inputs can cause extra power consumption. based on the above principles, the following measures are taken: ? during s3 (str), all signals attached to powered down planes are tri-stated or driven low. 5.13.12 clock generators the clock generator is expected to provide the frequencies shown in table 76 . table 76. intel ? ich8 clock inputs clock domain frequency source usage sata_clk 100 mhz differential main clock generator used by sata controller. st opped in s3 ~ s5 based on slp_s3# assertion. dmi_clk 100 mhz differential main clock generator used by dmi and pci express*. stopped in s3 ~ s5 based on slp_s3# assertion. pciclk 33 mhz main clock generator desktop: free-running pci cl ock to ich8. stopped in s3 ~ s5 based on slp_s3# assertion. mobile: free-running (not affected by stp_pci# pci clock to ich8. this is not the system pci clock. this clock must keep running in s0 while the system pci clock may stop based on clkrun# protocol. stopped in s3 ~ s5 based on slp_s3# assertion. clk48 48.000 mhz main clock generator used by usb controllers and intel ? high definition audio controller. stopped in s3 ~ s5 based on slp_s3# assertion. clk14 14.318 mhz main clock generator used by acpi timers. stopped in s3 ~ s5 based on slp_s3# assertion. lan_clk 0.8 to 50 mhz lan connect lan connect interface. contro l policy is determined by the clock source. intel ? ich8 family datasheet 183 functional description 5.13.12.1 clock contro l signals from intel ? ich8 to clock synthesizer (mobile only) the clock generator is assumed to have direct connect from the following ich8 signals: ? stp_cpu#: stops processor clocks in c3 and c4 states ? stp_pci#: stops system pci clocks (not the ich8 free-running 33 mhz clock) due to clkrun# protocol ? slp_s3#: expected to drive clock chip pwrdown (through inverter), to stop clocks in s3 to s5. 5.13.13 legacy power management theory of operation instead of relying on acpi software, legacy power management uses bios and various hardware mechanisms. the scheme relies on th e concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. however, the operating system is assumed to be at least apm enabled. without apm calls, there is no quick way to know when the system is idle between keystrokes. the ich8 does not support burst modes. 5.13.13.1 apm power mana gement (desktop only) the ich8 has a timer that, when enabled by the 1min_en bit in the smi control and enable register, generates an smi# once per minute. the smi handler can check for system activity by reading the devact_sts regi ster. if none of the system bits are set, the smi handler can increment a software counter. when the counter reaches a sufficient number of consecutive minutes with no activity, the smi handler can then put the system into a lower power state. if there is activity, various bits in the deva ct_sts register will be set. software clears the bits by writing a 1 to the bit position. the devact_sts register allows for monitori ng various internal devices, or super i/o devices (sp, pp, fdc) on lpc or pci, keyb oard controller accesses, or audio functions on lpc or pci. other pci activity can be monitored by checking the pci interrupts. 5.13.13.2 mobile apm power management (mobile only) in mobile systems, there are additional re quirements associated with device power management. to handle this, the ich8 has specific smi# traps available. the following algorithm is used: 1. the periodic smi# timer checks if a device is idle for the require time. if so, it puts the device into a low-power state and sets the associated smi# trap. 2. when software (not the smi# handler) attempts to access the device, a trap occurs (the cycle does not really go to the device and an smi# is generated). 3. the smi# handler turns on the device and turns off the trap the smi# handler exits with an i/o restart. this allows the original software to continue. functional description 184 intel ? ich8 family datasheet 5.14 system management (d31:f0) the ich8 provides various functions to make a system easier to manage and to lower the total cost of ownership (tco) of the system. in addition, ich8 provides integrated asf management support. features and functions can be augmented via external a/d converters and gpio, as well as an external microcontroller. the following features and functi ons are supported by the ich8: ? processor present detection ? detects if processor fails to fetch the first instruction after reset ? various error detection (such as ecc errors) indicated by host controller ? can generate smi#, sci, serr, nmi, or tco interrupt ? intruder detect input ? can generate tco interrupt or smi# when the system cover is removed ? intruder# allowed to go active in any power state, including g3 ? detection of bad bios flash (fwh or flash on spi) programming ? detects if data on first read is ffh (indicates that bios flash is not programmed) ? ability to hide a pci device ? allows software to hide a pci device in terms of configuration space through the use of a device hide register (see section 7.1.71 ) note: voltage id from the processor can be read via gpi signals. note: asf functionality with the integrated ic h8 asf controller re quires a correctly configured system, including an appropriat e (g)mch with me, me firmware, system bios support, and appropriate platform lan connect device. 5.14.1 theory of operation the system management functions are designed to allow the system to diagnose failing subsystems. the intent of this logic is that some of the system management functionality be provided without the aid of an external microcontroller. 5.14.1.1 detecting a system lockup when the processor is reset, it is expected to fetch its first instruction. if the processor fails to fetch the first instruction after reset, the tco timer times out twice and the ich8 asserts pltrst#. 5.14.1.2 handling an intruder the ich8 has an input signal, intruder#, that can be attached to a switch that is activated by the system?s case being open. this input has a two rtc clock debounce. if intruder# goes active (after the debouncer ), this will set the intrd_det bit in the tco_sts register. the intrd_sel bits in the tco_cnt register can enable the ich8 to cause an smi# or interrupt. the bios or in terrupt handler can then cause a transition to the s5 state by writing to the slp_en bit. the software can also directly read the status of the intruder# signal (high or low) by clearing and then reading the intrd_det bit. th is allows the signal to be used as a gpi if the intruder function is not required. intel ? ich8 family datasheet 185 functional description if the intruder# signal goes inactive some point after the intrd_det bit is written as a 1, then the intrd_det signal will go to a 0 when intruder# input signal goes inactive. note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. note: the intrd_det bit resides in the ich8?s rtc well, and is set and cleared synchronously with the rtc clock. thus, wh en software attempts to clear intrd_det (by writing a 1 to the bit location) there may be as much as two rtc clocks (about 65 s) delay before the bit is actually cleare d. also, the intruder# signal should be asserted for a minimum of 1 ms to assu re that the intrd_det bit will be set. note: if the intruder# signal is still active when software attempts to clear the intrd_det bit, the bit remains set and the smi is ge nerated again immediately. the smi handler can clear the intrd_sel bits to avoid furthe r smis. however, if the intruder# signal goes inactive and then active again, there will not be further smis, since the intrd_sel bits would select that no smi# be generated. 5.14.1.3 detecting improper firmware hub programming the ich8 can detect the case where the bios flash is not programmed. this results in the first instruction fetched to have a value of ffh. if this occurs, the ich8 sets the bad_bios bit. the bios flash may reside in fwh or flash on the spi bus. 5.14.2 tco modes 5.14.2.1 tco legacy/compatible mode in tco legacy/compatible mode the intel ma nagement engine and intel amt logic and smbus controllers are disabled. to enable legacy/compatible tco mode the tcomode bit 7 in the ichstrp0 register in the spi device must be 0. see section 20.2.5.1 for details. note: smbus and smlink may be tied together ex ternally, if a device has a single smbus interface and needs access to the tco slave and be visible to the host smbus controller. functional description 186 intel ? ich8 family datasheet . in tco legacy/compatible mode the intel ic h8/ich8m can function directly with the integrated gigabit ethernet controller or equivalent external lan controller to report messages to a network management console without the aid of the system processor. this is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. table 78 includes a list of events that will report messages to the network management console. note: the gpio11/smbalert# pin will trigger an event message (when enabled by the gpio11_alert_disable bit) re gardless of whether it is configured as a gpi or not. table 77. tco legacy/compatible mode smbus configuration host smbus tco slave intel ? ich8 spd (slave) uctrl legacy sensors (master or slave with alert) asf sensors (master or slave) tco compatible mode smbus intel ? amt smbus controller 1 intel ? amt smbus controller 2 smlink x x table 78. event transitions that cause messages event assertion? deassertion? comments intruder# pin yes no must be in ?s1 or hung s0? state thrm# pin yes yes must be in ?s1 or hung s0? state. note that the thrm# pin is isolated when the core power is of f, thus preventing this event in s3-s5. watchdog timer expired yes no (na) ?s1 or hung s0? state entered gpio[11]/ smbalert# pin yes yes must be in ?s1 or hung s0? state batlow# yes yes must be in ?s1 or hung s0? state cpu_pwr_flr yes no ?s1 or hung s0? state entered intel ? ich8 family datasheet 187 functional description 5.14.2.2 advanced tco mode intel ich8/ich8m supports two modes of advanced tco. intel ? active management technology mode and bmc mode. to enable advance tco mode (amt or bmc mode) the tcomode bit 7 in the ichstrp0 register in the spi device must be 1. see section 20.2.5.1 for details. advanced tco intel? active management technology mode in this mode, intel amt smbus controller 1, host smbus and smlink are connected together internally. see figure below. this mode is enabled when the bmcmode bit 15 in the ichstrp0 register in the spi device is 0. see section 20.2.5.1 for details. the intel amt smbus controller 2 can be connected to either the smbus pins or the smlink pins by the mesm2sel bit 23 in the ichstrp0 register in the spi device. see section 20.2.5.1 for details. the default is to have the intel amt smbus controller 2 connected to smlink. the amt smbus contro ller 2 has no connection to linkalert#. 5.14.2.3 advanced tco bmc mode in this mode, the external microcontrolle r (bmc) is connected to both smlink and smbus. the bmc communicates with ma nagement engine through amt smbus connected to smlink. the host and tco slave communicated with bmc through smbus. see figure below. this mode is enabled when the bmcmode bit 15 in the ichstrp0 register in the spi device is 1. see section 20.2.5.1 for details. figure 11. advanced tco intel? amt mode smbus/smlink configuration amt smbus controller 1 host smbus intel ? ich8 spd (slave) uctrl legacy sensors (master or slave with alert) asf sensors (master or slave) advanced tco amt mode amt smbus controller 2 smbus tco slave embedded controller smlink intel ? amt smbus controller 1 host smbus spd (slave) uctrl legacy sensors (master or slave with alert) asf sensors (master or slave) advanced tco amt mode intel ? amt smbus controller 2 smbus tco slave embedded controller smlink functional description 188 intel ? ich8 family datasheet figure 12. advanced tco bmc mode smbus/smlink configuration host smbus tco slave intel ? ich8 spd (slave) legacy sensors (master or slave with alert) asf sensors (master or slave) advanced tco bmc mode intel ? amt smbus controller 1 smbus bmc smlink intel ? amt smbus controller 2 intel ? ich8 family datasheet 189 functional description 5.15 ide controller (d 31:f1) (mobile only) the ich8 ide controller features one set of interface signals that can be enabled, tri- stated or driven low. the ide interfaces of the ich8 can su pport several types of data transfers: ? programmed i/o (pio): processor is in control of the data transfer. ? 8237 style dma: dma protocol that resembles the dma on the isa bus, although it does not use the 8237 in the ich8. this protocol off loads the processor from moving data. this allows higher transfer rate of up to 16 mb/s. ? ultra ata/33: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 33 mb/s. ? ultra ata/66: dma protocol that redefines signal s on the ide cable to allow both host and target throttling of data and transfer rates of up to 66 mb/s. ? ultra ata/100: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 100 mb/s. 5.15.1 pio transfers the ich8 ide controller includes both compatible and fast timing modes. the fast timing modes can be enabled only for the ide data ports. all other transactions to the ide registers are run in single transaction mode with compatible timings. up to two ide devices may be attached to the ide connector (drive 0 and drive 1). the ide_timp and ide_tims registers permit di fferent timing modes to be programmed for drive 0 and drive 1 of the same connector. the ultra ata/33/66/100 synchronous dma timing modes can also be applied to each drive by programming the ide i/o configuration register and the synchronous dma control and timing registers. when a dr ive is enabled for synchronous dma mode operation, the dma transfers are executed with the synchronous dma timings. the pio transfers are executed using compatible timings or fast timings if also enabled. 5.15.1.1 pio ide timing modes ide data port transaction latency consists of startup latency, cycle latency, and shutdown latency. startup latency is incurred when a pci master cycle targeting the ide data port is decoded and the da[2:0] and csxx# lines are not set up. startup latency provides the setup time for the da[2 :0] and csxx# lines prior to assertion of the read and write strobes (dior# and diow#). cycle latency consists of the i/o command strobe assertion length and recovery time. recovery time is provided so that transactions may occur back-to-back on the ide interface (without incurring startup and shutdown latency) without violating minimum cycle periods for the ide interface. the command strobe assertion width for the enhanced timing mode is selected by the ide_tim register and may be set to 2, 3, 4, or 5 pci clocks. the recovery time is selected by the ide_tim register and may be set to 1, 2, 3, or 4 pci clocks. if iordy is asserted when the initial sample point is reached, no wait-states are added to the command strobe assertion length. if iordy is negated when the initial sample point is reached, additional wait-states are added. since the rising edge of iordy must be synchronized, at least two additional pci clocks are added. functional description 190 intel ? ich8 family datasheet shutdown latency is incurred after outstanding scheduled ide data port transactions (either a non-empty write post buffer or an outstanding read prefetch cycles) have completed and before other transactions can proceed. it provides hold time on the da[2:0] and csxx# lines with respect to the read and write strobes (dior# and diow#). shutdown latency is two pci clocks in duration. the ide timings for various transaction types are shown in table 79 . 5.15.1.2 iordy masking the iordy signal can be ignored and assumed asserted at the first iordy sample point (isp) on a drive by drive basis via the idetim register. 5.15.1.3 pio 32-bit ide data port accesses a 32-bit pci transaction run to the ide data address (01f0h primary) results in two back-to-back 16-bit transactions to the ide data port. the 32-bit data port feature is enabled for all timings, not just enhanced timing. for compatible timings, a shutdown and startup latency is incurred between the tw o, 16-bit halves of the ide transaction. this assures that the chip selects are dea sserted for at least tw o pci clocks between the two cycles. 5.15.1.4 pio ide data port prefetching and posting the ich8 can be programmed via the idetim registers to allow data to be posted to and prefetched from the ide data ports. data prefetching is initiated when a data port read occurs. the read prefetch eliminates latency to the ide data ports and allows them to be performed back-to-back for the highest possible pio data transfer rates. the first data port read of a sector is called the demand read. subsequent data port reads from the sector are called prefetch reads. the demand read and all prefetch reads much be of the same size (16 or 32 bits) ? software must not mix 32-bit and 16-bit reads. data posting is performed for writes to the ide data ports. the transaction is completed on the pci bus after the data is received by the ich8. the ich8 then runs the ide cycle to transfer the data to the drive. if the ic h8 write buffer is non-empty and an unrelated (non-data or opposite channel) ide transact ion occurs, that transaction will be stalled until all current data in the write buffer is tr ansferred to the drive. only 16-bit buffer writes are supported. table 79. ide transactio n timings (pci clocks) ide transaction type startup latency iordy sample point (isp) recovery time (rct) shutdown latency non-data port compatible 4 11 22 2 data port compatible 3 6 14 2 fast timing mode 2 2?5 1?4 2 intel ? ich8 family datasheet 191 functional description 5.15.2 bus master function the ich8 can act as a pci bus master on behalf of an ide device. one pci bus master channel is provided for the ide connector. by performing the ide data transfer as a pci bus master, the ich8 off-loads the proce ssor and improves system performance in multitasking environments. both devices attached to the connector can be programmed for bus master transfers, but only one device can be active at a time. 5.15.2.1 physical region descriptor format the physical memory region to be transferred is described by a physical region descriptor (prd). the prds are stored sequ entially in a descriptor table in memory. the data transfer proceeds until all regions described by the prds in the table have been transferred. descriptor tables must not cross a 64-kb boundary. each prd entry in the table is 8 bytes in length. the first 4 bytes specify the byte address of a physical memory region. this memory region must be dw ord-aligned and must not cross a 64-kb boundary. the next two bytes specify the size or transfer count of the region in bytes (64-kb limit per region). a value of 0 in these two bytes indicates 64-kb (thus the minimum transfer count is 1). if bit 7 (eot) of the last byte is a 1, it indicates that this is the final prd in the descriptor table. bus master operation terminates when the last descriptor has been retired. when the bus master ide controller is readin g data from the memory regions, bit 1 of the base address is masked and byte enables are asserted for all read transfers. when writing data, bit 1 of the base address is not masked and if set, will cause the lower word byte enables to be deasserted for the first dword transfer. the write to pci typically consists of a 32-byte cache line. if valid data ends prior to end of the cache line, the byte enables will be deasserted for invalid data. the total sum of the byte counts in every pr d of the descriptor table must be equal to or greater than the size of the disk transfer request. if greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the bus master ide command register to 0) when the drive issues an interrupt to signal transfer completion. figure 13. physical region descriptor table entry eot reserved byte count [15:1] memory region physical base address [31:1] byte 3 byte 2 byte 1 byte 0 memory region main memory o o functional description 192 intel ? ich8 family datasheet 5.15.2.2 bus master ide timings the timing modes used for bus master ide transfers are identical to those for pio transfers. the dma timing enable only bits in ide timing register can be used to program fast timing mode for dma transactio ns only. this is useful for ide devices whose dma transfer timings are faster than its pio transfer timings. the ide device dma request signal is sampled on the same pci clock that dior# or diow# is deasserted. if inactive, the dma acknowledg e signal is deasserted on the next pci clock and no more transfers take place until dma request is asserted again. 5.15.2.3 interrupts the ich8 can generate interrupts based upon a signal coming from the pata device, or due to the completion of a prd with the ?i? bit set. the interrupt is edge triggered and active high. the pata host controller generates ideirq. when the ich8 ide controller is operatin g independently from the sata controller (d31:f2), ideirq will generate irq14. when operating in conjunction with the sata controller (combined mode), ide interrupts w ill still generate ideirq, but this may in turn generate either irq14 or irq15, depending upon the value of the map.mv (d31:f2:90h:bits 1:0) register. when in combined mode and the sata controller is emulating the logical secondary channel (map.mv = 1h), the pata channel will emulate the logical primary channel and ideirq will generate irq14. conversely, if the sata controller in combined mode is emulating the logical primary channel (map.mv=2h), ideirq will generate irq15. note: ide interrupts cannot be communicated throug h pci devices or the serial irq stream. 5.15.2.4 bus master ide operation to initiate a bus master transfer between memory and an ide device, the following steps are required: 1. software prepares a prd table in system memory. the prd table must be dword- aligned and must not cross a 64-kb boundary. 2. software provides the starting address of the prd table by loading the prd table pointer register. the direction of the data transfer is specified by setting the read/ write control bit. the interrupt bit and error bit in the status register are cleared. 3. software issues the appropriate dma transfer command to the disk device. 4. the bus master function is engaged by software writing a 1 to the start bit in the command register. the first entry in the prd table is fetched and loaded into two registers which are not visible by software, the current base and current count registers. these registers hold the current value of the address and byte count loaded from the prd table. the value in th ese registers is only valid when there is an active command to an ide device. 5. once the prd is loaded internally, the ide device will receive a dma acknowledge. 6. the controller transfers data to/from memo ry responding to dma requests from the ide device. the ide device and the host controller may or may not throttle the transfer several times. when the last data transfer for a region has been completed on the ide interface, the next descriptor is fetched from the table. the descriptor contents are loaded into the current base and current count registers. 7. at the end of the transfer, the ide device signals an interrupt. 8. in response to the interrupt, software resets the start/stop bit in the command register. it then reads the controller status followed by the drive status to determine if the transfer completed successfully. intel ? ich8 family datasheet 193 functional description the last prd in a table has the end of list (eol) bit set. the pci bus master data transfers terminate when the physical region described by the last prd in the table has been completely transferred. the active bi t in the status register is reset and the ddrq signal is masked. the buffer is flushed (when in the write state) or invalidated (when in the read state) when a terminal count condition exists; that is, the current region descriptor has the eol bit set and that region has been exhausted. the buffer is also flushed (write state) or invalidated (read state) when the interrupt bit in the bus master ide status register is set. software that reads the status regist er and finds the error bit reset, and either the active bit reset or the interrupt bit set, can be assured that all data destined for system memory has been transferred and that data is valid in system memory. table 80 describes how to interpret the interrupt and active bits in the status register after a dma transfer has started. 5.15.2.5 error conditions ide devices are sector based mass storage devices. the drivers handle errors on a sector basis; either a sector is transferred successfully or it is not. a sector is 512 bytes. if the ide device does not complete the tran sfer due to a hardware or software error, the command will eventually be stopped by the driver setting command start bit to 0 when the driver times out the disk transactio n. information in the ide device registers help isolate the cause of the problem. if the controller encounters an error while doing the bus master transfers it will stop the transfer (i.e., reset the active bit in the command register) and set the error bit in the bus master ide status register. the controller does not generate an interrupt when this happens. the device driver can use devi ce specific information (pci configuration space status register and ide drive register) to determine what caused the error. whenever a requested transfer does not co mplete properly, info rmation in the ide device registers (sector count) can be used to determine how much of the transfer was completed and to construct a new prd table to complete the requested operation. in most cases the existing prd table can be used to complete the operation. table 80. interrupt/active bit interaction definition interrupt active description 0 1 dma transfer is in progress. no inte rrupt has been generated by the ide device. 1 0 the ide device generate d an interrupt. the controller exhausted the physical region descript ors. this is the normal completion case where the size of the physical memory re gions was equal to the ide device transfer size. 1 1 the ide device generated an interrupt. the cont roller has not reached the end of the physical memory region s. this is a valid completion case where the size of the physical memo ry regions was larger than the ide device transfer size. 0 0 this bit combination signals an error condition. if the error bit in the status register is set, then the controller has so me problem transferring data to/from memory. specifics of the error have to be determined using bus-specific information. if the er ror bit is not set, then the prds specified a smaller size than the ide transfer size. functional description 194 intel ? ich8 family datasheet 5.15.3 ultra ata/100/66/33 protocol the ich8 supports ultra ata/100/66/33 bus mastering protocol, providing support for a variety of transfer speeds with ide device s. ultra ata/33 provides transfers up to 33 mb/s, ultra ata/66 provides transfers at up to 44 mb/s or 66 mb/s, and ultra ata/100 can achieve read transfer rates up to 100 mb/s and write transfer rates up to 88.9 mb/s. the ultra ata/100/66/33 definition also incorporates a cyclic redundancy checking (crc-16) error checking protocol. 5.15.3.1 operation initial setup programming consists of enablin g and performing the proper configuration of the ich8 and the ide device for ultra ata/100/66/33 operation. for the ich8, this consists of enabling synchronous dma mode and setting up appropriate synchronous dma timings. when ready to transfer data to or from an ide device, the bus master ide programming model is followed. once programmed, the drive and ich8 control the transfer of data via the ultra ata/100/66/33 protocol. the actual data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase. the ide device begins the start-up phase by asserting dmarq signal. when ready to begin the transfer, the ich8 asserts dmack# signal. when dmack# signal is asserted, the host controller drives cs0# and cs1# inactive, da0?da2 low. for write cycles, the ich8 deasserts stop, waits for the ide device to assert dmardy#, and then drives the first data word and strobe signal. for read cycles, the ich8 tri-states the dd lines, deasserts stop, and asserts dmardy#. the id e device then sends the first data word and strobe. the data transfer phase continues the burst transfers with the data transmitter (ich8 ? writes, ide device ? reads) providing data and togg ling strobe. data is transferred (latched by receiver) on each rising and falling edge of strobe. the transmitter can pause the burst by holding strobe high or low, resuming the burst by again toggling strobe. the receiver can pause the burst by deasserting dmardy# and resumes the transfers by asserting dmardy #. the ich8 pauses a burst transaction to prevent an internal line buffer over or under flow condition, resuming once the condition has cleared. it may also pause a transaction if the current prd byte count has expired, resuming once it has fetched the next prd. the current burst can be terminated by either the transmitter or receiver. a burst termination consists of a stop request, st op acknowledge and transfer of crc data. the ich8 can stop a burst by asserting st op, with the ide device acknowledging by deasserting dmarq. the ide device stops a burst by deasserting dmarq and the ich8 acknowledges by asserting stop. the transmi tter then drives the strobe signal to a high level. the ich8 then drives the cr c value onto the dd lines and deassert dmack#. the ide device latches the crc valu e on rising edge of dmack#. the ich8 terminates a burst transfer if it needs to service the opposite ide channel, if a programmed i/o (pio) cycle is executed to the ide channel currently running the burst, or upon transferring the last data from the final prd. intel ? ich8 family datasheet 195 functional description 5.15.4 ultra ata/33/66/100 timing the timings for ultra ata/33/66/100 modes are programmed via the synchronous dma timing register and the ide configuration register. different timings can be programmed for each drive in the system. the base clock frequency for each drive is selected in the ide configuration register. the cycle time (ct) and ready to pause (rp) time (defined as multiples of the ba se clock) are programmed in the synchronous dma timing register. the cycle time repres ents the minimum pulse width of the data strobe (strobe) signal. the ready to pause time represents the number of base clock periods that the ich8 waits from deassert ion of dmardy# to the assertion of stop when it desires to stop a burst read transaction. note: the internal base clock for ultra ata/100 (mode 5) runs at 133 mhz, and the cycle time (ct) must be set for three base cloc ks. the ich8 thus toggles the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe edge. this means that the ich8 performs mode 5 write tran sfers at a maximum rate of 88.9 mb/s. for read transfers, the read strobe is driven by the ata/100 device, and the ich8 supports reads at the maximum rate of 100 mb/s. 5.15.5 ata swap bay to support pata swap bay, the ich8 allows the ide output signals to be tri-stated and input buffers to be turned off. this should be done prior to the removal of the drive. the output signals can also be driven low. this can be used to remove charge built up on the signals. configuration bits are included in the ide i/o configuration register, offset 54h in the ide pci configuration space. in a pata swap bay operation, an ide devi ce is removed and a new one inserted while the ide interface is powered down and the rest of the system is in a fully powered-on state (so). during a pata swap bay operation, if the operating system executes cycles to the ide interface after it has been powere d down it will cause the ich8 to hang the system that is waiting for iordy to be asserted from the drive. to correct this issue, the following bios pr ocedures are required for performing an ide swap: 1. program ide sig_mode (configuration register at offset 54h) to 10b (drive low mode). 2. clear iordy sample point enable (bits 1 or 5 of ide timing reg.). this prevents the ich8 from waiting for iordy assertion when the operating system accesses the ide device after the ide drive powers do wn, and ensures that 0s are always be returned for read cycles that occur during swap operation. warning: software should not attempt to control the outputs (either tri-state or driving low), while an ide transfer is in progress. unpredictable results could occur, including a system lockup. 5.15.6 smi trapping device 31:function 1: offset c0h (see section 12.1.56 ) contain control for generating smi# on accesses to the ide i/o spaces. these bits map to the legacy ranges (1f0 ? 1f7h and 3f6h). accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to th e ide controller, and for an smi# to be generated. if an access to the bus-master ide registers occurs while trapping is enabled for the device being accessed, then the register is updated, an smi# is generated, and the device activity status bits (device 31:function 1:offset c4h) are updated indicating that a trap occurred. functional description 196 intel ? ich8 family datasheet 5.16 sata host controller (d31:f2, f5) the sata function in the ich8 has three modes of operation to support different operating system conditions. in the case of native ide enabled operating systems, the ich8 utilizes two controllers to enable all six ports of the bus. the first controller (device 31: function 2) supports ports 0 -3 and the second controller (device 31: function 5) supports ports 4 an d 5. when using a legacy operating system, only one controller (device 31: function 2) is available that supports ports 0 ? 3. in ahci or raid mode, only one controller (dev ice 31: function 2) is utilized enabling all six ports. the map register, section 13.1.29 , provides the ability to share pci functions. when sharing is enabled, all decode of i/o is done through the sata registers. device 31, function 1 (ide controller) is hidden by software writing to the function disable register (d31, f0, offset f2h, bit 1), and its configuration registers are not used. the ich8 sata controllers feature six (desktop only) / three (mobile only) sets of interface signals (ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). each interface is supported by an independent dma controller. the ich8 sata controllers interact with an attached mass storage device through a register interface that is equivalent to that presented by a traditional ide host adapter. the host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. note: sata interface transfer rates are independen t of udma mode settings. sata interface transfer rates will operate at the bus?s ma ximum speed, regardless of the udma mode reported by the sata device or the system bios. table 81. sata feature support feature ich8 (ahci/ raid disabled) ich8 (ahci/ raid enabled) native command queuing (ncq) n/a supported auto activate for dma n/a supported hot plug support n/a supported asynchronous signal recovery n/a supported 3 gb/s transfer rate supported supported atapi asynchronous notification n/a supported host initiated power management n/a supported (mobile only) staggered spin-up supported supported command completion coalescing n/a n/a port multiplier n/a n/a external sata n/a supported (desktop only) intel ? ich8 family datasheet 197 functional description 5.16.1 theory of operation 5.16.1.1 standard ata emulation the ich8 contains a set of registers that shadow the contents of the legacy ide registers. the behavior of the command and control block registers, pio, and dma data transfers, resets, and interrupts are all emulated. note: the ichn will assert intr when the ma ster device completes the edd command regardless of the command completion status of the slave device. if the master completes edd first, an intr is generated and bsy will remain '1' until the slave completes the command. if the slave comple tes edd first, bsy will be '0' when the master completes the edd command and asserts intr. software must wait for busy to clear (0) before completing an edd command, as required by the ata5 through ata7 (t13) industry standards. 5.16.1.2 48-bit lba operation the sata host controller supports 48-bit lba through the host-to-device register fis when accesses are performed via writes to the task file. the sata host controller will ensure that the correct data is put into the correct byte of the host-to-device fis. table 82. sata feature support feature description native command queuing (ncq) allows the device to reorder co mmands for more efficient data transfers auto activate for dma collapses a dma setup then dma activate sequence into a dma setup only hot plug support allows for device detection wi thout power being applied and ability to connect and discon nect devices without prior notification to the system asynchronous signal recovery provides a recovery from a loss of signal or establishing communication after hot plug 3 gb/s transfer rate capable of data transfers up to 3gb/s atapi asynchronous notification a mechanism for a device to send a notification to the host that the device requires attention host initiated power management capability for the host controller to request partial and slumber interface power states staggered spin-up enables the host the ability to spin up hard drives sequentially to prevent power load problems on boot command completion coalescing reduces interrupt and completi on overhead by allowing a specified number of commands to complete and then generating an interrupt to process the commands port multiplier a mechanism for one active ho st connection to communicate with multiple devices external sata technology that allows for an outside the box connection of up to 2 meters (when using the cable defined in sata-io) functional description 198 intel ? ich8 family datasheet there are special considerations when reading from the task file to support 48-bit lba operation. software may need to read all 16 -bits. since the registers are only 8-bits wide and act as a fifo, a bit must be set in the device/control register, which is at offset 3f6h for primary and 376h for secondary (or their native counterparts). if software clears bit 7 of the control regist er before performing a read, the last item written will be returned from the fifo. if software sets bi t 7 of the control register before performing a read, the first item written will be returned from the fifo. 5.16.2 sata swap bay support dynamic hot-plug (e.g., surprise removal) is not supported by the sata host controller without special support from ahci and the proper board hardware. however, the ich8 does provide for basic sata swap bay support using the psc register configuration bits and power management flows. a device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. note: this sata swap bay operation requires bo ard hardware (implementation specific), bios, and operating system support. 5.16.3 intel ? matrix storage technolo gy configuration (intel ? ich8r, ich8dh, ich8do, and ich8m-e only) the intel ? matrix storage technology offers several diverse options for raid (redundant array of independent disks) to meet the needs of the end user. ahci support provides higher performance and alleviates disk bottlenecks by taking advantage of the independent dma engines that each sata port offers in ich8. ? raid level 0 performance scaling up to 4 drives, enabling higher throughput for data intensive applications such as video editing. ? data security is offered through raid level 1, which performs mirroring. ? raid level 10 provides high levels of storage performance with data protection, combining the fault-tolerance of raid level 1 with the performance of raid level 0. by striping raid level 1 segments, high i/o rates can be achieved on systems that require both performance and fault-tolerance. raid level 10 requires 4 hard drives, and provides the capacity of two drives. ? raid level 5 provides highly efficient storage while maintaining fault-tolerance on 3 or more drives. by striping parity, and rotating it across all disks, fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity. that is, a 3 drive raid 5 has the capacity of 2 drives, or a 4 drive raid 5 has the capacity of 3 drives. raid 5 has high read transaction rates, with a medium write rate. raid 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance. by using the ich8?s built-in intel matrix storage technology, there is no loss of pci resources (request/grant pair) or add-in card slot. intel ? matrix storage technology functionality requires the following items: 1. ich8 component enabled for intel matrix storage technology (see section 1.2 ) 2. intel ? matrix storage manager raid option rom must be on the platform 3. intel ? matrix storage manager drivers, most recent revision. 4. at least two sata hard disk drives (minimum depends on raid configuration). intel matrix storage technology is not av ailable in the following configurations: 1. the sata controller in compatible mode. intel ? ich8 family datasheet 199 functional description 5.16.3.1 intel ? matrix storage manager raid option rom the intel matrix storage manager raid option rom is a standard pnp option rom that is easily integrated into any system bios. when in place, it provides the following three primary functions: ? provides a text mode user interface that allows the user to manage the raid configuration on the system in a pre-oper ating system environment. its feature set is kept simple to keep size to a minimum, but allows the user to create & delete raid volumes and select recovery options when problems occur. ? provides boot support when using a raid vo lume as a boot disk. it does this by providing int13 services when a raid volume needs to be accessed by dos applications (such as ntldr) and by ex porting the raid volumes to the system bios for selection in the boot order. ? at each boot up, provides the user with a status of the raid volumes and the option to enter the user interface by pressing ctrl-i. 5.16.4 power management operation power management of the ich8 sata contro ller and ports will cover operations of the host controller and the sata wire. 5.16.4.1 power state mappings the d0 pci power management state for device is supported by the ich8 sata controller. sata devices may also have multiple power states. from parallel ata, three device states are supported through acpi. they are: ? d0 ? device is working and instantly available. ? d1 ? device enters when it receives a standby immediate command. exit latency from this state is in seconds ? d3 ? from the sata device?s perspective, no different than a d1 state, in that it is entered via the standby immediate command. however, an acpi method is also called which will reset the device and then cut its power. each of these device states are subsets of the host controller?s d0 state. finally, sata defines three phy layer power states, which have no equivalent mappings to parallel ata. they are: ? phy ready ? phy logic and pll are both on and active ? partial ? phy logic is powered, but in a reduced state. exit latency is no longer than 10 ns ? slumber ? phy logic is powered, but in a reduced state. exit latency can be up to 10 ms. since these states have much lower exit latency than the acpi d1 and d3 states, the sata controller defines these states as sub-states of the device d0 state. functional description 200 intel ? ich8 family datasheet 5.16.4.2 power state transitions 5.16.4.2.1 partial and slumber state entry/exit the partial and slumber states save interface power when the interface is idle. it would be most analogous to pci clkrun# (in power savings, not in mechanism), where the interface can have power saved while no commands are pending. the sata controller defines phy layer power management (as performed via primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. the sata controller accepts device transition types, but does not issue any transitions as a host. all received requests from a sata device will be acked. when an operation is performed to the sata controller such that it needs to use the sata cable, the controller must check whet her the link is in the partial or slumber states, and if so, must issue a com_wake to bring the link back online. similarly, the sata device must perform the same action. 5.16.4.2.2 device d1, d3 states these states are entered after some period of time when software has determined that no commands will be sent to this device for some time. the mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to th e device. the command most likely to be used in ata/atapi is the ?standby immediate? command. 5.16.4.2.3 host controller d3 hot state after the interface and device have been pu t into a low power state, the sata host controller may be put into a low power stat e. this is performed via the pci power management registers in configuration space. there are two very important aspects to note when using pci power management. 1. when the power state is d3, only accesses to configuration space are allowed. any attempt to access the memory or i/o spaces will result in master abort. 2. when the power state is d3, no interrupt s may be generated, even if they are enabled. if an interrupt status bit is pending when the controller transitions to d0, an interrupt may be generated. when the controller is put into d3, it is a ssumed that software has properly shut down the device and disabled the ports. therefore, there is no need to sustain any values on the port wires. the interface will be treated as if no device is present on the cable, and power will be minimized. when returning from a d3 state, an internal reset will not be performed. figure 14. sata power states intel ? ich sata controller = d0 device = d3 power res ume latency device = d0 phy = ready device = d1 phy = slumber phy = partial phy = off (port disabled) phy = slumber phy = off (port disabled) phy = slumber phy = off (port disabled) intel ? ich8 family datasheet 201 functional description 5.16.4.2.4 non-ahci mode pme# generation when in non-ahci mode (legacy mode) of operation, the sata controller does not generate pme#. this includes attach events (since the port must be disabled), or interlock switch events (via the satagp pins). 5.16.4.3 smi trapping (apm) device 31:function2:offset c0h (see section 12.1.56 ) contain control for generating smi# on accesses to the ide i/o spaces. these bits map to the legacy ranges (1f0?1f7h, 3f6h, 170?177h, and 376h). if the sa ta controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to th e sata controller, and for an smi# to be generated. if an access to the bus-master ide registers occurs while trapping is enabled for the device being accessed, then the register is updated, an smi# is generated, and the device activity status bits ( section 12.1.56 ) are updated indicating that a trap occurred. 5.16.5 sata led the sataled# output is driven whenever the bsy bit is set in any sata port. the sataled# is an active-low open-collector output. when sataled# is low, the led should be active. when sataled# is high, the led should be inactive. 5.16.6 ahci operation the ich8 provides hardware support for ad vanced host controller interface (ahci), a programming interface for sata host controllers developed through a joint industry effort. ahci defines transactions between the sata controller and software and enables advanced performance and usability with sata. platforms supporting ahci may take advantage of performance features such as no master/slave designation for sata devices?each device is treated as a master?and hardware assisted native command queuing. ahci also provides usability enhanc ements such as hot-plug. ahci requires appropriate software support (e.g., an ahci driver) and for some features, hardware support in the sata device or additional platform hardware. the ich8 supports all of the mandatory features of the serial ata advanced host controller interface specification , revision 1.0 and many optional features, such as hardware assisted native command queuing, aggressive power management, led indicator support, and hot-plug through the use of interlock switch support (additional platform hardware and software may be re quired depending upon the implementation). note: for reliable device removal notification wh ile in ahci operation without the use of interlock switches (surprise removal), interf ace power management should be disabled for the associated port. see section 7.3.1 of the ahci specification for more information. functional description 202 intel ? ich8 family datasheet 5.16.7 serial ata reference clock low power request (sataclkreq#) the 100 mhz serial ata reference clock (sataclkp, sataclkn) is implemented on the system as a ground-terminated low-voltage differential signal pair driven by the system clock chip. when all the sata links are in slumber or disabled, the sata reference clock is not needed and may be stopped and tri-stated at the clock chip allowing system-level power reductions. the ich8 uses the sataclkreq# output signal to communicate with the system clock chip to request either sata clock running or to tell the system clock chip that it can stop the sata reference clock. ich8 drives this signal low to request clock running, and tristates the signal to indicate that th e sata reference clock may be stopped (the ich8 never drives the pin high). when the sataclkreq# is tristated by the ich8, the clock chip may stop the sata reference cl ock within 100 ns, anytime after 100 ns, or not at all. if the sata reference clock is not already running, it will start within 100 ns after a sataclkreq# is driven low by the ich8. to enable sata reference clock low power request: 1. configure gpio35 to native function 2. set sata clock request enable (scre) bit to ?1? (dev 31:f2:offset 94h:bit 28). note: the reset default for sataclkreq# is low to ensure that the sata reference clock is running after system reset. 5.16.8 sgpio signals the sgpio signals, in accordance to the sff-8485 specification, support per-port led signaling. these signals are not related to sataled#, which allows for simplified indication of sata command activity. the sgpio group interfaces with an external controller chip that fetches and serializes the data for driving across the sgpio bus. the output signals then control the leds. 5.16.9 external sata (intel ? ich8r, ich8dh, and ich8do only) ich8 supports external sata . external sata uses the sata interface outside of the system box. the usage model for this feature must comply with the serial ata ii cables and connectors volume 2 gold specif ication at www.sata-io.org. intel validates two configurations: 1. the "cable-up" solution involves an internal sata cable that connects to the sata motherboard connector and spans to a back panel pci bracket with an e-sata connector. a separate e-sata cable is required to connect an e-sata device. 2. the back-panel solution involves running a trace to the i/o back panel and connecting a device via an external sata connector on the board. note: port multipliers are not suppor ted on ich8. there is no hot plugging of the os host device. intel ? matrix storage technology must be present to support external sata. intel ? ich8 family datasheet 203 functional description 5.17 high precision event timers this function provides a set of timers that can be used by the operating system. the timers are defined such that in the future, the operating system may be able to assign specific timers to used directly by specific applications. each timer can be configured to cause a separate interrupt. ich8 provides three timers. the three timers are implemented as a single counter each with its own comparator and value register. this counter increases monotonically. each individual timer can generate an interrupt wh en the value in its value register matches the value in the main counter. the registers associated with these timers are mapped to a memory space (much like the i/o apic). however, it is not implemen ted as a standard pci function. the bios reports to the operating system the location of the register space. the hardware can support an assignable decode space; however, the bios sets this space prior to handing it over to the operating system (see section 6.4 ). it is not expected that the operating system will move the location of these timers once it is set by the bios. 5.17.1 timer accuracy 1. the timers are accurate over any 1 ms peri od to within 0.05% of the time specified in the timer resolution fields. 2. within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. the timer is monotonic. it does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). the main counter is clocked by the 14.3 1818 mhz clock, synchronized into the 66.666 mhz domain. this results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. the accuracy of the main counter is as accurate as the 14.3818 mhz clock. 5.17.2 interrupt mapping mapping option #1 (legacy replacement option) in this case, the legacy replacement rout bit (leg_rt_cnf) is set. this forces the mapping found in table 83 . mapping option #2 (standard option) in this case, the legacy replacement rout bit (leg_rt_cnf) is 0. each timer has its own routing control. the supported inte rrupt values are irq 20, 21, 22, and 23. table 83. legacy replacement routing timer 8259 mapping apic mapping comment 0 irq0 irq2 in this case, the 8254 timer will not cause any interrupts 1 irq8 irq8 in this case, the rtc will not cause any interrupts. 2 per irq routing field. per irq routing field functional description 204 intel ? ich8 family datasheet 5.17.3 periodic vs. no n-periodic modes non-periodic mode timer 0 is configurable to 32 (default) or 64-bit mode, whereas timers 1 and 2 only support 32-bit mode (see section 19.1.5 ). all three timers support non-periodic mode. consult section 2.3.9.2.1 of the ia-pc hpet specification for a description of this mode. periodic mode timer 0 is the only timer that supports periodic mode. consult section 2.3.9.2.2 of the ia-pc hpet specification for a description of this mode. the following usage model is expected: 1. software clears the enable_cnf bit to prevent any interrupts 2. software clears the main counter by writing a value of 00h to it. 3. software sets the timer0_val_set_cnf bit. 4. software writes the new value in the timer0_comparator_val register 5. software sets the enable_c nf bit to enable interrupts. the timer 0 comparator value register cannot be programmed reliably by a single 64- bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. if the actual timer 0 compar ator value needs to be reinitialized, then the following software solution will alwa ys work regardless of the environment: 1. set timer0_val_set_cnf bit 2. set the lower 32 bits of the timer0 comparator value register 3. set timer0_val_set_cnf bit 4. 4) set the upper 32 bits of the timer0 comparator value register 5.17.4 enabling the timers the bios or operating system pnp code shou ld route the interrupts. this includes the legacy rout bit, interrupt rout bit (for each timer), interrupt type (to select the edge or level type for each timer) the device driver code should do the following for an available timer: 1. set the overall enable bit (offset 04h, bit 0). 2. set the timer type field (selects one-shot or periodic). 3. set the interrupt enable 4. set the comparator value intel ? ich8 family datasheet 205 functional description 5.17.5 interrupt levels interrupts directed to the internal 8259s are active high. see section 5.9 for information regarding the polarity programmin g of the i/o apic for detecting internal interrupts. if the interrupts are mapped to the i/o apic and set for level-triggered mode, they can be shared with pci interrupts. this may be shared although it?s unlikely for the operating system to attempt to do this. if more than one timer is configured to share the same irq (using the timern_int_rout_cnf fields), then the software must configure the timers to level- triggered mode. edge-triggered interrupts cannot be shared. 5.17.6 handling interrupts if each timer has a unique interrupt and the timer has been configured for edge- triggered mode, then there are no specific steps required. no read is required to process the interrupt. if a timer has been configured to level-tr iggered mode, then its interrupt must be cleared by the software. this is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. if timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register. 5.17.7 issues related to 64-bit timers with 32-bit processors a 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions. however, a 32-bit processor may not be able to directly read 64-bit timer. a race condition comes up if a 32-bit processor reads the 64-bit register using two separate 32-bit reads. the danger is that just after reading one half, the other half rolls over and changes the first half. if a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. if a 32-bit processor does not want to halt the timer, it can use the 64-b it timer as a 32-bit timer by setting the timern_32mode_cnf bit. this causes the timer to behave as a 32-bit timer. the upper 32-bits are always 0. functional description 206 intel ? ich8 family datasheet 5.18 usb uhci host controllers (d29:f0, f1, f2 and d26:f0, f1) the ich8 contains five usb full/low-speed ho st controllers that support the standard universal host controller interface (uhci), revision 1.1. each uhci host controller (uhc) includes a root hub with two separate usb ports each, for a total of ten usb ports. ? overcurrent detection on all ten usb ports is supported. the overcurrent inputs are not 5 v tolerant, and can be used as gpis if not needed. ? the ich8?s uhci host controllers are arbitrated differently than standard pci devices to improve arbitration latency. ? the uhci controllers use the analog fr ont end (afe) embedded cell that allows support for usb full-speed signaling rates, instead of usb i/o buffers. 5.18.1 data structures in main memory section 3.1 - 3.3 of the universal host controller interface specification, revision 1.1 details the data structures used to commu nicate control, status, and data between software and the ich8. 5.18.2 data transfers to/from main memory section 3.4 of the universal host controller interface specification, revision 1.1 describes the details on how hcd and the ich8 communicate via the schedule data structures. 5.18.3 data encoding and bit stuffing the ich8 usb employs nrzi data encoding (non-return to zero inverted) when transmitting packets. full details on this implementation are given in the universal serial bus specification, revision 2.0 . 5.18.4 bus protocol 5.18.4.1 bit ordering bits are sent out onto the bus least signific ant bit (lsb) first, followed by next lsb, through to the most significant bit (msb) last. 5.18.4.2 sync field all packets begin with a synchronization (sync) field, which is a coded sequence that generates a maximum edge transition densit y. the sync field appears on the bus as idle followed by the binary string ?kjkjkjkk, ? in its nrzi encoding. it is used by the input circuitry to align incoming data with the local clock and is defined to be 8 bits in length. sync serves only as a synchronizat ion mechanism. full details are given in the universal serial bus specification, revision 2. 0, in section 8.3.1. the last two bits in the sync field are a marker that is used to identify the first bit of the pid. all subsequent bits in the packet must be indexed from this point. 5.18.4.3 packet field formats all packets have distinct start and end of packet delimiters. full details are given in the universal serial bus specification, revision 2.0, in section 8.3.1. intel ? ich8 family datasheet 207 functional description 5.18.4.4 address fields function endpoints are addressed using th e function address field and the endpoint field. full details on this are given in the universal serial bus specification, revision 2.0 , in section 8.3.2. 5.18.4.5 frame number field the frame number field is an 11-bit field that is incremented by the host on a per frame basis. the frame number field rolls over upon reaching its maximum value of 7ffh, and is sent only for sof tokens at the start of each frame. 5.18.4.6 data field the data field may range from 0 to 1023 by tes and must be an integral numbers of bytes. data bits within each byte are shifted out lsb first. 5.18.4.7 cyclic redundancy check (crc) crc is used to protect the all non-pid fields in token and data packets. in this context, these fields are considered to be protected fields. full details on this are given in the universal serial bus specification, revision 2.0 , in section 8.3.5. 5.18.5 packet formats the usb protocol calls out several packet types: token, data, and handshake packets. full details on this are given in the universal serial bus specification, revision 2.0 , in section 8.4. 5.18.6 usb interrupts there are two general groups of usb interrupt sources, those resulting from execution of transactions in the schedule, and those re sulting from an ich8 operation error. all transaction-based sources can be masked by software through the ich8?s interrupt enable register. additionally, individual tran sfer descriptors can be marked to generate an interrupt on completion. when the ich8 drives an interrupt for usb, it internally drives the pirqa# pin for usb function #0 and usb function #3, pirqd# pin for usb function #1, and the pirqc# pin for usb function #2, until all sources of the interrupt are cleared. in order to accommodate some operating systems, the interrupt pin register must contain a different value for each function of this new multi-function device. 5.18.6.1 transaction-based interrupts these interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. this assures that software can safely process through (frame list current index -1) when it is servicing an interrupt. crc error / time-out a crc/time-out error occurs when a packet transmitted from the ich8 to a usb device or a packet transmitted from a usb device to the ich8 generates a crc error. the ich8 is informed of this event by a time-out from the usb device or by the ich8?s crc checker generating an error on reception of the packet. additionally, a usb bus time- out occurs when usb devices do not respond to a transaction phase within 19-bit times of an eop. either of these conditions causes the c_err field of the td to decrement. functional description 208 intel ? ich8 family datasheet when the c_err field decrements to 0, the following occurs: ? the active bit in the td is cleared ? the stalled bit in the td is set ? the crc/time-out bit in the td is set. ? at the end of the frame, the usb error interrupt bit is set in the hc status register. if the crc/time out interrupt is enabled in the interrupt enable register, a hardware interrupt will be signaled to the system. interrupt on completion transfer descriptors contain a bit that ca n be set to cause an interrupt on their completion. the completion of the transaction associated with that block causes the usb interrupt bit in the hc status register to be set at the end of the frame in which the transfer completed. when a td is encoun tered with the ioc bit set to 1, the ioc bit in the hc status register is set to 1 at the end of the frame if the active bit in the td is set to 0 (even if it was set to 0 when initially read). if the ioc enable bit of interrupt enable regi ster (bit 2 of i/o offset 04h) is set, a hardware interrupt is signaled to the syst em. the usb interrupt bit in the hc status register is set either when the td complete s successfully or because of errors. if the completion is because of errors, the usb error bit in the hc status register is also set. short packet detect a transfer set is a collection of data which requires more than one usb transaction to completely move the data across the usb. an example might be a large print file which requires numerous tds in multiple frames to completely transfer the data. reception of a data packet that is less than the endpoint?s max packet size during control, bulk or interrupt transfers signals the completion of the transfer set, even if there are active tds remaining for this transfer set. setting the spd bit in a td indicates to the hc to set the usb interrupt bit in the hc status register at the end of the frame in which this event occurs. this feature streamlines the processing of input on these transfer types. if the short packet interrupt enable bit in the interrupt enable register is set, a hardware interrupt is signaled to the syst em at the end of the frame where the event occurred. serial bus babble when a device transmits on the usb for a time greater than its assigned max length, it is said to be babbling. since isochrony can be destroyed by a babbling device, this error results in the active bit in the td being cleared to 0 and the stalled and babble bits being set to 1. the c_err field is not decremented for a babble. the usb error interrupt bit in the hc status register is se t to 1 at the end of the frame. a hardware interrupt is signaled to the system. if an eof babble was caused by the ich8 (d ue to incorrect schedule for instance), the ich8 forces a bit stuff error followed by an eop and the start of the next frame. stalled this event indicates that a device/endpo int returned a stall handshake during a transaction or that the transaction ended in an error condition. the tds stalled bit is set and the active bit is cleared. reception of a stall does not decrement the error counter. a hardware interrupt is signaled to the system. intel ? ich8 family datasheet 209 functional description data buffer error this event indicates that an overrun of inco ming data or a under-run of outgoing data has occurred for this transaction. this would generally be caused by the ich8 not being able to access required data buffers in me mory within necessary latency requirements. either of these conditions causes the c_ err field of the td to be decremented. when c_err decrements to 0, the active bit in the td is cleared, the stalled bit is set, the usb error interrupt bit in the hc status re gister is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. bit stuff error a bit stuff error results from the detection of a sequence of more that six 1s in a row within the incoming data stream. this causes the c_err field of the td to be decremented. when the c_err field decrements to 0, the active bit in the td is cleared to 0, the stalled bit is set to 1, the usb erro r interrupt bit in the hc status register is set to 1 at the end of the frame and a hard ware interrupt is signaled to the system. 5.18.6.2 non-transaction based interrupts if an ich8 process error or system error occur, the ich8 halts and immediately issues a hardware interrupt to the system. resume received this event indicates that the ich8 received a resume signal from a device on the usb bus during a global suspend. if this interrupt is enabled in the interrupt enable register, a hardware interrupt is signaled to the system allowing the usb to be brought out of the suspend state and returned to normal operation. ich8 process error the hc monitors certain critical fields during operation to ensure that it does not process corrupted data structures. these include checking for a valid pid and verifying that the maxlength field is less than 1280. if it detects a condition that would indicate that it is processing corrupted data structures, it immediately halts processing, sets the hc process error bit in the hc status register and signals a hardware interrupt to the system. this interrupt cannot be disabled th rough the interrupt enable register. host system error the ich8 sets this bit to 1 when a parity error, master abort, or target abort occur. when this error occurs, the ich8 clears the run/stop bit in the command register to prevent further execution of the scheduled tds. this interrupt cannot be disabled through the interrupt enable register. functional description 210 intel ? ich8 family datasheet 5.18.7 usb power management the host controller can be put into a suspended state and its power can be removed. this requires that certain bits of information are retained in the resume power plane of the ich8 so that a device on a port may wake the system. such a device may be a fax- modem, which will wake up the machine to re ceive a fax or take a voice message. the settings of the following bits in i/o space will be maintained when the ich8 enters the s3, s4, or s5 states. when the ich8 detects a resume event on any of its ports, it sets the corresponding usb_sts bit in acpi space. if usb is en abled as a wake/break event, the system wakes up and an sci generated. 5.18.8 usb legacy keyboard operation when a usb keyboard is plugged into the sy stem, and a standard keyboard is not, the system may not boot, and ms-dos legacy so ftware will not run, because the keyboard will not be identified. the ich8 implements a series of trapping operations which will snoop accesses that go to the keyboard cont roller, and put the expected data from the usb keyboard into the keyboard controller. note: the scheme described below assumes that the keyboard controller (8042 or equivalent) is on the lpc bus. this legacy operation is performed through smm space. figure 15 shows the enable and status path. the latched smi source (60r, 60w, 64r, 64w) is available in the status register. because the enable is after the latch, it is possible to check for other events that didn't necessarily cause an sm i. it is the software's responsibility to logically and the value with the appropriate enable bits. note also that the smi is generated before the pci cycle completes (e.g., before trdy# goes active) to ensure that the processor doesn't complete the cycle before the smi is observed. this method is used on mpiix and has been validated. the logic also needs to block the accesses to the 8042. if there is an external 8042, then this is simply accomplished by not activating the 8042 cs. this is simply done by logically anding the four enables (60r, 60w, 64r, 64w) with the 4 types of accesses to determine if 8042cs should go active. an a dditional term is required for the ?pass- through? case. the state table for the diagram is shown in table 85 . table 84. bits maintained in low power states register offset bit description command 00h 3 enter global suspend mode (egsm) status 02h 2 resume detect port status and control 10h & 12h 2 port enabled/disabled 6 resume detect 8 low-speed device attached 12 suspend intel ? ich8 family datasheet 211 functional description figure 15. usb legacy keyboard flow diagram table 85. usb legacy keyboard state transitions current state action data value next state comment idle 64h / write d1h gatestate1 standard d1 command. cycle passed through to 8042. smi# doesn't go active. pstate (offset c0, bit 6) goes to 1. idle 64h / write not d1h idle bit 3 in config register determines if cycle passed through to 8042 and if smi# generated. idle 64h / read n/a idle bit 2 in config register determines if cycle passed through to 8042 and if smi# generated. idle 60h / write don't care idle bit 1 in config register determines if cycle passed through to 8042 and if smi# generated. idle 60h / read n/a idle bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. gatestate1 60h / write xxh gatestate2 cycle passed through to 8042, even if trap enabled in bit 1 in config register. no smi# generated. pstate remains 1. if data value is not dfh or ddh then the 8042 may chose to ignore it. kbc accesses pci config read, write 60 read clear smi_60_r en_smi_on_60r comb. decoder and same for 60w, 64r, 64w smi or to individual "caused by" "bits" to pirqd# to "caused by" bit and and en_pirqd# usb_irq clear usb_irq en_smi_on_irq s d r s d r functional description 212 intel ? ich8 family datasheet gatestate1 64h / write d1h gatestate1 cycle passed through to 8042, even if trap enabled via bit 3 in conf ig register. no smi# generated. pstate remains 1. stay in gatestate1 because this is part of the double-trigger sequence. gatestate1 64h / write not d1h ilde bit 3 in config space determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. gatestate1 60h / read n/a idle this is an invalid sequence. bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. gatestate1 64h / read n/a gatestate1 just stay in same state. generate an smi# if enabled in bit 2 of config register. pstate remains 1. gatestate2 64 / write ffh idle standard end of sequence. cycle passed through to 8042. pstate goes to 0. bit 7 in config space determines if smi# should be generated. gatestate2 64h / write not ffh idle improper end of sequence. bit 3 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. gatestate2 64h / read n/a gatestate2 just stay in same state. generate an smi# if enabled in bit 2 of config register. pstate remains 1. gatestate2 60h / write xxh idle improper end of sequence. bit 1 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. gatestate2 60h / read n/a idle improper end of sequence. bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. table 85. usb legacy keyboard state transitions current state action data value next state comment intel ? ich8 family datasheet 213 functional description 5.19 usb ehci host contro llers (d29:f7 and d26:f7) the ich8 contains two enhanced host controller interface (ehci) host controllers which support up to ten usb 2.0 high-speed root ports. usb 2.0 allows data transfers up to 480 mb/s using the same pins as the ten usb full-speed/low-speed ports. the ich8 contains port-routing logic that determines whether a usb port is controlled by one of the uhci controllers or by one of the ehci controllers. usb 2.0 based debug port is also implemented in the ich8. a summary of the key architectural differences between the usb uhci host controllers and the ehci host controller are shown in table 86 . 5.19.1 ehc initialization the following descriptions step through the expected ich8 enhanced host controller (ehc) initialization sequence in chronologica l order, beginning with a complete power cycle in which the suspend well and core well have been off. 5.19.1.1 bios initialization bios performs a number of platform customization steps after the core well has powered up. contact your intel field representative for additional ich8 bios information. 5.19.1.2 driver initialization see chapter 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0. table 86. uhci vs. ehci parameter usb uhci usb ehci accessible by i/o space memory space memory data structure single linked list separated in to period ic and asynchronous lists differential signaling voltage 3.3 v 400 mv ports per controller 2 6 (controller #1) and 4 (controller #2) functional description 214 intel ? ich8 family datasheet 5.19.1.3 ehc resets in addition to the standard ich8 hardware resets, portions of the ehc are reset by the hcreset bit and the transition from the d3 hot device power management state to the d0 state. the effects of each of these resets are listed in the following table. if the detailed register descriptions give exceptions to these rules, those exceptions override these rules. this summary is provid ed to help explain the reasons for the reset policies. 5.19.2 data structures in main memory see section 3 and appendix b of the enhanced host controller interface specification for universal serial bus, revision 1.0 for details. 5.19.3 usb 2.0 enhanced host controller dma the ich8 usb 2.0 ehc implements three source s of usb packets. they are, in order of priority on usb during each microframe: 1. the usb 2.0 debug port (see section usb 2.0 based debug port), 2. the periodic dma engine, and 3. the asynchronous dma engine. the ich8 always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. if there is time left in the microframe, then the ehc performs any pending asynchronous traffic until the end of the microframe (eof1). note that the debug port traffic is only presented on one port (port #0), while the other ports are idle during this time. 5.19.4 data encoding and bit stuffing see chapter 8 of the universal serial bus specification, revision 2.0. 5.19.5 packet formats see chapter 8 of the universal serial bus specification, revision 2.0 . the ich8 ehci allows entrance to usb test modes, as defined in the usb 2.0 specification, including test j, test packet, etc. however note that the ich8 test packet test mode interpacket gap timing ma y not meet the usb 2.0 specification. reset does reset does not reset comments hcreset bit set. memory space registers except structural parameters (which is written by bios). configuration registers. the hcreset must only affect registers that the ehci driver controls. pci configuration space and bios-programmed parameters can not be reset. software writes the device power state from d3 hot (11b) to d0 (00b). core well registers (except bios- programmed registers). suspend well registers; bios- programmed core well registers. the d3-to-d0 transition must not cause wake information (suspend well) to be lost. it also must not clear bios- programmed registers because bios may not be invoked following the d3-to-d0 transition. intel ? ich8 family datasheet 215 functional description 5.19.6 usb 2.0 interrupts and error conditions section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 goes into detail on the ehc interrupts and the error conditions that cause them. all error conditions that the ehc detects can be reported through the ehci interrupt status bits. only ich8-specific interrupt and error-reporting behavior is documented in this section. the ehci interrupts section must be read first, followed by this section of the datasheet to fully comp rehend the ehc interrupt and error-reporting functionality. ? based on the ehc?s buffer sizes and buffer management policies, the data buffer error can never occur on the ich8. ? master abort and target abort responses from hub interface on ehc-initiated read packets will be treated as fatal host erro rs. the ehc halts when these conditions are encountered. ? the ich8 may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal writ e buffers. the requirement in the enhanced host controller interface specificatio n for universal serial bus, revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on dmi before the interrupt is asserted. ? since the ich8 supports the 1024-element frame list size, the frame list rollover interrupt occurs every 1024 milliseconds. ? the ich8 delivers interrupts using pirqh#. ? the ich8 does not modify the cerr count on an interrupt in when the ?do complete-split? execution criteria are not met. ? for complete-split transactions in the peri odic list, the ?missed microframe? bit does not get set on a control-structure-fetch that fails the late-start test. if subsequent accesses to that control structure do not fail the late-start test, then the ?missed microframe? bit will get set and written back. 5.19.6.1 aborts on usb 2. 0-initiated memory reads if a read initiated by the ehc is aborted, th e ehc treats it as a fatal host error. the following actions are taken when this occurs: ? the host system error status bit is set ? the dma engines are halted after completi ng up to one more transaction on the usb interface ? if enabled (by the host system error enable), then an interrupt is generated ? if the status is master abort, then the received master abort bit in configuration space is set ? if the status is target abort, then the received target abort bit in configuration space is set ? if enabled (by the serr enable bit in the function?s configuration space), then the signaled system error bit in configuration bit is set. functional description 216 intel ? ich8 family datasheet 5.19.7 usb 2.0 power management 5.19.7.1 usb pre-fetch pause feature the pre-fetch based pause is a power management feature in usb (ehci) host controllers to ensure maximum c3/c4 cpu power state time with c2 popup. this feature applies to the period schedule and work s by allowing the dma engine to identify periods of idleness and prevents the dma engine from accessing memory when the periodic schedule is idle. typically in the presence of periodic devices with multiple millisecond poll periods, the periodic schedule will be idle for several frames between polls. the usb pre-fetch based pause feature is disabled by setting bit 4 of ehci configuration register section 15.1.30 . 5.19.7.2 suspend feature the enhanced host controller interface (ehci) for universal serial bus specification , section 4.3 describes the details of port suspend and resume. 5.19.7.3 acpi device states the usb 2.0 function only supports the d0 and d3 pci power management states. notes regarding the ich8 implementation of the device states: 1. the ehc hardware does not inherently consume any more power when it is in the d0 state than it does in the d3 state. however, software is required to suspend or disable all ports prior to entering the d3 state such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ehc features are enabled. 3. in the d3 state, accesses to the ehc me mory-mapped i/o range will master abort. note that, since the debug port uses the same memory range, the debug port is only operational when the ehc is in the d0 state. 4. in the d3 state, the ehc interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power state field is wri tten to d0 from d3, an internal reset is generated. see section ehc resets for gene ral rules on the effects of this reset. 6. attempts to write any other value into the device power state field other than 00b (d0 state) and 11b (d3 state) will complete normally without changing the current value in this field. intel ? ich8 family datasheet 217 functional description 5.19.7.4 acpi system states the ehc behavior as it relates to other power management states in the system is summarized in the following list: ? the system is always in the s0 state when the ehc is in the d0 state. however, when the ehc is in the d3 state, the system may be in any power management state (including s0). ? when in d0, the pause feature (see section 5.19.7.1 ) enables dynamic processor low-power states to be entered. ? the pll in the ehc is disabled when entering the s3/s4/s5 states (core power turns off). ? all core well logic is reset in the s3/s4/s5 states. 5.19.7.5 mobile considerations the ich8 usb 2.0 implementation does not behave differently in the mobile configurations versus the desktop configurations. however, some features may be especially useful for the mobile configurations. ? if a system (e.g., mobile) does not im plement all ten usb 2.0 ports, the ich8 provides mechanisms for changing the stru ctural parameters of the ehc and hiding unused uhci controllers. see the intel ? ich8 bios specification for information on how bios should configure the ich8. ? mobile systems may want to minimize th e conditions that will wake the system. the ich8 implements the ?wake enable? bits in the port status and control registers, as specified in the ehci spec, for this purpose. ? mobile systems may want to cut suspend well power to some or all usb ports when in a low-power state. the ich8 implemen ts the optional port wake capability register in the ehc configuration space for this platform-specific information to be communicated to software. 5.19.8 interaction with uhci host controllers the enhanced host controllers share its ports with uhci host controllers in the ich8. the uhc at d29:f0 shares ports 0 and 1; th e uhc at d29:f1 shares ports 2 and 3; the uhc at d29:f2 shares ports 4 and 5 with the ehc at d29:f7, while the uhc at d26:f0 shares ports 6 and 7, the uhc at d26:f1 shares ports 8 and 9 with ehc at d26:f7. there is very little interaction between th e enhanced and the uhci controllers other than the multiplexing control which is provided as part of the ehc. figure 16 shows the usb port connections at a conceptual level. 5.19.8.1 port-routing logic integrated into the ehc functionality is port -routing logic, which performs the muxing between the uhci and ehci host controllers . the ich8 conceptually implements this logic as described in section 4.2 of the enhanced host controller interface specification for universal serial bus, revision 1.0. if a device is connected that is not capable of usb 2.0?s high-speed signaling protocol or if the ehci software drivers are not present as indicated by the configured flag, then the uhci controller owns the port. owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. the host controller that is not the owner of the port internally sees a disconnected port. functional description 218 intel ? ich8 family datasheet note that the port-routing logic is the only block of logic within the ich8 that observes the physical (real) connect/disconnect information. the port status logic inside each of the host controllers observes the electrical connect/disconnect information that is generated by the port-routing logic. only the differential signal pairs are mult iplexed/demultiplexed between the uhci and ehci host controllers. the other usb functional signals are handled as follows: ? the overcurrent inputs (oc[9:0]#) are di rectly routed to both controllers. an overcurrent event is recorded in both controllers? status registers. the port-routing logic is implemented in the suspend power well so that re- enumeration and re-mapping of the usb port s is not required following entering and exiting a system sleep state in which the core power is turned off. the ich8 also allows the usb debug port traffic to be routed in and out of port #0. when in this mode, the enhanced host controller is the owner of port 0. 5.19.8.2 device connects the enhanced host controller interface spec ification for universal serial bus, revision 1.0 describes the details of handling device connects in section 4.2. there are four general scenarios that are summarized below. 1. configure flag = 0 and a full-speed /low-speed-only device is connected ? in this case, the uhc is the owner of the port both before and after the connect occurs. the ehc (except for the port-routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. 2. configure flag = 0 and a high-speed-capable device is connected ? in this case, the uhc is the owner of the port both before and after the connect occurs. the ehc (except for the port-routing logic) never sees the connect occur. the uhci driver handles the conne ction and initialization process. since the uhc does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. configure flag = 1 and a full-speed /low-speed-only device is connected ? in this case, the ehc is the owner of the port before the connect occurs. the ehci driver handles the connection and pe rforms the port reset. after the reset process completes, the ehc hardware has cleared (not set) the port enable bit in the ehc?s portsc register. the ehci driver then writes a 1 to the port owner figure 16. intel ? ich8-usb port connections uhc i uhc i uhc i uhc i port 0 port 1 uhc i port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 uhci 1 uhci 4 uhci 2 port 1 device 29 ehci uhci 5 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 device 26 ehci uhci 3 intel ? ich8 family datasheet 219 functional description bit in the same register, causing the uh c to see a connect event and the ehc to see an ?electrical? disconnect event. the uhci driver and hardware handle the connection and initialization process from that point on. the ehci driver and hardware handle the perceived disconnect. 4. configure flag = 1 and a high-speed-capable device is connected ? in this case, the ehc is the owner of the port before, and remains the owner after, the connect occurs. the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehc hardware has set the port enable bit in the ehc?s portsc register . the port is functional at this point. the uhc continues to see an unconnected port. 5.19.8.3 device disconnects the enhanced host controller interface specification for universal serial bus, revision 1.0 describes the details of handling device connects in section 4.2. there are three general scenarios that are summarized below. 1. configure flag = 0 and the device is disconnected ? in this case, the uhc is the owner of the port both before and after the disconnect occurs. the ehc (except for the port-routing logic) never sees a device attached. the uhci driver handles disconnection process. 2. configure flag = 1 and a full-speed/low -speed-capable device is disconnected ? in this case, the uhc is the owner of th e port before the disconnect occurs. the disconnect is reported by the uhc and se rviced by the associated uhci driver. the port-routing logic in the ehc cluster forces the port owner bit to 0, indicating that the ehc owns the unconnected port. 3. configure flag = 1 and a high-speed-capable device is disconnected ? in this case, the ehc is the owner of the port before, and remains the owner after, the disconnect occurs. the ehci hardware and driver handle the disconnection process. the uhc never sees a device attached. 5.19.8.4 effect of resets on port-routing logic as mentioned above, the port routing logic is implemented in the suspend power well so that remuneration and re-mapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. 5.19.9 usb 2.0 legacy keyboard operation the ich8 must support the possibility of a keyboard downstream from either a full- speed/low-speed or a high-speed port. the de scription of the lega cy keyboard support is unchanged from usb 1.1 (see section 5.18.8 ). the ehc provides the basic ability to generate smis on an interrupt event, along with more sophisticated control of the generation of smis. reset event effect on configure flag effect on port owner bits suspend well reset cleared (0) set (1) core well reset no effect no effect d3-to-d0 reset no effect no effect hcreset cleared (0) set (1) functional description 220 intel ? ich8 family datasheet 5.19.10 usb 2.0 based debug port the ich8 supports the elimination of the le gacy com ports by providing the ability for new debugger software to interact with devices on a usb 2.0 port. high-level restrictions and features are: ? operational before usb 2.0 drivers are loaded. ? functions even when the port is disabled. ? works even though non-configured port is default-routed to the uhci. note that the debug port can not be used to debug an issue that requires a full-speed/low- speed device on port #0 using the uhci drivers. ? allows normal system usb 2.0 traffic in a system that may only have one usb port. ? debug port device (dpd) must be high-speed capable and connect directly to port #0 on ich8 systems (e.g., the dpd cannot be connected to port #0 through a hub). ? debug port fifo always makes forward progress (a bad status on usb is simply presented back to software). ? the debug port fifo is only given one usb access per microframe. the debug port facilitates operating system and device driver debug. it allows the software to communicate with an external console using a usb 2.0 connection. because the interface to this link does not go through the normal usb 2.0 stack, it allows communication with the external console during cases where the operating system is not loaded, the usb 2.0 software is broken, or where the usb 2.0 software is being debugged. specific features of this implementation of a debug port are: ? only works with an external usb 2.0 debug device (console) ? implemented for a specific port on the host controller ? operational anytime the port is not suspended and the host controller is in d0 power state. ? capability is interrupted when port is driving usb reset 5.19.10.1 theory of operation there are two operational modes for the usb debug port: 1. mode 1 is when the usb port is in a disabled state from the viewpoint of a standard host controller driver. in mode 1, the debu g port controller is required to generate a ?keepalive? packets less than 2 ms apart to keep the attached debug device from suspending. the keepalive packet should be a standalone 32-bit sync field. 2. mode 2 is when the host controller is running (i.e., host controller?s run/stop# bit is 1). in mode 2, the normal transmission of sof packets will keep the debug device from suspending. behavioral rules 1. in both modes 1 and 2, the debug port controller must check for software requested debug transactions at least every 125 microseconds. 2. if the debug port is enabled by the debu g driver, and the standard host controller driver resets the usb port, usb debug transa ctions are held off for the duration of the reset and until after the first sof is sent. 3. if the standard host controller driver suspends the usb port, then usb debug transactions are held off for the duration of the suspend/resume sequence and until after the first sof is sent. 4. the enabled_cnt bit in the debug register space is independent of the similar port control bit in the associated port status and control register. intel ? ich8 family datasheet 221 functional description table 87 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated port status and control register. table 87. debug port behavior owner_cnt enabled_ct port enable run / stop suspend debug port behavior 0 x x x x debug port is not being used. normal operation. 1 0 x x x debug port is not being used. normal operation. 1 1 0 0 x debug port in mode 1. sync keepalives sent plus debug traffic 1 1 0 1 x debug port in mode 2. sof (and only sof) is sent as keepalive. debug traffic is also sent. note that no other normal traffic is sent out this port, because the port is not enabled. 1 1 1 0 0 invalid. host controller driver should never put controller into this state (enabled, not running and not suspended). 1 1 1 0 1 port is suspended. no debug traffic sent. 1 1 1 1 0 debug port in mode 2. debug traffic is interspersed with normal traffic. 1 1 1 1 1 port is suspended. no debug traffic sent. functional description 222 intel ? ich8 family datasheet 5.19.10.1.1 out transactions an out transaction sends data to the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is set the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ? usb_address_cnf ? usb_endpoint_cnf ? data_buffer[63:0] ? token_pid_cnt[7:0] ? send_pid_cnt[15:8] ? data_len_cnt ? write_read#_cnt (note: this will always be 1 for out transactions) ? go_cnt (note: this will always be 1 to initiate the transaction) 2. the debug port controller sends a token packet consisting of: ? sync ? token_pid_cnt field ? usb_address_cnt field ? usb_endpoint_cnt field ? 5-bit crc field 3. after sending the token packet, the debug port controller sends a data packet consisting of: ? sync ? send_pid_cnt field ? the number of data bytes indicated in data_len_cnt from the data_buffer ? 16-bit crc note: a data_len_cnt value of 0 is valid in which case no data bytes would be included in the packet. 4. after sending the data packet, the contro ller waits for a handshake response from the debug device. ? if a handshake is received, the debug port controller: ? a. places the received pid in the received_pid_sts field ? b. resets the error_good#_sts bit ? c. sets the done_sts bit ? if no handshake pid is received, the debug port controller: ? a. sets the exception_sts field to 001b ? b. sets the error_good#_sts bit ? c. sets the done_sts bit intel ? ich8 family datasheet 223 functional description 5.19.10.1.2 in transactions an in transaction receives data from the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is reset the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ? usb_address_cnf ? usb_endpoint_cnf ? token_pid_cnt[7:0] ? data_len_cnt ? write_read#_cnt (note: this will always be 0 for in transactions) ? go_cnt (note: this will always be 1 to initiate the transaction) 2. the debug port controller sends a token packet consisting of: ? sync ? token_pid_cnt field ? usb_address_cnt field ? usb_endpoint_cnt field ? 5-bit crc field. 3. after sending the token packet, the debug port controller waits for a response from the debug device. if a response is received: ? the received pid is placed into the received_pid_sts field ? any subsequent bytes are pl aced into the data_buffer ? the data_len_cnt field is updated to show the number of bytes that were received after the pid. 4. if valid packet was received from the devi ce that was one byte in length (indicating it was a handshake packet), then the debug port controller: ? resets the error_good#_sts bit ? sets the done_sts bit 5. if valid packet was received from the devi ce that was more than one byte in length (indicating it was a data packet), then the debug port controller: ? transmits an ack handshake packet ? resets the error_good#_sts bit ? sets the done_sts bit 6. if no valid packet is received, then the debug port controller: ? sets the exception_sts field to 001b ? sets the error_good#_sts bit ? sets the done_sts bit. functional description 224 intel ? ich8 family datasheet 5.19.10.1.3 debug software enabling the debug port there are two mutually exclusive conditions that debug software must address as part of its startup processing: ? the ehci has been initialized by system software ? the ehci has not been initialized by system software debug software can determine the current ?ini tialized? state of the ehci by examining the configure flag in the ehci usb 2.0 command register. if this flag is set, then system software has initialized the ehci. ot herwise the ehci should not be considered initialized. debug software will initialize th e debug port registers depending on the state the ehci. however, before this can be accomplished, debug software must determine which root usb port is designated as the debug port. determining the debug port debug software can easily determine which usb root port has been designated as the debug port by examining bits 20:23 of the ehci host controller structural parameters register. this 4-bit field represents the numeric value assigned to the debug port (i.e., 0000=port 0). debug software startup with non-initialized ehci debug software can attempt to use the debug port if after setting the owner_cnt bit, the current connect status bit in the appropriate (see determining the debug port) portsc register is set. if the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. if a device is connected to the port, then debug software must reset/enable the port. debug software does this by setting and then clearing the port reset bit the portsc register. to assure a successful reset, debug software should wait at least 50 ms before clearing the port reset bit. due to possible delays, this bit may not change to 0 immediately; reset is complete when this bi t reads as 0. software must not continue until this bit reads 0. if a high-speed device is attached, the eh ci will automatically set the port enabled/ disabled bit in the portsc register and the debug software can proceed. debug software should set the enabled_cnt bit in the debug port control/status register, and then reset (clear) the port enabled/disabled bit in the portsc register (so that the system host controller driver does not see an enabled port when it is first loaded). debug software startup with initialized ehci debug software can attempt to use the debug port if the current connect status bit in the appropriate (see determining the debug port) portsc register is set. if the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. if a device is connected, then debug software must set the owner_cnt bit and then the enabled_cnt bit in the debug port control/status register. determining debug peripheral presence after enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. if all attempts result in an error (exception bits in the debug port control/status register indicates a transaction error), then the attached device is not a debug peripheral. if the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected. intel ? ich8 family datasheet 225 functional description 5.20 smbus controller (d31:f3) the ich8 provides an system management bus (smbus) 2.0 host controller as well as an smbus slave interface. the host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves). the ich8 is also capable of operating in a mode in which it can communicate with i 2 c compatible devices. the ich8 can perform smbus messages with either packet error checking (pec) enabled or disabled. the actual pec calculation and checking is performed in hardware by the ich8. the slave interface allows an external master to read from or write to the ich8. write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of variou s status bits. the ich8?s internal host controller cannot access the ich8?s internal slave interface. the ich8 smbus logic exists in device 31:f unction 3 configuration space, and consists of a transmit data path, and host controller. the transmit data path provides the data flow logic needed to implement the seven different smbus command protocols and is controlled by the host controller. the ich8 smbus controller logic is clocked by rtc clock. the smbus address resolution protocol (arp) is supported by using the existing host controller commands through software, except for the new host notify command (which is actually a received message). the programming model of the host controlle r is combined into two portions: a pci configuration portion, and a system i/o mapped portion. all static configuration, such as the i/o base address, is done via the pci configuration space. real-time programming of the host interface is done in system i/o space. the ich8 smbus host controller checks for pa rity errors as a target. if an error is detected, the detected parity error bit in the pci status register (device 31:function 3:offset 06h:bit 15) is set. if bit 6 and bit 8 of the pci command register (device 31:function 3:offset 04h) are set, an serr# is generated and the signaled serr# bit in the pci status register (bit 14) is set. note that the ich8 smbus controller may stop responding if an smbus device suddenly stops transmitting in the middle of a packet. this could result in unexpected system behavior, including a system hang. 5.20.1 host controller the smbus host controller is used to send commands to other smbus slave devices. software sets up the host controller with an address, command, and, for writes, data and optional pec; and then tells the controlle r to start. when the controller has finished transmitting data on writes, or receiving data on reads, it generates an smi# or interrupt, if enabled. the host controller supports 8 command protocols of the smbus interface (see system management bus (smbus) specification, version 2.0 ): quick command, send byte, receive byte, write byte/word, read byte/word, process call, block read/write, block write?block read process call, and host notify. the smbus host controller requires that the various data and command fields be setup for the type of command to be sent. when so ftware sets the start bit, the smbus host controller performs the requested transa ction, and interrupts the processor (or generates an smi#) when the transaction is completed. once a start command has been issued, the values of the ?active re gisters? (host control, host command, transmit slave address, data 0, data 1) should not be changed or read until the functional description 226 intel ? ich8 family datasheet interrupt status bit (intr) has been set (indicating the completion of the command). any register values needed for computation purposes should be saved prior to issuing of a new command, as the smbus host controller updates all registers while completing the new command. the ich8 supports the system management bus (smbus) specification, version 2.0 . slave functionality, including the host notify protocol, is available on the smbus pins. the smlink and smbus signals should not be tied together externally. using the smb host controller to send commands to the ich8?s smb slave port is not supported. 5.20.1.1 command protocols in all of the following commands, the host status register (offset 00h) is used to determine the progress of the command. wh ile the command is in operation, the host_busy bit is set. if the command completes successfully, the intr bit will be set in the host status register. if the device does not respond with an acknowledge, and the transaction times out, the dev_err bit is set. if software sets the kill bit in the host control register while the command is running, the transaction will stop and the failed bit will be set. quick command when programmed for a quick command, the transmit slave address register is sent. the pec byte is never append ed to the quick protocol. software should force the pec_en bit to 0 when performing the quick command. software must force the i2c_en bit to 0 when running this command. see section 5.5.1 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. send byte / receive byte for the send byte command, the transmit slave address and device command registers are sent. for the receive byte command, the transmit slave address register is sent. the data received is stored in the data0 register. software must force the i2c_en bit to 0 when running this command. the receive byte is similar to a send byte, the only difference is the direction of data transfer. see sections 5.5.2 and 5.5.3 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. write byte/word the first byte of a write byte/word access is the command code. the next 1 or 2 bytes are the data to be written. when programmed for a write byte/word command, the transmit slave address, device command, and data0 registers are sent. in addition, the data1 register is sent on a write word command. software must force the i2c_en bit to 0 when running this comm and. see section 5.5.4 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. read byte/word reading data is slightly more complicated than writing data. first the ich8 must write a command to the slave device. then it must follow that command with a repeated start condition to denote a read from that device 's address. the slave then returns 1 or 2 bytes of data. software must force the i2c_en bit to 0 when running this command. intel ? ich8 family datasheet 227 functional description when programmed for the read byte/word command, the transmit slave address and device command registers are sent. data is received into the data0 on the read byte, and the dat0 and data1 registers on the read word. see section 5.5.5 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. process call the process call is so named because a command sends data and waits for the slave to return a value dependent on that data. the pr otocol is simply a write word followed by a read word, but without a second command or stop condition. when programmed for the process call command, the ich8 transmits the transmit slave address, host command, data0 and data1 registers. data received from the device is stored in the data0 and data1 registers. the process call command with i2c_en set and the pec_en bit set produces undefined results. software must force either i2c_en or pec_en to 0 when runnin g this command. see section 5.5.6 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. note: for process call command, the value written into bit 0 of the transmit slave address register (smb i/o register, offset 04h) needs to be 0. note: if the i2c_en bit is set, the protocol sequence changes slightly: the command code (bits 18:11 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 19 in the sequence). block read/write the ich8 contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of the auxiliary control register at offset 0dh in i/o space, as opposed to a single byte of buffering. this 32-byte buffer is filled with write data before transmission, and filled with read data on reception. in the ich8, the interrupt is generated only after a transmission or recept ion of 32 bytes, or when the entire byte count has been transmitted/received. the byte count field is transmitted but ignored by the ich8 as software will end the transfer after all bytes it cares about have been sent or received. for a block write, software must either force the i2c_en bit or both the pec_en and aac bits to 0 when running this command. the block write begins with a slave addre ss and a write condition. after the command code the ich8 issues a byte count describ ing how many more bytes will follow in the message. if a slave had 20 bytes to send, th e first byte would be the number 20 (14h), followed by 20 bytes of data. the byte count may not be 0. a block read or write is allowed to transfer a maximum of 32 data bytes. when programmed for a block write command, the transmit slave address, device command, and data0 (count) registers are sent. data is then sent from the block data byte register; the total data sent being the value stored in the data0 register. on block read commands, the first byte received is stored in the data0 register, and the remaining bytes are stored in the block data byte register. see section 5.5.7 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. note: for block write, if the i2c_en bit is set, the format of the command changes slightly. the ich8 will still send the num ber of bytes (on writes) or receive the number of bytes (on reads) indicated in the data0 register. however, it will not send the contents of the data0 register as part of the message. also, the block write protocol sequence functional description 228 intel ? ich8 family datasheet changes slightly: the byte count (bits 27:20 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 28 in the sequence). i 2 c read this command allows the ich8 to perform block reads to certain i 2 c devices, such as serial e 2 proms. the smbus block read supports the 7-bit addressing mode only. however, this does not allow access to devices using the i 2 c ?combined format? that has data bytes after the address. typically these data bytes correspond to an offset (address) within the serial memory chips. note: this command is supported independent of the setting of the i2c_en bit. the i 2 c read command with the pec_en bit set produces undefined results. software must force both the pec_en and aac bit to 0 when running this command. for i 2 c read command, the value written into bit 0 of the transmit slave address register (smb i/o register, offset 04h) needs to be 0. the format that is used for the command is shown in table 88 . the ich8 will continue reading data from the peripheral until the nak is received. table 88. i 2 c block read bit description 1 start 8:2 slave address ? 7 bits 9 write 10 acknowledge from slave 18:11 send data1 register 19 acknowledge from slave 20 repeated start 27:21 slave address ? 7 bits 28 read 29 acknowledge from slave 37:30 data byte 1 from slave ? 8 bits 38 acknowledge 46:39 data byte 2 from slave ? 8 bits 47 acknowledge ? data bytes from slave / acknowledge ? data byte n from slave ? 8 bits ? not acknowledge ? stop intel ? ich8 family datasheet 229 functional description block write?block read process call the block write-block read process call is a two-part message. the call begins with a slave address and a write condition. after the command code the host issues a write byte count (m) that describes how many more bytes will be written in the first part of the message. if a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. the write byte count (m) cannot be 0. the second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a re ad bit. the next byte is the read byte count (n), which may differ from the write byte count (m). the read byte count (n) cannot be 0. the combined data payload must not exceed 32 bytes. the byte leng th restrictions of this process call are summarized as follows: ? m 1 byte ? n 1 byte ? m + n 32 bytes the read byte count does not include the pe c byte. the pec is computed on the total message beginning with the first slav e address and using the normal pec computational rules. it is highly recommende d that a pec byte be used with the block write-block read process call. software mu st do a read to the command register (offset 2h) to reset the 32 byte buffer pointe r prior to reading the block data register. note that there is no stop condition before the repeated start condition, and that a nack signifies the end of the read transfer. note: e32b bit in the auxiliary control register must be set when using this protocol. see section 5.5.8 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. 5.20.2 bus arbitration several masters may attempt to get on the bus at the same time by driving the smbdata line low to signal a start conditio n. the ich8 continuously monitors the smbdata line. when the ich8 is attempting to drive the bus to a 1 by letting go of the smbdata line, and it samples smbdata low, th en some other master is driving the bus and the ich8 will stop transferring data. if the ich8 sees that it has lost arbitratio n, the condition is called a collision. the ich8 will set the bus_err bit in the host status register, and if enabled, generate an interrupt or smi#. the processor is responsible for restarting the transaction. when the ich8 is a smbus master, it driv es the clock. when the ich8 is sending address or command as an smbus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. it will not start toggling the clock until the start or stop condition meets proper setup and hold time. the ich8 will also assure minimum time between smbus transactions as a master. note: the ich8 supports the same arbitration protocol for both the smbus and the system management (smlink) interfaces. functional description 230 intel ? ich8 family datasheet 5.20.3 bus timing 5.20.3.1 clock stretching some devices may not be able to handle thei r clock toggling at the rate that the ich8 as an smbus master would like. they have the capability of stretching the low time of the clock. when the ich8 attempts to releas e the clock (allowing the clock to go high), the clock will remain low for an extended period of time. the ich8 monitors the smbus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. while the bus is still low, the high time counter must not be enabled. simila rly, the low period of the clock can be stretched by a smbus master if it is not ready to send or receive data. 5.20.3.2 bus time out (intel ? ich8 as smbus master) if there is an error in the transaction, such that an smbus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. the ich8 will discard the cy cle and set the dev_err bit. the time out minimum is 25 ms (800 rtc clocks). the time-out counter inside the ich8 will start after the last bit of data is transferred by the ich8 and it is waiting for a response. the 25 ms timeout counter will not co unt under the following conditions: 1. byte_done_status bit (smbus i/o offset 00h, bit 7) is set 2. the second_to_sts bit (tco i/o offset 06h, bit 1) is not set (this indicates that the system has not locked up). 5.20.4 interrupts / smi# the ich8 smbus controller uses pirqb# as its interrupt pin. however, the system can alternatively be set up to generate smi# instead of an interrupt, by setting the smbus_smi_en bit (device 31:function 0:offset 40h:bit 1). table 90 and table 91 specify how the various enable bi ts in the smbus function control the generation of the interrupt, host and slave smi, and wake internal signals. the rows in the tables are additive, which means that if more than one row is true for a particular scenario then the results for all of the activated rows will occur. intel ? ich8 family datasheet 231 functional description table 89. enable for smbalert# event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit 1) smbalert_dis (slave command i/o register, offset 11h, bit 2) result smbalert# asserted low (always reported in host status register, bit 5) x x x wake generated x 1 0 slave smi# generated (smbus_smi_sts) 1 0 0 interrupt generated table 90. enables for smbus slave write and smbus host events event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit1) event slave write to wake/ smi# command x x wake generated when asleep. slave smi# generated when awake (smbus_smi_sts). slave write to smlink_slave_smi command x x slave smi# generated when in the s0 state (smbus_smi_sts) any combination of host status register [4:1] asserted 0 x none 1 0 interrupt generated 1 1 host smi# generated table 91. enables for the host notify command host_notify_intren (slave control i/o register, offset 11h, bit 0) smb_smi_en (host config register, d31:f3:off40h, bit 1) host_notify_wken (slave control i/o register, offset 11h, bit 1) result 0 x 0 none x x 1 wake generated 1 0 x interrupt generated 1 1 x slave smi# generated (smbus_smi_sts) functional description 232 intel ? ich8 family datasheet 5.20.5 smbalert# smbalert# is multiplexed with gpio[11]. when enable and the signal is asserted, the ich8 can generate an interrupt, an smi#, or a wake event from s1?s5. 5.20.6 smbus crc gene ration and checking if the aac bit is set in the auxiliary control register, the ich8 automatically calculates and drives crc at the end of the transmitte d packet for write cycles, and will check the crc for read cycles. it will not transmit the contents of the pec register for crc. the pec bit must not be set in the host control re gister if this bit is set, or unspecified behavior will result. if the read cycle results in a crc error, the dev_err bit and the crce bit in the auxiliary status register at offset 0ch will be set. 5.20.7 smbus slave interface the ich8?s smbus slave interface is accesse d via the smbus. the smbus slave logic will not generate or handle receiving the pec by te and will only act as a legacy alerting protocol device. the slave interface allows the ich8 to decode cycles, and allows an external microcontroller to perform specif ic actions. key features and capabilities include: ? supports decode of three types of messages: byte write, byte read, and host notify. ? receive slave address register: this is the address that the ich8 decodes. a default value is provided so that the slave interface can be used without the processor having to program this register. ? receive slave data register in the smbus i/o space that includes the data written by the external microcontroller. ? registers that the external microcontrolle r can read to get the state of the ich8. ? status bits to indicate that the smbus sl ave logic caused an interrupt or smi# due to the reception of a message that matched the slave address. ? bit 0 of the slave status register for the host notify command ? bit 16 of the smi status register ( section 9.8.3.15 ) for all others note: the external microcontroller should not atte mpt to access the intel ich8?s smbus slave logic until either: ? 800 milliseconds after both: rtcrst## is high and rsmrst# is high, or ? the pltrst# de-asserts ? the 800 ms case is based on the scenario where the rtc battery is dead or missing such that the rtc power well comes up simultaneously with suspend well. in this case, the rtc clock may ta ke a while to stabilize. the ich8 uses the rtc clock to extend the internal rsmrst# by ~100 ms. therefore, if the clock is slow to toggle, this time could be extended. 800 ms is assumed to be sufficient guardband for this. if a master leaves the clock and data bits of the smbus interface at 1 for 50 s or more in the middle of a cycle, the ich8 slave logi c's behavior is undefined. this is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. note: when an external microcontroller accesses the smbus slave interface over the smbus a translation in the address is needed to accommodate the least significant bit used for read/write control. for example, if the ich8 slave address (rcv_slva) is left at 44h (default), the external micro controller woul d use an address of 88h/89h (write/read). intel ? ich8 family datasheet 233 functional description 5.20.7.1 format of slave write cycle the external master performs byte write co mmands to the ich8 smbus slave i/f. the ?command? field (bits 11:18) indicate which register is being accessed. the data field (bits 20:27) indicate the value that should be written to that register. note: if the ich8 is sent a ?hard reset without cycling? command on smbus while the system is in s4 or s5, the reset command and any other write commands accepted by the ich8 smbus will not be executed until the next wake event. smbus write commands that are accepted by the ich8 are not lost, but completion occurs after the next system wake event. this also applies to any sm bus wake commands accepted after a ?hard reset without cycling? command, such that the smbus wake command will not cause the system to wake. any smbus read that is accepted by the ich8 will complete normally. intel? active management technology is not impacted as intel amt does not use the hard reset without cycling command while the system is in s4 or s5. table 92 has the values associated with the registers. note: the external microcontroller is responsible to make sure th at it does not update the contents of the data byte registers until they have been read by the system processor. the ich8 overwrites the old value with any new value received. a race condition is possible where the new value is being written to the regist er just at the time it is being read. ich8 will not attempt to cover this race condition (i.e., unpredictable results in this case). table 92. slave write registers register function 0 command register. see table 93 below for valid values wr itten to this register. 1?3 reserved 4 data message byte 0 5 data message byte 1 6?7 reserved 8 reserved 9?ffh reserved functional description 234 intel ? ich8 family datasheet . table 93. command types command type description 0 reserved 1 wake/smi#. this command wakes the system if it is not already awake. if system is already awake, an smi# is generated. note: the smb_wak_sts bit will be set by this command, even if the system is already awake. the smi handler should then clear this bit. 2 unconditional powerdown. this command sets the pwrbtnor_sts bit, and has the same effect as the po werbutton override occurring. 3 hard reset without cycling: this command causes a hard reset of the system (does not include cycling of the power supply). this is equivalent to a write to the cf9h register with bits 2:1 set to 1, but bit 3 set to 0. 4 hard reset system. this command causes a hard reset of the system (including cycling of the power supply). th is is equivalent to a write to the cf9h register with bits 3:1 set to 1. 5 disable the tco messages. this command will disable the intel ? ich8 from sending heartbeat and event messages (as described in section 5.15 ). once this command has been executed, heartbeat an d event message reporting can only be re-enabled by assertion and deas sertion of the rsmrst# signal. 6 wd reload: reload watchdog timer. 7 reserved 8 smlink_slv_smi. when ich8 detects this command type while in the s0 state, it sets the smlink_slv_smi_sts bit (see section 9.9.5 ). this command should only be used if the system is in an s0 state. if the me ssage is received during s1? s5 states, the ich8 acknowledges it, bu t the smlink_slv_smi_sts bit does not get set. note: it is possible that the system transitions out of the s0 state at the same time that the smlink_slv_smi command is received. in this case, the smlink_slv_smi_sts bit may get set bu t not serviced before the system goes to sleep. once the system returns to s0, the smi associated with this bit would then be generated. software mu st be able to handle this scenario. 9?ffh reserved intel ? ich8 family datasheet 235 functional description 5.20.7.2 format of read command the external master performs byte read commands to the ich8 smbus slave i/f. the ?command? field (bits 18:11) indicate which register is being accessed. the data field (bits 30:37) contain the value that should be read from that register. table 94. slave read cycle format bit description driven by: comment: 1 start external microcontroller 2?8 slave address - 7 bits external microcontroller must match value in receive slave address register. 9 write external microcontroller always 0 10 ack intel ich8 11?18 command code ? 8 bits external microcontroller indicates which register is being accessed. see table 95 below for list of implemented registers. 19 ack intel ich8 20 repeated start external microcontroller 21?27 slave address - 7 bits external microcontroller must match value in receive slave address register 28 read external microcontroller always 1 29 ack intel ich8 30?37 data byte intel ich8 value depends on register being accessed. table 95 below for list of implemented registers. 38 not ack external microcontroller 39 stop external microcontroller table 95. data values for slave read registers (sheet 1 of 2) register bits description 0 7:0 reserved for capabilities indication. sh ould always return 00h. future chips may return another value to in dicate different capabilities. 1 2:0 system power state 000 = s0 001 = s1 010 = reserved 011 = s3 100 = s4 101 = s5 110 = reserved 111 = reserved 7:3 reserved 2 3:0 reserved 7:4 reserved 3 5:0 watchdog timer current value. note that watchdog timer has 10 bits, but this field is only 6 bits. if the cu rrent value is greater than 3fh, ich8 will always report 3fh in this field. 7:6 reserved 4 0 1 = the intruder detect (intrd_det) bit is set. this indicates that the system cover has probably been opened. 1 1 = bti temperature event occurred. this bit will be set if the intel ich8?s thrm# input signal is active. functional description 236 intel ? ich8 family datasheet 5.20.7.2.1 behavioral notes according to smbus protocol, read and write messages always begin with a start bit ? address? write bit sequence. when the ich8 detects that the address matches the value in the receive slave address register, it will assume that the protocol is always followed and ignore the write bit (bit 9) and signal an acknowledge during bit 10. in other words, if a start ?address?read occurs (which is invalid for smbus read or write protocol), and the address matches the ich8 ?s slave address, the ich8 will still grab the cycle. 2 doa cpu status . this bit will be 1 to indica te that the processor is dead 3 1 = second_to_sts bit set. this bit will be set after the second time-out (second_to_sts bit) of th e watchdog timer occurs. 6:4 reserved. will always be 0, but software should ignore. 7 reflects the value of the gpi[11]/smbalert# pin (and is dependent upon the value of the gpi_inv[11] bit. if the gpi_inv[11] bit is 1, then the value in this bit equals the level of the gpi[11]/smbalert# pin (high = 1, low = 0). if the gpi_inv[11] bit is 0, then the value of this bit will equal the inverse of the level of the gpi[11]/smbalert# pin (high = 0, low = 1). 5 0 fwh bad bit. this bit will be 1 to indicate that the fwh read returned ffh, which indicates that it is probably blank. 1 battery low status. ?1? if the batlow# pin is a ?0?. 2 cpu power failure status: ?1? if the cpupwr_flr bit in the gen_pmcon_2 register is set. 3 init# due to receiving shutdown message: this event is visible from the reception of the shutdown message un til a platform reset is done if the shutdown policy select bit (sps) is configured to drive init#. when the sps bit is configured to generate pltr st# based on shutdown, this register bit will always return 0. events on signal will not create a event message 5 power_ok_bad: indicates the failure core po wer well ramp during boot/ resume. this bit will be active if the slp_s3# pin is de-asserted and pwrok pin is not asserted. 6 thermal trip: this bit will shadow the state of cpu thermal trip status bit (cts) (16.2.1.2, gen_pmcon_2, bit 3). events on signal will not create a event message 7 reserved: default value is ?x? note: software should not expect a consis tent value when this bit is read through smbus/smlink 6 7:0 contents of the message 1 register. see section 9.9.8 for the description of this register. 7 7:0 contents of the message 2 register. see section 9.9.8 for the description of this register. 8 7:0 contents of the wdstatus register. see section 9.9.9 for the description of this register. 9 ? ffh 7:0 reserved table 95. data values for slave read registers (sheet 2 of 2) register bits description intel ? ich8 family datasheet 237 functional description also according to smbus protocol, a read cycle contains a repeated start?address? read sequence beginning at bit 20. once again, if the address matches the ich8?s receive slave address, it will assume that th e protocol is followed, ignore bit 28, and proceed with the slave read cycle. note: an external microcontroller must not attempt to access the ich8?s smbus slave logic until at least 1 second after both rtcrst# and rsmrst# are deasserted (high). 5.20.7.3 format of host notify command the ich8 tracks and responds to the standard host notify command as specified in the system management bus (smbus) specification, version 2.0. the host address for this command is fixed to 0001000b. if the ich8 already has data for a previously-received host notify command which has not been serviced yet by the host software (as indicated by the host_notify_sts bit), then it will nack following the host address byte of the protocol. this allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. note: host software must always clear the host_notify_sts bit after completing any necessary reads of the address and data registers. table 96 shows the host notify format. table 96. host notify format bit description driven by comment 1 start external master 8:2 smb host address ? 7 bits external master always 0001_000 9 write external master always 0 10 ack (or nack) intel ? ich8 ich8 nacks if host_notify_sts is 1 17:11 device address ? 7 bits external master indicates the address of the master; loaded into the notify device address register 18 unused ? always 0 external master 7-bit-only address; this bit is inserted to complete the byte 19 ack ich8 27:20 data byte low ? 8 bits external master loaded into the notify data low byte register 28 ack ich8 36:29 data byte high ? 8 bits external master loaded into the notify data high byte register 37 ack ich8 38 stop external master functional description 238 intel ? ich8 family datasheet 5.21 intel ? high definition audio overview the ich8?s controller communicates with the external codec(s) over the intel high definition audio serial link. the controller consists of a set of dma engines that are used to move samples of digitally enco ded data between system memory and an external codec(s). the ich8 implements four output dma engines and 4 input dma engines. the output dma engines move digi tal data from system memory to a d-a converter in a codec. ich8 implements a single serial data output signal (hda_sdout) that is connected to all exte rnal codecs. the input dma engines move digital data from the a-d converter in the codec to system memory. the ich8 implements four serial digital input sign als (hda_sdi[3:0]) supporting up to four codecs. audio software renders outbound and processes inbound data to/from buffers in system memory. the location of individual buffers is described by a buffer descriptor list (bdl) that is fetched and processed by the controller. the data in the buffers is arranged in a predefined format. the output dma engines fetch the digital data from memory and reformat it based on the programmed sample rate, bit/sample and number of channels. the data from the ou tput dma engines is then combined and serially sent to the external codecs over th e intel high definition audio link. the input dma engines receive data from the codecs over the intel high definition audio link and format the data based on the programmable attributes for that stream. the data is then written to memory in the predefined format for software to process. each dma engine moves one stream of data. a single codec can accept or generate multiple streams of data, one for each a-d or d-a converter in the codec. multiple codecs can accept the same output stream processed by a single dma engine. codec commands and responses are also tran sported to and from the codecs via dma engines. 5.21.1 intel ? high definition audio docking (mobile only) 5.21.1.1 dock sequence note that this sequence is followed when the system is running and a docking event occurs. 1. since the ich8 supports docking, the do cking supported (dcksts. ds) bit defaults to a 1. post bios and acpi bios software uses this bit to determine if the hd audio controller supports docking. bios may write a 0 to this rwo bit during post to effectively turn off the docking feature. 2. after reset in the undocked quiescent stat e, the dock attach (dckctl.da) bit and the dock mate (dcksts.dm) bit are both de-asserted. the hda_dock_en# signal is de-asserted and hda_dock_rst# is asserted. bclk, sync and sdo signals may or may no be running at the point in time that the docking event occurs. 3. the physical docking event is signaled to acpi bios software via acpi control methods. this is normally done through a gpio signal on the ich8 and is outside the scope of this section of the specification. 4. acpi bios software first checks that the docking is supported via dcksts.ds=1 and that the dcksts.dm=0 and then initia tes the docking sequence by writing a 1 to the dckctl.da bit. 5. the hd audio controller then asserts the hda_dock_en# signal so that the bclk signal begins toggling to the dock co dec. hda_dock_en# shall be asserted synchronously to bclk and timed such that bclk is low, sync is low, and sdo is low. pull-down resistors on these signals in the docking station discharge the signals low so that when the state of the si gnal on both sides of the switch is the same when the switch is turned on. this reduces the potential for charge coupling intel ? ich8 family datasheet 239 functional description glitches on these signals. note that in the ich8 the first 8 bits of the command field are ?reserved? and always driven to 0s. this creates a predictable point in time to always assert hda_dock_en#. note that th e hd audio link reset exit specification that requires that sync and sdo be driven low during bclk startup is not assured. note also that the sdo and bclk sign als may not be low while hda_dock_rst# is asserted which also violates the spec. 6. after the controller asserts hda_dock_en# it waits for a minimum of 2400 bclks (100 us) and then de-asserts hda_dock_rst#. this is done in such a way to meet the hd audio link reset exit spec ification. hda_dock_rst# de-assertion should be synchronous to bclk and timed such that there are least 4 full bclks from the de-assertion of hda_dock_rst# to the first frame sync assertion. 7. the connect/turnaround/address frame hard ware initialization sequence will now occur on the dock codecs' sdi signals. a dock codec is detected when sdi is high on the last bclk cycle of the frame sy nc of a connect frame. the appropriate bit(s) in the state change status (statest s) register will be set. the turnaround and address frame initialization sequence th en occurs on the dock codecs' sdi(s). 8. after this hardware initialization sequence is complete (approximately 32 frames), the controller hardware sets the dcksts.dm bi t to 1 indicating that the dock is now mated. acpi bios polls the dcksts.dm bit and when it detects it is set to 1, conveys this to the os through a plug-n-play irp. this eventually invokes the hd audio bus driver, which then begins it's codec discovery, enumeration, and configuration process. 9. alternatively to step #8, the hd audi o bus driver may choose to enable an interrupt by setting the wakeen bits for sdins that didn't originally have codecs attached to them. when a corresponding st atests bit gets set an interrupt will be generated. in this case the hd audio bus dr iver is called directly by this interrupt instead of being notified by the plug-n-play irp. 10. hd audio bus driver software ?discovers? the dock codecs by comparing the bits now set in the statests register with the bits that were set prior to the docking event. 5.21.1.2 exiting d3/crst# when docked 1. in d3/crst#, crst# is asserted by the hd audio bus driver. crst# asserted resets the dock state machines, but does not reset the dckctl.da bit. because the dock state machines are reset, the dock is electrically isolated (hda_dock_en# de-asserted) and dock_rst# is asserted. 2. the bus driver clears the statests bits, then de-asserts crst#, waits approximately 7ms, then checks the statests bits to see which codecs are present. 3. when crst# is de-asserted, the dock st ate machine detects that dckctl.da is still set and the controller hardware sequences through steps to electrically connect the dock by asserting hda_dock_en# and then eventually de-asserts dock_rst#. this completes within the 7 ms mentioned in step 2). 4. the bus driver enumerates the codecs present as indicated via the statests bits. 5. note that this process did not require bi os or acpi bios to set the dckctl.da bit. functional description 240 intel ? ich8 family datasheet 5.21.1.3 cold boot/resume from s3 when docked 1. when booting and resuming from s3, pltrst# switches from asserted to de- asserted. this clears the dckctl.da bit and the dock state machines. because the dock state machines are reset, the dock is electrically isolated (hda_dock_en# de-asserted) and dock_rst# is asserted. 2. post bios detects that the dock is attach ed and sets the dckctl.da bit to 1. note that at this point crst# is still asserted so the dock state machine will remain in it's reset state. 3. the bus driver clears the statests bits, then de-asserts crst#, waits approximately 7ms, then checks the statests bits to see which codecs are present. 4. when crst# is de-asserted, the dock st ate machine detects that dckctl.da is still set and the controller hardware sequences through steps to electrically connect the dock by asserting hda_dock_en# and then eventually de-asserts dock_rst#. this completes within the 7ms mentioned in step 3). 5. the bus driver enumerates the codecs present as indicated via the statests bits. 5.21.1.4 undock sequence there are two possible undocking scenarios. the first is the one that is initiated by the user that invokes software and gracefully shuts down the dock codecs before they are undocked. the second is referred to as th e ?surprise undock? where the user undocks while the dock codec is running. both of these situations appear the same to the controller as it is not cognizant of the ?surprise removal?. but both sequences will be discussed here. 5.21.1.4.1 normal undock 1. in the docked quiescent state, the dock attach (dckctl.da) bit and the dock mate (dcksts.dm) bit are both asserted. the hda_dock_en# signal is asserted and hda_dock_rst# is de-asserted. 2. the user initiates an undock event th rough the gui interface or by pushing a button. this mechanism is outside the scope of this section of the document. either way acpi bios software will be invoked to manage the undock process. 3. acpi bios will call the hd au dio bus driver software in order to halt the stream to the dock codec(s) prior to electrical undocking. if the hd audio bus driver is not capable of halting the stream to the dock ed codec, acpi bios will initiate the hardware undocking sequence as described in the next step while the dock stream is still running. from this standpoint, the result is similar to the ?surprise undock? scenario where an audio glitch may occur to the docked codec(s) during the undock process. 4. the acpi bios initiates the hardware und ocking sequence by writing a 0 to the dckctl.da bit. 5. the hd audio controller asserts hda_dock_rst#. hda_dock_rst# assertion shall be synchronous to bclk. there are no other timing requirements for hda_dock_rst# assertion. note that the hd audio link reset specification requirement that the last frame sync be skipped will not be met. 6. a minimum of 4 bclks after hda_dock_rst# the controller will de-assert hda_dock_en# to isolate the dock code c signals from the ich8 hd audio link signals. hda_dock_en# is de-asserted synchronously to bclk and timed such that bclk, sync, and sdo are low. 7. after this hardware undocking sequence is complete, the controller hardware clears the dcksts.dm bit to 0 indicating that the dock is now un-mated. acpi bios software polls dcksts.dm and when it sees dm set, conveys to the end user that physical undocking can proceed. the controller is now ready for a subsequent docking event. intel ? ich8 family datasheet 241 functional description 5.21.1.4.2 surprise undock 1. in the surprise undock case the user undocks before software has had the opportunity to gracefully halt the stream to the dock codec and initiate the hardware undock sequence. 2. a signal on the docking connector is connec ted to the switch that isolates the dock codec signals from the ich8 hd audio link signals (dock_det# in the conceptual diagram). when the undock event begins to occur the switch will be put into isolate mode. 3. the undock event is communicated to the acpi bios via acpi control methods that are outside the scope of this section of the document. 4. acpi bios software writes a 0 to the dckctl.da bit. acpi bios then calls the hd audio bus driver via plug-n-play irp. the bus driver then posthumously cleans up the dock codec stream. 5. the hd audio controller hardware is obliv ious to the fact that a surprise undock occurred. the flow from this point on is identical to the normal undocking sequence described in section 0 starting at step 3). it finishes with the hardware clearing the dcksts.dm bit set to 0 indicating that the dock is now un-mated. the controller is now ready for a subsequent docking event. 5.21.1.5 interaction between dock/undock and power management states when exiting from s3, pltrst# will be asse rted. the post bios is responsible for initiating the docking sequence if the dock is already attached when pltrst# is de- asserted. post bios writes a 1 to the dckctl.da bit prior to the hd audio driver de- asserting crts# and detecting and enum erating the codecs attached to the hda_dock_rst# signal. the hd audio controlle r does not directly monitor a hardware signal indicating that a dock is attached. therefore a method outside the scope of this document must be used to cause the post bios to initiate the docking sequence. when exiting from d3, crst# will be assert ed. when crst# bit is ?0? (asserted), the dckctl.da bit is not cleared. the dock state machine will be reset such that hda_dock_en# will be de-asserted, hda_ dock_rst# will be asserted and the dcksts.dm bit will be cleared to reflect this state. when the crst# bit is de-asserted, the dock state machine will detect that dckctl.da is set to ?1? and will begin sequencing through the dock process. note that this does not require any software intervention. 5.21.1.6 relationship between hda_dock_rst# and hda_rst# hda_rst# will be asserted when a pltrst# occurs or when the crst# bit is 0. as long as hda_rst# is asserted, the do ck_rst# signal will also be asserted. when pltrst# is asserted, the dckctl.da and dcksts.dm bits will be get cleared to their default state (0's), and the dock state machine will be reset such that hda_dock_en# will be de-ass erted, and hda_dock_rst# w ill be asserted. after any pltrst#, post bios software is responsible for detecting that a dock is attached and then writing a ?1? to the dckctl.da bit prior to the hd audio bus driver de-asserting crst#. when crst# bit is ?0? (asserted), the dckc tl.da bit is not cleared. the dock state machine will be reset such that hd a_dock_en# will be de-asserted, hda_dock_rst# will be asserted and the dcks ts.dm bit will be cleared to reflect this state. when the crst# bit is de-asserted, the dock state machine will detect that dckctl.da is set to ?1? and will begin sequen cing through the dock process. note that this does not require any software intervention. functional description 242 intel ? ich8 family datasheet 5.22 intel ? active management technology (intel ? amt) (intel ? ich8do and ich8m-e only)) intel active management technology is a set of advanced manageability features developed as a direct result of it custom er feedback gained through intel market research. reducing the total cost of ownership (tco) through improved asset tracking, remote manageability, and fewer desk-side visi ts were identified as key it priorities. intel amt extends the capabilities of existi ng management solutions by making the asset information, remote diagnostics, recovery and contain capabilities always available, or out of band (oob), even when the system is in a low-power ?off? state or the os is hung. another technology feature of intel active technology is system defense. system defense is a intel amt feature that is us ed to stop the propagation of worms and viruses. programmable packet filters in th e integrated lan controller are used to accomplish this. these filters inspect all inco ming and all outgoing packets and decide whether to block or pass the packets as configured. there is no indication to the host that a packet has been blocked or accepted. the logic can be used to accept or block reception to host or transmission to network paths. additionally, counter logic can be used to count the number or filter matches for a given filter. this feature allows for statistical sampling of connections as well as rate limiting of connections. 5.22.1 intel ? amt features ? e-asset tag ? oob hw and sw inventory logs ? oob alerts ? ide redirect ? serial over lan for remote control ? remote diagnostics execution ? os lock-up alert ? os repair ? remote bios recovery and update 5.22.2 intel ? amt requirements intel amt is a platform-level solution that utilizes multiple system components including: ? intel amt-ready ich8 component ? intel gigabit ethernet phy (intel ? 82566 gigabit platform lan connect device) with intel ? active management technology for remote access ? spi flash memory with 4 kb sector erase that meets requirements set in section 5.23.2.2 (16 mb minimum for intel amt 2.0 (desktop only) and 32-mb minimum for intel amt 2.5 (mobile only) to store asset information, management software code, and logs ? bios to provide asset detection and post diagnostics (bios and intel amt can optionally share same flash memory device) ? familiar isv software packages to take advantage of intel amt?s platform management capabilities intel ? ich8 family datasheet 243 functional description 5.23 serial peripheral interface (spi) the serial peripheral interface (spi) is a 4-pin interface that provides a potentially lower-cost alternative for system flash versus the firmware hub on the lpc bus. the 4-pin spi interface consists of clock (c lk), master data out (master out slave in (mosi)), master data in (master in slave out (miso)) and an active low chip select (cs#). the ich8 supports two spi flash devices usin g two separate chip select pins. each spi flash device can be up to 16 mbytes. the ich8 spi interface supports 20 mhz and 33 mhz spi devices. communication on the spi bus is done with a master ? slave protocol. the slave is connected to the ich8 and is implemented as a tri-state bus. note: when spi is selected by the boot bios dest ination strap and a spi device is detected by the ich8, lpc based bios flash is disabled. 5.23.1 spi supported feature overview spi flash on the ich8 has two operational modes, descriptor and non-descriptor. non- descriptor mode is similar to flash functionality of intel ? ich7. in this mode, spi flash can only be used for bios. direct read an d writes are not supported. bios has read/ write access only through register accesses. through those register accesses bios can read and write to the entire flash without secu rity checking. there is also no support for the integrated gbe, manageability engine, chipset soft straps, as well multiple spi flash components. descriptor mode enables many new features of the chipset ? integrated gbe and host cpu for gbe software ? intel active management technology (ich8do and ich8m-e only) ? intel ? quiet system technology (desktop only) ? supports two spi flash components us ing two separate chip select pins ? hardware enforced security restricting master accesses to different regions ? chipset soft strap region provides the ability to use flash nvm as an alternative to hardware pull-up/pull-down resistors for both ich and mch ? supports the spi fast read instruction and frequencies of 33 mhz ? uses standardized flash instruction set in descriptor mode the flash is divided into four separate regions: only three masters can access the four regions: host cpu running bios code, integrated gbe and host cpu running gbe software, and me. the flash descriptor is requires one 4kb block/sector. the integr ated gbe needs two 4kb blocks/sectors. bios and the manageability engine (me) are the other two regions. the only required region is region 0, the flash descriptor. region 0 must be located in the first sector of component 0 (offset 0). region content 0 flash descriptor 1 bios 2 me 3 gbe functional description 244 intel ? ich8 family datasheet 5.23.1.1 flash descriptor the maximum size of the flash descriptor is one 4kb block. the information stored in the flash descriptor can only be written duri ng the manufacturing process as its read/ write permissions must be set to read only when the computer leaves the manufacturing floor. the flash descriptor is broken up into six sections: the flash signature as mentioned before is what selects descriptor mode as well as verifying if the flash is programmed and f unctioning. the data at the bottom of the flash (offset 0) must be 0ff0a55ah in order to be in descriptor mode. the descriptor map has pointers to the other six descriptor sections as well as the size of each. the component section has information about the spi flash in the system. it has number of components, density of each, invalid instruct ions (such as chip erase), and frequencies for read, fast read and write/erase instructio ns. the region section points to the three other regions as well as the size of each region. the master region contains the security settings for the flash, granting read/write permissions for each region and identifying each master. the mch and ich chipset soft strap sections contain mch and ich configurable parameters. the reserved for ch ipset future uses region between the top of the mch strap section and the bottom of th e vscc table is reserved for future uses or growth of the existing sections by th e chipset. the descriptor upper map is 256b below the 4kb boundary of the descriptor. th is determines the length and base address of the vscc table. the vscc table holds th e jedec id and the vscc information of all the spi flash supported by that nvm imag e. the jedec and vscc information is necessary to allow devices that meet the compatibility requirements in section 5.23.2.2 to work with intel ? amt, asf, and/or intel ? quiet technology. 256b is reserved at the top of the flash descriptor for use by oem. figure 17. flash descriptor component descriptor map signature region master ich soft straps mch soft straps 0 4kb 256b oem section reserved for chipset future uses descriptor upper map vscc table intel ? ich8 family datasheet 245 functional description 5.23.1.2 flash access there are two types of flash accesses: direct access: ? masters are allowed to do direct read only of their primary region ? gbe region can only be directly accessed by the gbe controller. gbe software must use program registers to access the gbe region. ? master's host or me virtual read address is converted into the spi flash linear address (fla) using the flash descriptor region base/limit registers program register access: ? program register accesses are not allowed to cross a 4kb boundary and can not issue a command that might extend across two componen ts ? software programs the fla corresponding to the region desired ? software must read the devices pri mary region base/limit address to create a fla. 5.23.1.3 program register software sequencing ? supported in descriptor and non-descriptor mode ? software has full control over the spi op codes and transactions ? same behavior as ich7 ? additional registers such as spi cycl e frequency and fast read have been added in ich8 ? primary use of software sequencing is wh en using non-standard instructions and as a backup to hardware sequencing. 5.23.1.4 direct access security ? "requester id of the device must match that of the primary requester id in the master section ? "calculated flash linear address must fall between primary region base/limit ? "direct write not allowed ? "direct read cache contents are reset to 0's on a read from a different master ? supports the same cache flush mechanism in ich7 which includes program register writes 5.23.1.5 register access security ? only primary region masters can access the registers note: processor running gbe software can access gbe registers ? masters are only allowed to read or wr ite those regions they have read/write permission ? using the flash region access permissions, one master can give another master read/write permissions to their area ? using the five protected range registers, each master can add separate read/write protection above that granted in the flash descriptor for their own accesses ? example: bios may want to protect different regions of bios from being erased ? ranges can extend across region boundaries functional description 246 intel ? ich8 family datasheet 5.23.2 spi device comp atibility requirements a variety of spi flash devices exist in the market. in order for a spi device to be compatible with the ich8 it must meet the minimum requirements detailed in the following sections. 5.23.2.1 device requirements for system bios storage only a serial flash device must meet the following minimum requirements when used explicitly for system bios storage. ? erase size capability of at least one of the following: 64 kbytes, 4 kbytes, or 256 bytes. ? if two serial flash devices will be used , they must have the same erase size capabilities and opcodes. ? required command set and associated opcodes (refer to section 5.23.3.1 ). ? jedec id device identification command (refer to section 5.23.3.3 ). ? device must support multiple writes to a page without requiring a preceding erase cycle (refer to section 5.23.3.4 ) ? serial flash device must ignore the upper address bits such that an address of ffffffh simply aliases to the top of the flash memory. ? spi compatible mode 0 support (clock phase is 0 and data is latched on the rising edge of the clock). ? if the device receives a command that is not supported, the device must complete the cycle gracefully without any impact on the flash content. ? an erase command (page, sector, block, chip, etc.) must set to 1 (ffh) all bits inside the designated area (page, sector, block, chip, etc.). ? minimum density of 4 mbit (platfor m dependent based on size of bios). 5.23.2.2 device requirements for intel ? amt, asf and afsc firmware ich8 has added the capability that a single spi flash device can be used to store system bios, intel amt firmware and gbe eeprom information. th is unified flash configuration for system bios and intel amt firmware must meet the following minimum requirements to be compatible with the ich8: the following are requirements that ar e in common with system bios only configuration as listed in section 5.23.2.1 : intel ? ich8 family datasheet 247 functional description the following is a list of additional requirements specific to configurations 2 and 3: ? 4 kbytes erase size must be supported. ? flash device must power up in an unlocked state (no write protection) or use the write status register to disable write protection. if the write status register must be unprotected, it must use the enable write status register command 50h or write enable 06h. opcode 01h must then be used to write 00h into the write status register. this must unlock the entire part. if there is no need to write enable the write status register, then 06h and 50h must be ignored. ? byte write must be supported. ? the flexibility to perform a write between 1 byte to 256 bytes is recommended ? a serial flash device that requires th e write enable command must automatically clear the write enable latch at the end of data program instructions. ? status register bit 0 must be set to 1 when a write or erase is in progress and cleared to 0 when a write or erase is not in progress. ? minimum density of afsc + bios is 8 mb ? minimum density of asf + bios is 8 mb ? minimum density of intel ? amt 2.0 (desktop only)+bios+gbe is 16 mb; minimum density of intel amt 2.5 (mobile only) + bios +gbe is 32 mb. 5.23.2.3 device requirements for gbe a serial flash device that will be used fo r both system bios and gbe on the same device must meet the minimum compatibility requirements detailed in section 5.23.2.1 5.23.3 serial flash command set 5.23.3.1 required command set for inte roperability the following table contains a list of commands and the associated opcodes that a spi- based serial flash device must support in order to be interoperable with the intel serial peripheral interface. table 97. required commands and opcodes commands opcode notes write status 01h if command is suppo rted, 01h must be the opcode. program data 02h write data / program data read data 03h write disable 04h read status 05h write enable 06h if command is suppo rted, 06h must be the opcode. fast read 0bh enable write status 50h if write status register must be unlocked it must use this opcode or write enable. erase programmab le size and opcode programmed in the vssc register jedec id 9fh refer to section 5.23.3.3 functional description 248 intel ? ich8 family datasheet 5.23.3.2 recommended command set and opcodes the following table lists recommended opcodes for serial flash commands. using a command specified below, with the associat ed opcode, will allow software developers to streamline their code and will aid in minimizing latencies. 5.23.3.3 jedec devi ce identification since each serial flash device may have unique capabilities and commands, the jedec id is the necessary mechanism for identify ing the device so the uniqueness of the device can be comprehended by the controlle r (master). the jedec id uses the opcode 9fh and a specified implementation an d usage model. this jedec standard manufacturer and device id read method is defined in standard jesd21-c, prn03-nv1 and is available on the jedec website: www.jedec.org. 5.23.3.4 multiple page write usage model the system bios and intel ? active management technolo gy firmware usage models require that the serial flash device support multiple writes (minimum of 512 writes) to a page (256 bytes) without requiring a preceding erase command. bios commonly uses capabilities such as counters that are typically implemented by using byte writes to ?increment? the bits within a page that have been designated as the counter. the intel amt firmware usage model requires the capability for multiple data updates within any given page. these data updates occur via byte writes without executing a preceding erase to the given page. both th e bios and intel amt firmware multiple page write usage models apply to sequential and non-sequential data writes. note: this usage model requirement is based on any given bit only being written once from a ?1? to a ?0? without requiring the preceding erase. an erase would be required to change bits back to the ?1? state. table 98. recommended command and opcode associations commands opcode notes full chip erase c7h intel ? ich8 family datasheet 249 functional description 5.24 intel ? quiet system technology (desktop only) the ich8 implements three pwm and 4 tach signals for fan speed control. note: intel ? quiet system technology functionality requires a correctly configured system, including an appropriate (g)mch with me , me firmware, and system bios support. 5.24.1 pwm outputs this signal is driven as open-drain. an external pull-up resistor is integrated into the fan to provide the rising edge of the pwm output signal. the pwm output is driven low during reset, which represents 0% duty cycl e to the fans. after reset de-assertion, the pwm output will continue to be driven low until one of the following occurs: ? the internal pwm control register is prog rammed to a non-zero value by the afsc firmware ? the watchdog timer expires (enabled and set at 4 seconds by default). ? the polarity of the signal is inverted by the intel quiet system technology firmware note that if a pwm output will be programmed to inverted polarity for a particular fan, then the low voltage driven during rese t represents 100% duty cycle to the fan. 5.24.2 tach inputs this signal is driven as an open-collector or open-drain output from the fan. an external pull-up is expected to be impl emented on the motherboard to provide the rising edge of the tach input. this signal has analog hysteresis and digital filtering due to the potentially slow rise and fall times. this signal has a weak internal pull-up resistor to keep the input buffer from floating if the tach input is not connected to a fan. 5.25 thermal sensors ich8 integrates two thermal sensors that monitor the temperature within its die. the thermal sensors are used for intel quiet system technology. the afsc firmware can internally access the temperature measured by the sensors and use the data as a factor to determine how to control the fans. the ich8 thermal sensors also provide the capability to protect the ich8 under a catastrophic thermal situation. when the sensors are enabled and correctly programmed by the system bios, the ich8 wi ll shut down the system when the ich8 thermal limit is reached. refer to the ther mal memory mapped configuration registers (section 20.2) for more information on the catastrophic settings. functional description 250 intel ? ich8 family datasheet 5.26 intel ? quick resume technology (intel ? ich8dh only) ich8dh implements the following inte l quick resume technology features: ? visual off ? consumer electronics (ce) like on/off 5.26.1 5.26.1 visual off intel quick resume technology provides a new functional state called visual off. in visual off the pc appears to be off but is ac tually active and able to run program tasks. the visual off state is transparent to the user. it is entered by simply pressing the power button when the system is on. this turns off the display, sound, front panel lights and hid devices (e.g. keyboard and mouse) but the pc stays active. perceptually to the user, the system appears off in this state. pressing the power button again will turn back on the perceptual componen ts that were ?muted? in visual off. from the visual off state, the system's power management can place the pc in a low power suspend state (s3) using existing mech anisms. again, this is transparent to the end user. 5.26.2 5.26.2 ce-like on/off intel quick resume technology redefines the pc's power button behavior to switch between user perceived on and off states lik e a consumer electronics (ce) device. for example when a television is turned off th ere is no shutdown procedure. the viewer simply turns it off. likewise when a modern television is turned on it returns to the same channel, volume level, color balance, et c. as when it was turned off. intel quick resume technology gives the pc this similar functionality. a simple press of the power button turns it on or off. there is no user visible lengthy boot up or shutdown process as the visual off state is used. therefore, th ere is no need to exit running applications. just as televisions may have multiple powe r buttons (e.g. on the tv and on a remote control) so may the pc (e.g. a power button on the system unit and another on the keyboard). however all power buttons behave the same - on/off. the pc will not turn on (wake up) when any key is pressed or the mouse moved just as pressing the volume button or tv channel button does not cause the tv to turn on. only a power button press turns it on and off. 5.26.3 intel ? quick resume technology signals to provide the end user notification of the system power state, it is recommended that the front panel led be used to indicate visual off in the same way that the front panel led is used to indicate the s3 system state. for example, if in the s3 state the front panel led is solid amber, also set the front panel led to be solid amber upon entrance into visual off. to provide for platform implementation flex ibility, the ich8 implements two intel quick resume technology signals which are mult iplexed with gpios: qrt_state0/gpio27 and qrt_state1/gpio28. the qrt_state[1:0] pins may be used to control led(s) to provide end-user notification of the current system state or may be used as gpio pins (independently or combined). see section 14 for further details on controlling these signals. intel ? ich8 family datasheet 251 functional description 5.26.4 power button sequence when intel quick resume technology is enabled and the user presses the pwrbtn# to indicate a desire to put the system into the visual off state, the following sequence is assumed: 1. user presses the power button, which causes the pwrbtn# signal to go low. 2. intel quick resume technology logi c sets the el_pb_ sts bit. if the pwrbtn_int_en bit is set, the ich8 does not set the pwrbtn_sts bit at this point. 3. intel quick resume technology logic causes an smi or sci (depending on the smi_option_cnt bit.) 4. if the intel quick resume technology logic was set to cause an smi, the smi handler executes and then sets the sci_now_cnt bit. 5. the intel quick resume technology sci handler executes. 6. the intel quick resume technology sci handler needs to cause the pwrbtn_sts bit to be set, it can do so by setting the pwrbtn_event bit. note: when pwrbtn_sts is set, the ich8 causes an sci and the normal os handler for pwrbtn_sts is called. 5.27 feature capability mechanism a new set of registers have been added into ich8 lpc interface (device 31, function 0, offset e0h ? ebh) that allows the system software or bios to easily determine the features supported by ich8. these registers can be accessed through lpc pci configuration space, thus allowing for conv enient single point access mechanism for chipset feature detection. this set of registers consists of: capability id (fdcap) capability length (fdlen) capability version and vendor-s pecific capability id (fdver) feature vector (fvect) functional description 252 intel ? ich8 family datasheet 5.28 serial post codes over gpio ich8 adds the extended capab ility allowing system software to serialize post or other messages on gpio. this capability negates the requirement for dedicated diagnostic leds on the platform. additionally, based on the newer btx form factors, the pci bus as a target for post codes is increasingly di fficult to support as the total number of pci devices supported are decreasing. 5.28.1 theory of operation for the ich8, generation post code serializ ation logic will be shared with gpio. these gpio will likely be shared with led control offered by the super i/o (sio) component. the anticipated usage model is that either the ich8 or the sio can drive a pin low to turn off an led. in the case of the power led, the sio would normally leave its corresponding pin in a high-z state to allow th e led to turn on. in this state, the ich8 can blink the led by driving its corresponding pin low and subsequently tri-stating the buffer. an external optical sensing device can detect the on/off state of the led. by externally post-processing the information from the optical device, the serial bit stream can be recovered. the hardware will supply a ?sync? byte before the actual data transmission to allow external detection of the transmit frequency. the frequency of transmission should be limited to 1 transition every 1usec to ensure the detector can reliably sample the on/off state of the led. to allow flex ibility in pull-up resistor values for power optimization, the frequency of the transmission is programmable via the drs field in the gp_sb_cmdsts register (see section 9.10.7 ). the serial bit stream is manchester encoded. this choice of transmission ensures that a transition will be seen on every clock. the 1 or 0 data is based on the transmission happening during the high or low phase of the clock. a simplified hardware/software register interface provides control and status information to track the activity of this block. software enabling the serial blink capability should implement an algorithm re ferenced below to send the serialized message on the enabled gpio. 1. read the go/busy status bit in the gp_sb_cmdsts register and verify it is cleared. this will ensure that the gpio is idled and a previously requested message is still not in progress. 2. write the data to serialize into the gp_sb_data register. 3. write the dls and drs values into the gp _sb_cmdsts register and set the go bit. this may be accomplished using a single write. by providing a generic capability that can be used both in the main and the suspend power planes, maximum flexibility can be ac hieved. a key point to make is that the ich8 will not unintentionally drive the led control pin low unless a serialization is in progress. system board connections using this serialization capability are required to use the same power plane controlling the le d as the ich8 gpio pin. otherwise, the ich8 gpio may float low during the me ssage and prevent the led from being controlled from the sio. the hardware will on ly be serializing messages when the core power well is powered and the processor is operational. care should be taken to prevent the ich8 from driving an active ?1? on a pin sharing the serial led capability. since the sio could be driving the line to 0, having the ich8 drive a 1 would create a high current path. a recommendation to avoid this condition involves choosing a gpio defaulting to an input. the gp_ser_blink register (see intel ? ich8 family datasheet 253 functional description section 9.10.7 ) should be set first before changing the direction of the pin to an output. this sequence ensures the open-drain capab ility of the buffer is properly configured before enabling the pin as an output. 5.28.2 serial message format to serialize the data onto the gpio, an init ial state of hi-z is assumed. the sio is required to have its led control pin in a high-z state as well to allow ich8 to blink the led. the three components of the serial message include the sync, data, and idle fields. the sync field is 7 bits of ?1? data followed by 1 bit of ?0? data. starting from the hi-z state (led on) provides external hardware a known initial condition and a known pattern. in case one or more of the leading 1 sync bi ts are lost, the 1?s followed by 0 provide a clear indication of ?end of sync?. this patte rn will be used to ?lock? external sampling logic to the encoded clock. the data field is shifted out with the highes t byte first (msb). within each byte, the most significant bit is shifted first (msb). the idle field is enforced by the hardware an d is at least 2 bit times long. the hardware will not clear the busy and go bits until this idle time is met. supporting the idle time in hardware prevents time-based counting in bi os as the hardware is immediately ready for the next serial code when the go bit is cleared. note that the idle state is represented as a high-z condition on the pin. if the last transmitted bit is a ?1?, returning to the idle state will result in a final 0-1 transition on the output manchester data. two full bit times of idle correspond to a count of 4 time intervals (the width of the time interval is controlled by the drs field). the waveform below shows a 1-byte serial writ e with a data byte of 5ah. the internal clock and bit position are for reference purposes only. the manchester d is the resultant data generated and serialized onto the gpio. since the buffer is operating in open-drain mode the transitions are from hi-z to 0 and back. internal clock manchester d 8-bit sync field (1111_1110) bit 7 0 1 2 3 4 5 6 5a data byte 2 clk idle functional description 254 intel ? ich8 family datasheet intel ? ich8 family datasheet 255 register and memory mapping 6 register and memory mapping the ich8 contains registers that are located in the processor?s i/o space and memory space and sets of pci configuration registers that are located in pci configuration space. this chapter describes the ich8 i/o an d memory maps at the register-set level. register access is also described. register-level address maps and individual register bit descriptions are provided in the followi ng chapters. the following notations and definitions are used in the register /instruction description chapters. ro read only. in some cases, if a regi ster is read only, writes to this register location have no effect. however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. wo write only. in some cases, if a register is write only, reads to this register location have no effect. however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. r/w read/write. a register with this attribute can be read and written. r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. r/wo read/write-once. a register bit with this attribute can be written only once after power up. after the first write, the bit becomes read only. r/wlo read/write, lock-once. a register bit with this attribute can be written to the non-locked value multiple times, but to the locked value only once. after the locked value has been written, the bit becomes read only. default when ich8 is reset, it sets its registers to predetermined default states. the default state repres ents the minimum functionality feature set required to successfu lly bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the ich8 registers accordingly. bold register bits that are highlighted in bold text indicate that the bit is implemented in the ich8. register bits that are not implemented or are hardwired will remain in plain text. 6.1 pci devices and functions the intel ich8 incorporates a variety of pci devices and functions, as shown in table 99 . they are divided into seven logical devices. the first is the dmi-to-pci bridge (device 30). the second device (device 31) contains most of the standard pci functions that always existed in the pci-to -isa bridges (south bridges), such as the intel piix4 or intel piix6. the third and fo urth (device 29 and device 26) are the usb register and memory mapping 256 intel ? ich8 family datasheet (and usb2) host controller devices. the fi fth (device 28) is pci express device. the sixth (device 27) is hd audio controller device, and the seventh (device 25) is the gbe controller device. if for some reason, the particular system platform does not want to support any one of the device functions, with the exception of d30:f0, they can individually be disabled. the integrated lan controller will be disabled if no platform lan connect component is detected (see chapter 5.3 ). when a function is disabled, it does not appear at all to the software. a disabled function will not respond to any register reads or writes, insuring that these devices appear hidden to software. b notes: 1. the pci-to-lpc bridge contai ns registers that control lp c, power manage ment, system management, gpio, proces sor interface, rtc, inte rrupts, timers, and dma 2. when usb ports 9, 10 and ehci controller #2 are disabled, the uhci host controller #4 will be mapped to d29:f3. otherwise, it will be mapped to d26:f0. table 99. pci devices and functions bus:device:function function description bus 0:device 30:functi on 0 pci-to-pci bridge bus 0:device 31:function 0 lpc controller 1 bus 0:device 31:function 1 ide controller bus 0:device 31:function 2 sata controller #1 bus 0:device 31:function 3 smbus controller bus 0:device 31:function 5 sata controller #2 bus 0:device 31:function 6 thermal subsystem bus 0:device 29:function 0 usb uhci controller #1 bus 0:device 29:function 1 usb uhci controller #2 bus 0:device 29:function 2 usb uhci controller #3 bus 0:device 29:function 3 usb uhci controller #42 bus 0:device 26:function 0 usb1.1 uhci controller #4 2 bus 0:device 26:function 1 usb1.1 uhci controller #5 bus 0:device 29:function 7 usb 2.0 ehci controller #1 bus 0:device 26:fucntion 7 usb2 ehci controller #2 bus 0:device 28:function 0 pci express* port 1 bus 0:device 28:function 1 pci express port 2 bus 0:device 28:function 2 pci express port 3 bus 0:device 28:function 3 pci express port 4 bus 0:device 28:function 4 pci express port 5 bus 0:device 28:function 5 pci express port 6 bus 0:device 27:function 0 intel ? high definition audio controller bus 0:device 25:function 0 gbe controller intel ? ich8 family datasheet 257 register and memory mapping 6.2 pci configuration map each pci function on the ich8 has a set of pci configuration registers. the register address map tables for these register sets are included at the beginning of the chapter for the particular function. configuration space registers are accessed th rough configuration cycles on the pci bus by the host bridge using configur ation mechanism #1 detailed in the pci local bus specification, revision 2.3 . some of the pci registers contain reserved bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of re served bit positions are preserved. that is, the values of reserved bit positions must fi rst be read, merged with the new values for other bit positions and then written back. no te the software does not need to perform read, merge, write operation for the configuration address register. in addition to reserved bits within a register, the configuration space contains reserved locations. software should not write to re served pci configuration locations in the device-specific region (above address offset 3fh). 6.3 i/o map the i/o map is divided into fixed and variable address ranges. fixed ranges cannot be moved, but in some cases can be disabled. variable ranges can be moved and can also be disabled. 6.3.1 fixed i/o address ranges table 100 shows the fixed i/o decode ranges from the processor perspective. note that for each i/o range, there may be separate behavior for reads and writes. dmi (direct media interface) cycles that go to ta rget ranges that are marked as ?reserved? will not be decoded by the ich8, and will be passed to pci unless the subtractive decode policy bit is set (d31:f0:offset 42h, bit 0). if a pci master targets one of the fixed i/o target ranges, it will be positive ly decoded by the ich8 in medium speed. refer to table 100 for a complete list of all fixed i/o registers. address ranges that are not listed or marked ?reserved? are not decoded by the ich8 (unless assigned to one of the variable ranges). register and memory mapping 258 intel ? ich8 family datasheet table 100. fixed i/o ranges decoded by intel ? ich8 (sheet 1 of 2) i/o address read target write target internal unit 00h?08h dma controller dma controller dma 09h?0eh reserved dma controller dma 0fh dma controller dma controller dma 10h?18h dma controller dma controller dma 19h?1eh reserved dma controller dma 1fh dma controller dma controller dma 20h?21h interrupt controller in terrupt controller interrupt 24h?25h interrupt controller in terrupt controller interrupt 28h?29h interrupt controller in terrupt controller interrupt 2ch?2dh interrupt controller interrupt controller interrupt 2e?2f lpc sio lpc sio forwarded to lpc 30h?31h interrupt controller in terrupt controller interrupt 34h?35h interrupt controller in terrupt controller interrupt 38h?39h interrupt controller in terrupt controller interrupt 3ch?3dh interrupt controller interrupt controller interrupt 40h?42h timer/counter timer/counter pit (8254) 43h reserved timer/counter pit 4e?4f lpc sio lpc sio forwarded to lpc 50h?52h timer/counter timer/counter pit 53h reserved timer/counter pit 60h microcontroller microcon troller forwarded to lpc 61h nmi controller nmi controller processor i/f 62h microcontroller microcon troller forwarded to lpc 64h microcontroller microcon troller forwarded to lpc 66h microcontroller microcon troller forwarded to lpc 70h reserved nmi and rtc controller rtc 71h rtc controller rtc controller rtc 72h rtc controller nmi and rtc controller rtc 73h rtc controller rtc controller rtc 74h rtc controller nmi and rtc controller rtc 75h rtc controller rtc controller rtc 76h rtc controller nmi and rtc controller rtc 77h rtc controller rtc controller rtc 80h dma controller, or lpc, or pci dma controller and lpc or pci dma 81h?83h dma controller dma controller dma 84h?86h dma controller dma controller and lpc or pci dma 87h dma controller dma controller dma intel ? ich8 family datasheet 259 register and memory mapping notes: 1. a read to this address will subtractivel y go to pci, where it will master abort. 2. mobile only: only if ide i/o space is enabled (d31:f1:40 bit 15) and the ide controller is in legacy mode. otherwise, the target is pci. 88h dma controller dma controller and lpc or pci dma 89h?8bh dma controller dma controller dma 8ch?8eh dma controller dma controller and lpc or pci dma 08fh dma controller dma controller dma 90h?91h dma controller dma controller dma 92h reset generator reset generator processor i/f 93h?9fh dma controller dma controller dma a0h?a1h interrupt controller interrupt controller interrupt a4h?a5h interrupt controller interrupt controller interrupt a8h?a9h interrupt controller interrupt controller interrupt ach?adh interrupt controller interrupt controller interrupt b0h?b1h interrupt controller interrupt controller interrupt b2h?b3h power management power management power management b4h?b5h interrupt controller interrupt controller interrupt b8h?b9h interrupt controller interrupt controller interrupt bch?bdh interrupt controller interrupt controller interrupt c0h?d1h dma controller dma controller dma d2h?ddh reserved dma controller dma deh?dfh dma controller dma controller dma f0h pci and master abort 1 ferr#/ignne# / interrupt controller processor i/f 170h?177h ide controller (mobile only), sata controller, or pci ide controller (mobile only), sata controller, or pci forwarded to ide (mobile only) or sata 1f0h?1f7h ide controller (mobile only), sata controller, or pci2 ide controller (mobile only), sata controller, or pci forwarded to ide (mobile only) or sata 376h ide controller (mobile only), sata controller, or pci ide controller (mobile only), sata controller, or pci forwarded to ide (mobile only) or sata 3f6h ide controller (mobile only), sata controller, or pci 2 ide controller (mobile only), sata controller, or pci forwarded to ide (mobile only) or sata 4d0h?4d1h interrupt controller interrupt controller interrupt cf9h reset generator reset generator processor i/f table 100. fixed i/o ranges decoded by intel ? ich8 (sheet 2 of 2) i/o address read target write target internal unit register and memory mapping 260 intel ? ich8 family datasheet 6.3.2 variable i/o decode ranges table 101 shows the variable i/o decode ranges. they are set using base address registers (bars) or other configuration bits in the various pci configuration spaces. the pnp software (pci or acpi) can use their configuration mechanisms to set and adjust these values. warning: the variable i/o ranges should not be set to conflict with the fixed i/o ranges. unpredictable results if the configuration soft ware allows conflicts to occur. the ich8 does not perform any checks for conflicts. note: 1. decode range size determined by d31:f0:adh:bits 5:4. table 101. variable i/o decode ranges range name mappable size (bytes) target acpi anywhere in 64 kb i/o space 64 power management ide bus master (mobile only) anywhere in 64 kb i/o space 16 ide unit native ide command (mobile only) anywhere in 64 kb i/o space 8 ide unit native ide control (mobile only) anywhere in 64 kb i/o space 4 ide unit usb uhci controller #1 anywhere in 64 kb i/o space 32 usb unit 1 usb uhci controller #2 anywhere in 64 kb i/o space 32 usb unit 2 usb uhci controller #3 anywhere in 64 kb i/o space 32 usb unit 3 usb uhci controller #4 anywhere in 64 kb i/o space 32 usb unit 4 usb uhci controller #5 anywhere in 64 kb i/o space 32 usb unit 5 smbus anywhere in 64 kb i/o space 32 smb unit tco 96 bytes above acpi base 32 tco unit gpio anywhere in 64 kb i/o space 64 gpio unit parallel port 3 ranges in 64 kb i/o space 8 lpc peripheral serial port 1 8 ranges in 64 kb i/o space 8 lpc peripheral serial port 2 8 ranges in 64 kb i/o space 8 lpc peripheral floppy disk controller 2 ranges in 64 kb i/o space 8 lpc peripheral lan anywhere in 64 kb i/o space 32 lan unit lpc generic 1 anywhere in 64 kb i/o space 4 to 256 lpc peripheral lpc generic 2 anywhere in 64 kb i/o space 4 to 256 lpc peripheral lpc generic 3 anywhere in 64 kb i/o space 4 to 256 lpc peripheral lpc generic 4 anywhere in 64 kb i/o space 4 to 256 lpc peripheral i/o trapping ranges anywhere in 64 kb i/o space 1 to 256 trap on backbone intel ? ich8 family datasheet 261 register and memory mapping 6.4 memory map table 102 shows (from the processor perspective) the memory ranges that the ich8 decodes. cycles that arrive from dmi that are not directed to any of the internal memory targets that decode directly from dmi will be driven out on pci unless the subtractive decode policy bit is set (d31:f0:offset 42h, bit 0). pci cycles generated by external pci masters will be positively decoded unless they fall in the pci-to-pci bridge memory forwarding ranges (those addresses are reserved for pci peer-to-peer traffic). if the cycle is not in the internal lan controller?s range, it will be forwarded up to dmi. software must not attempt locks to the ich8?s memory- mapped i/o ranges for ehci and hpet. if attempted, the lock is not honored which means potential deadlock conditions may occur. table 102. memory decode ranges from processor perspective (sheet 1 of 2) memory range target dependency/comments 0000 0000h?000d ffffh 0010 0000h?tom (top of memory) main memory tom registers in host controller 000e 0000h?000e ffffh firmware hub bit 6 in firmware hub decode enable register is set 000f 0000h?000f ffffh firmware hub bit 7 in firmware hub decode enable register is set fec0 x000h?fec0 x040h io(x) apic inside ich8 x is controlled via apic range select (asel) field and apic enable (aen) bit fec1 0000h?fec1 7fff pci express* port 1 pci express* root port 1 i/oxapic enable (pae) set fec1 8000h?fec1 8fffh pci express* port 2 pci express* root port 2 i/oxapic enable (pae) set fec2 0000h?fec2 7fffh pci express* port 3 pci express* root port 3 i/oxapic enable (pae) set fec2 8000h?fec2 8fffh pci express* port 4 pci express* root port 4 i/oxapic enable (pae) set fec3 0000h?fec3 7fffh pci express* port 5 pci express* root port 5 i/oxapic enable (pae) set fec3 8000h?fec3 8fffh pci express* port 6 pci express* root port 6 i/oxapic enable (pae) set fed4 0000h?fed4 bfffh tpm on lpc ffc0 0000h?ffc7 ffffh ff80 0000h?ff87 ffffh firmware hub (or pci) 2 bit 8 in firmware hub decode enable register is set ffc8 0000h?ffcf ffffh ff88 0000h?ff8f ffffh firmware hub (or pci) 2 bit 9 in firmware hub decode enable register is set ffd0 0000h?ffd7 ffffh ff90 0000h?ff97 ffffh firmware hub (or pci) 2 bit 10 in firmware hub decode enable register is set ffd8 0000h?ffdf ffffh ff98 0000h?ff9f ffffh firmware hub (or pci) 2 bit 11 in firmware hub decode enable register is set ffe0 000h?ffe7 ffffh ffa0 0000h?ffa7 ffffh firmware hub (or pci) 2 bit 12 in firmware hub decode enable register is set register and memory mapping 262 intel ? ich8 family datasheet notes: 1. software must not at tempt locks to memory mapped i/o ranges for usb ehci or high precision event timers. if attempted, the lo ck is not honored, which means potential deadlock conditions may occur. 2. pci is the target when the boot bios destination selection bit is low (chipset config registers:offset 3401:bit 3). when pci select ed, the firmware hub decode enable bits have no effect. ffe8 0000h?ffef ffffh ffa8 0000h?ffaf ffffh firmware hub (or pci) 3 bit 13 in firmware hub decode enable register is set fff0 0000h?fff7 ffffh ffb0 0000h?ffb7 ffffh firmware hub (or pci) 2 bit 14 in firmware hub decode enable register is set fff8 0000h?ffff ffffh ffb8 0000h?ffbf ffffh firmware hub (or pci) 2 always enabled. the top two, 64 kb blocks of this range can be swapped, as described in section 7.4.1 . ff70 0000h?ff7f ffffh ff30 0000h?ff3f ffffh firmware hub (or pci) 2 bit 3 in firmware hub decode enable register is set ff60 0000h?ff6f ffffh ff20 0000h?ff2f ffffh firmware hub (or pci) 2 bit 2 in firmware hub decode enable register is set ff50 0000h?ff5f ffffh ff10 0000h?ff1f ffffh firmware hub (or pci) 2 bit 1 in firmware hub decode enable register is set ff40 0000h?ff4f ffffh ff00 0000h?ff0f ffffh firmware hub (or pci) 2 bit 0 in firmware hub decode enable register is set 128 kb anywhere in 4- gb range integrated lan controller enable via bar in device 25:function 0 (integrated lan controller) 1 kb anywhere in 4-gb range usb ehci controller #1 1 enable via standard pci mechanism (device 29, function 7) 1 kb anywhere in 4-gb range usb ehci controller #2 1 enable via standard pci mechanism (device 26, function 7) 512 b anywhere in 64-bit addressing space intel ? high definition audio host controller enable via standard pci mechanism (device 27, function 0) fed0 x000h?fed0 x3ffh high precision event timers 1 bios determines the ?fixed? location which is one of four, 1-kb ranges where x (in the first column) is 0h, 1h, 2h, or 3h. all other pci none table 102. memory decode ranges from processor perspectiv e (sheet 2 of 2) memory range target dependency/comments intel ? ich8 family datasheet 263 register and memory mapping 6.4.1 boot-block update scheme the ich8 supports a ?top-block swap? mode that has the ich8 swap the top block in the firmware hub (the boot block) with anothe r location. this allows for safe update of the boot block (even if a power failure occurs). when the ?top_swap? enable bit is set, the ich8 will invert a16 for cycles targ eting firmware hub space. when this bit is 0, the ich8 will not invert a16. this bit is automatically set to 0 by rtcrst#, but not by pltrst#. the scheme is based on the concept that the top block is reserved as the ?boot? block, and the block immediately below the top block is reserved for doing boot-block updates. the algorithm is: 1. software copies the top block to the block immediately below the top 2. software checks that the copied block is correct. this could be done by performing a checksum calculation. 3. software sets the top_swap bit. this will invert a16 for cycles going to the firmware hub. processor access to ffff_0000h through ffff_ffffh will be directed to fffe_0000h through fffe_ffffh in the firmware hub, and processor accesses to fffe_0000h through fffe_ffff will be directed to ffff_0000h through ffff_ffffh. 4. software erases the top block 5. software writes the new top block 6. software checks the new top block 7. software clears the top_swap bit 8. software sets the top_swap lock-down bit if a power failure occurs at any point after st ep 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. this is because the top_swap bit is backed in the rtc well. note: the top-block swap mode may be forced by an external strapping option (see section 2.26.1 ). when top-block swap mode is forced in this manner, the top_swap bit cannot be cleared by software. a re-boot with the strap removed will be required to exit a forced top-block swap mode. note: top-block swap mode only affects accesses to the firmware hub space, not feature space. note: the top-block swap mode has no effect on accesses below fffe_0000h. register and memory mapping 264 intel ? ich8 family datasheet intel ? ich8 family datasheet 265 chipset configuration registers 7 chipset configuration registers this section describes all registers and base functionality that is related to chipset configuration and not a specific interface (s uch as lpc, pci, or pci express*). it contains the root complex register block, which describes the behavior of the upstream internal link. this block is mapped into memory space, using register rcba of the pci-to-lpc bridge. accesses in this space must be limited to 32-(dw) bit quantities. burst accesses are not allowed. 7.1 chipset configuration registers (memory space) note: address locations that are not shown should be treated as reserved (see section 6.2 for details). . table 103. chipset configuratio n register memory map (mem ory space) (sheet 1 of 3) offset mnemonic register name default type 0000?0003h vch virtual channel capability header 10010002h ro 0004?0007h vcap1 virtual channel capability #1 00000801h ro 0008?000bh vcap2 virtual channel capability #2 00000001h ro 000c?000dh pvc port vc control 0000h r/w, ro 000e?000fh pvs port vc status 0000h ro 0010?0013h v0cap vc 0 resource capability 00000001h ro 0014?0017h v0ctl vc 0 resource control 800000ffh r/w, ro 001a?001bh v0sts vc 0 resource status 0000h ro 001c?001fh v1cap vc 1 resource capability 30008010h r/wo, ro 0020?0023h v1ctl vc 1 resource control 00000000h r/w, ro 0026?0027h v1sts vc 1 resource status 0000h ro 0030?006fh pat port arbitration table 0088?008bh cir1 chipset initialization register 1 00000000h r/wo, ro 0100?0103h rctcl root complex topology capability list 1a010005h ro 0104?0107h esd element self description 00000602h r/wo, ro 0110?0113h uld upstream link descriptor 00000001h r/wo, ro 0118?011fh ulba upstream link base address 00000000000000 00h r/wo 0120?0123h rp1d root port 1 descriptor 01xx0002h r/wo, ro 0128?012fh rp1ba root port 1 base address 00000000000e00 00h ro 0130?0133h rp2d root port 2 descriptor 02xx0002h r/wo, ro 0138?013fh rp2ba root port 2 base address 00000000000e10 00h ro chipset configuration registers 266 intel ? ich8 family datasheet 0140?0143h rp3d root port 3 descriptor 03xx0002h r/wo, ro 0148?014fh rp3ba root port 3 base address 00000000000e20 00h ro 0150?0153h rp4d root port 4 descriptor 04xx0002h r/wo, ro 0158?015fh rp4ba root port 4 base address 00000000000e30 00h ro 0160?0163h hdd intel ? high definition audio descriptor 15xx0002h r/wo, ro 0168?016fh hdba intel high definition audio base address 00000000000d80 00h ro 0170?0173h rp5d root port 5 descriptor 05xx0002h r/wo, ro 0178?017fh rp5a root port 5 base address 00000000000e40 00h ro 0180?0183h rp6d root port 6 descriptor 06xx0002h r/wo, ro 0188?018fh rp6ba root port 6 base address 00000000000e50 00h ro 01a0?01a3h ilcl internal link capability list 00010006h ro 01a4?01a7h lcap link capabilities 00012441h ro, r/wo 01a8?01a9h lctl link control 0000h r/w 01aa?01abh lsts link status 0041h ro 01fc?01fdh cir3 chipset initialization register 3 0000h r/w, ro 0200?0201h cir4 chipset initialization register 4 0000h r/w, ro 0220?0223h bcr backbone configuration register 00000000 r/w 0224?0227h rpc root port configuration 0000000xh r/w, ro 0234?0237h dmic dmi control register 00000000h r/w, ro 0238?023bh rpfn root port function number for pci express root ports 00543210h r/wo, ro 1d40?1d47h cir5 chipset initialization register 5 00000000000000 00h r/w, r/ wl 1e00?1e03h trsr trap status register 00000000h r/wc, ro 1e10?1e17h trcr trapped cycle register 00000000000000 00h ro 1e18?1e1fh twdr trapped write data register 00000000000000 00h ro 1e80?1e87h iotr0 i/o trap register 0 00000000000000 00h r/w, ro 1e88?1e8fh iotr1 i/o trap register 1 00000000000000 00h r/w, ro 1e90?1e97h iotr2 i/o trap register 2 00000000000000 00h r/w, ro 1e98?1e9fh iotr3 i/o trap register 3 00000000000000 00h r/w, ro table 103. chipset configuration register me mory map (memory space) (sheet 2 of 3) offset mnemonic register name default type intel ? ich8 family datasheet 267 chipset configuration registers 2010?2013h dmc dmi miscellaneous control register (mobile only) not applicable r/w 2024?2027h cir6 chipset initialization register 6 (mobile only) 0b2030xxh r/w, ro 2034?2037h cir7 chipset initialization register 7 b2b477cch r/w 3000?3001h tctl tco control 00h r/w 3100?3103h d31ip device 31 interrupt pin 03243210h r/w, ro 3104?3107h d30ip device 30 interrupt pin 00000000h r/w, ro 3108?310bh d29ip device 29 interrupt pin 10004321h r/w 310c?310fh d28ip device 28 interrupt pin 00004321h r/w 3110?3113h d27ip device 27 interrupt pin 00000001h r/w 3114?3117h d26ip device 26 interrupt pin 30000021h r/w, ro 3118?3121h d25ip device 25 interrupt pin 00000001h r/w, ro 3140?3141h d31ir device 31 interrupt route 3210h r/w 3144?3145h d29ir device 29 interrupt route 3210h r/w 3146?3147h d28ir device 28 interrupt route 3210h r/w 3148?3149h d27ir device 27 interrupt route 3210h r/w 314c?314dh d26ir device 26 interrupt route 3210h r/w 3150?3151h d25ir device 25 interrupt route 3210h r/w 31ff?31ffh oic other interrupt control 00h r/w 3400?3403h rc rtc configuration 00000000h r/w, r/wlo 3404?3407h hptc high precision timer configuration 00000000h r/w 3410?3413h gcs general control and status 0000000xh r/w, r/wlo 3414?3414h buc backed up control 0000001xb (mobile) 0000000xb (desktop) r/w 3418?341bh fd function disable see bit description r/w, ro 341c?341fh cg clock gating (mobile only) 00000000h r/w, ro 3420h fdsw function disable sus well 00h r/w, ro 3430h cir8 chipset initialization register 8 00h r/w, ro 350ch-350fh cir9 chipset initialization register 9 00000000h r/w, ro table 103. chipset configuratio n register memory map (mem ory space) (sheet 3 of 3) offset mnemonic register name default type chipset configuration registers 268 intel ? ich8 family datasheet 7.1.1 vch?virtual channel ca pability header register offset address: 0000?0003h attribute: ro default value: 10010002h size: 32-bit 7.1.2 vcap1?virtual channel capability #1 register offset address: 0004?0007h attribute: ro default value: 00000000h size: 32-bit 7.1.3 vcap2?virtual channel capability #2 register offset address: 0008?000bh attribute: ro default value: 00000001h size: 32-bit bit description 31:20 next capability offset (nco) ? ro. indicates the next item in the list. 19:16 capability version (cv) ? ro. indicates support as a version 1 capability structure. 15:0 capability id (cid) ? ro. indicates this is the virtual channel capability item. bit description 31:12 reserved 11:10 port arbitration table entry size (pats) ? ro. indicates the size of the port arbitration table is 4 bits (to allow up to 8 ports). 9:8 reference clock (rc) ? ro. fixed at 100 ns. 7 reserved 6:4 low priority extended vc count (lpevc) ? ro. indicates that there are no additional vcs of low priority with extended capabilities. 3 reserved 2:0 extended vc count (evc) ? ro. indicates that there is one additional vc (vc1) that exists with extended capabilities. bit description 31:24 vc arbitration table offset (ato) ? ro. in dicates that no table is present for vc arbitration since it is fixed. 23:8 reserved 7:0 vc arbitration capability (ac) ? ro. indicate s that the vc arbitration is fixed in the root complex. intel ? ich8 family datasheet 269 chipset configuration registers 7.1.4 pvc?port virtual ch annel control register offset address: 000c?000dh attribute: r/w, ro default value: 0000h size: 16-bit 7.1.5 pvs?port virtual channel status register offset address: 000e?000fh attribute: ro default value: 0000h size: 16-bit 7.1.6 v0cap?virtual channel 0 resource capability register offset address: 0010?0013h attribute: ro default value: 00000001h size: 32-bit bit description 15:04 reserved 3:1 vc arbitration select (as) ? ro. indicate s which vc should be programmed in the vc arbitration table. the root complex takes no action on the setting of this field since there is no arbitration table. 0 load vc arbitration table (lat) ? ro. in dicates that the table programmed should be loaded into the vc arbitration table. this bit is defined as read/write with always returning 0 on reads. bit description 15:01 reserved 0 vc arbitration table status (vas) ? ro. indicates the coherency status of the vc arbitration table when it is being updated. this field is always 0 in the root complex since there is no vc arbitration table. bit description 31:24 port arbitration table offset (at) ? ro. this vc implements no po rt arbitration table since the arbitration is fixed. 23 reserved 22:16 maximum time slots (mts) ? ro. this vc implements fixed arbitration, and therefore this field is not used. 15 reject snoop transactions (rts) ? ro. this vc must be able to take snoopable transactions. 14 advanced packet switching (aps) ? ro. this vc is capable of all transactions, not just advanced packet switching transactions. 13:8 reserved 7:0 port arbitration capability (pac) ? ro. in dicates that this vc uses fixed port arbitration. chipset configuration registers 270 intel ? ich8 family datasheet 7.1.7 v0ctl?virtual channel 0 resource control register offset address: 0014?0017h attribute: r/w, ro default value: 800000ffh size: 32-bit 7.1.8 v0sts?virtual channel 0 resource status register offset address: 001a?001bh attribute: ro default value: 0000h size: 16-bit bit description 31 virtual channel enable (en) ? ro. always set to 1. vc0 is always enabled and cannot be disabled. 30:27 reserved 26:24 virtual channel identifier (id) ? ro. indi cates the id to use for this virtual channel. 23:20 reserved 19:17 port arbitration select (pas) ? r/w. indicates which port table is being programmed. the root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. 16 load port arbitration table (lat) ? ro. the root complex does not implement an arbitration table for this virtual channel. 15:8 reserved 7:1 transaction class / virtual channel map (tvm) ? r/w. indicates which transaction classes are mapped to this virt ual channel. when a bit is set, this transaction class is mapped to the virtual channel. 0 reserved bit description 15:02 reserved 1 vc negotiation pending (np) ? ro. when set, indicates the virtual channel is still being negotiated wi th ingress ports. 0 port arbitration tables status (ats) ? ro. there is no port arbitration table for this vc, so this bit is reserved at 0. intel ? ich8 family datasheet 271 chipset configuration registers 7.1.9 v1cap?virtual channel 1 resource capability register offset address: 001c?001fh attribute: r/wo, ro default value: 30008010h size: 32-bit 7.1.10 v1ctl?virtual channel 1 resource control register offset address: 0020?0023h attribute: r/w, ro default value: 00000000h size: 32-bit bit description 31:24 port arbitration table offset (at) ? ro. indi cates the location of the port arbitration table in the root complex. a value of 3h indicates the table is at offset 30h. 23 reserved 22:16 maximum time slots (mts) ? r/wo. this value is updated by platform bios based upon the determination of the number of time slots available in the platform. 15 reject snoop transactions (rts) ? ro. all snoopable transactions on vc1 are rejected. this vc is for isochronous transfers only. 14 advanced packet switching (aps) ? ro. this vc is capable of all transactions, not just advanced packet switching transactions. 13:8 reserved 7:0 port arbitration capability (pac) ? ro. indi cates the port arbitration capability is time-based wrr of 128 phases. bit description 31 virtual channel enable (en) ? r/w. enables the vc when set. disables the vc when cleared. 30:27 reserved 26:24 virtual channel identifier (id) ? r/w. indicates the id to use for this virtual channel. 23:20 reserved 19:17 port arbitration select (pas) ? r/w. indicates which port table is being programmed. the only permissible value of this field is 4h for the time-based wrr entries. 16 load port arbitration table (lat) ? ro/w. when set, the port arbitration table loaded based upon the pas field in this regi ster. this bit always returns 0 when read. 15:8 reserved 7:1 transaction class / virtual channel map (tvm) ? r/w. indicates which transaction classes are mapped to this virtual channel. when a bit is set, this transaction class is mapped to the virtual channel. 0 reserved chipset configuration registers 272 intel ? ich8 family datasheet 7.1.11 v1sts?virtual channel 1 resource status register offset address: 0026?0027h attribute: ro default value: 0000h size: 16-bit 7.1.12 pat?port arbitration table offset address: 0030?006fh attribute: default value: size: 64-byte this is a 64-byte register that contains the arbitration table to be loaded into the port arbitration table. every 4-bits contains an entry for one of the downstream pci-express ports or a 0h to indicate idle. the ports are mapped as follows: ? port 1: value used is 1h. ? port 2: value used is 2h. ? port 3: value used is 3h ? port 4: value used is 4h ? port 5: value used is 5h ? port 6: value used is 6h ? intel ? high definition audio: value used is fh this table is copied to an internal structure used during port arbitration when v1ctl.pas is set to 04h, and v1ctl.lat is set to 1. 7.1.13 cir1?chipset init ialization register 1 offset address: 0088?008bh attribute: r/wo, ro default value: 00000000h size: 32-bit bit description 15:02 reserved 1 vc negotiation pending (np) ? ro. when set, indicates the virtual channel is still being negotiated wi th ingress ports. 0 port arbitration tables status (ats) ? ro. indicates the coherency status of the port arbitration table. this bit is set when lat (offset 000 ch:bit 0) is written with value 1 and pas (offset 0014h:bits19:17) has value of 4h. this bit is cleared after the table has been updated. bit description 31:21 reserved 20 cir1 field 3 ? r/wo. bios must set this bit. 19:16 reserved 15 cir1 field 2 ? r/wo. bios must set this bit. 14:13 reserved 12 cir1 field 1 ? r/wo. bios must set this bit. 11:0 reserved intel ? ich8 family datasheet 273 chipset configuration registers 7.1.14 rctcl?root complex topolo gy capabilities list register offset address: 0100?0103h attribute: ro default value: 1a010005h size: 32-bit 7.1.15 esd?element self description register offset address: 0104?0107h attribute: r/wo, ro default value: 00000602h size: 32-bit 7.1.16 uld?upstream link descriptor register offset address: 0110?0113h attribute: r/wo, ro default value: 00000001h size: 32-bit bit description 31:20 next capability (next) ? ro. indicates the next item in the list. 19:16 capability version (cv) ? ro. indicate s the version of the capability structure. 15:0 capability id (cid) ? ro. indica tes this is a pci express* li nk capability section of an rcrb. bit description 31:24 port number (pn) ? ro. a value of 0 to indicate the egress port for the intel ? ich. 23:16 component id (cid) ? r/wo. this field indicates the component id assigned to this element by software. this is written on ce by platform bios and is locked until a platform reset. 15:8 number of link entries (nle) ? ro. this field indicates that one link entry (corresponding to dmi), 6 root port entr ies (for the downstre am ports), and the intel ? high definition audio device are described by this rcrb. 7:4 reserved 3:0 element type (et) ? ro. this field indicates that the element type is a root complex internal link. bit description 31:24 target port number (pn) ? r/wo. this field is programmed by platform bios to match the port number of the (g)mch rcrb that is attached to this rcrb. 23:16 target component id (tcid) ? r/wo. this field is programmed by platform bios to match the component id of the (g)mch rcrb that is attached to this rcrb. 15:2 reserved 1 link type (lt) ? ro. this field indicates that the link points to the (g)mch rcrb. 0 link valid (lv) ? ro. this field indicates that the link entry is valid. chipset configuration registers 274 intel ? ich8 family datasheet 7.1.17 ulba?upstream link base address register offset address: 0118?011fh attribute: r/wo default value: 0000000000000000h size: 64-bit 7.1.18 rp1d?root port 1 descriptor register offset address: 0120?0123h attribute: r/wo, ro default value: 01xx0002h size: 32-bit 7.1.19 rp1ba?root port 1 base address register offset address: 0128?012fh attribute: ro default value: 00000000000e0000h size: 64-bit bit description 63:32 base address upper (bau) ? r/wo. this field is progra mmed by platform bios to match the upper 32-bits of base address of the (g)mch rcrb that is attached to this rcrb. 31:0 base address lower (bal) ? r/wo. this field is progra mmed by platform bios to match the lower 32-bits of base address of the (g)mch rcrb that is attached to this rcrb. bit description 31:24 target port number (pn) ? ro. indicates th e target port number is 1h (root port #1). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. indicates that the link points to a root port. 0 link valid (lv) ? ro. when fd.pe1d (offs et 3418h, bit 16) is set, this link is not valid (returns 0). when fd.pe1d is clea red, this link is valid (returns 1). bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. indica tes the root port is on bus #0. 19:15 device number (dn) ? ro. indicate s the root port is on device #28. 14:12 function number (fn) ? ro. indicate s the root port is on function #0. 11:0 reserved intel ? ich8 family datasheet 275 chipset configuration registers 7.1.20 rp2d?root port 2 descriptor register offset address: 0130?0133h attribute: r/wo, ro default value: 02xx0002h size: 32-bit 7.1.21 rp2ba?root port 2 base address register offset address: 0138?013fh attribute: ro default value: 00000000000e1000h size: 64-bit 7.1.22 rp3d?root port 3 descriptor register offset address: 0140?0143h attribute: r/wo, ro default value: 03xx0002h size: 32-bit bit description 31:24 target port number (pn) ? ro. indicates th e target port number is 2h (root port #2). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, sinc e the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. indicates that the link points to a root port. 0 link valid (lv) ? ro. when rpc.pc (offset 0224h, bits 1:0) is ?01?, ?10?, or ?11?, or fd.pe2d (offset 3418h, bit 17) is set, the link for this root port is not valid (return 0). when rpc.pc is ?00? and fd.pe2d is cleared, the link for this root port is valid (return 1). bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. indicate s the root port is on bus #0. 19:15 device number (dn) ? ro. indicate s the root port is on device #28. 14:12 function number (fn) ? ro. indicate s the root port is on function #1. 11:0 reserved bit description 31:24 target port number (pn) ? ro. indicates th e target port number is 3h (root port #3). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, sinc e the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. indicates that the link points to a root port. 0 link valid (lv) ? ro. when rpc.pc (offset 0224h, bits 1:0) is ?11?, or fd.pe3d (offset 3418h, bit 18) is set, the link for this root port is not valid (return 0). when rpc.pc is ?00?, ?01?, or ?10?, and fd.pe3d is cleared, the link for this root port is valid (return 1). chipset configuration registers 276 intel ? ich8 family datasheet 7.1.23 rp3ba?root port 3 base address register offset address: 0148?014fh attribute: ro default value: 00000000000e2000h size: 64-bit 7.1.24 rp4d?root port 4 descriptor register offset address: 0150?0153h attribute: r/wo, ro default value: 04xx0002h size: 32-bit 7.1.25 rp4ba?root port 4 base address register offset address: 0158?015fh attribute: ro default value: 00000000000e3000h size: 64-bit bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. indica tes the root port is on bus #0. 19:15 device number (dn) ? ro. indicate s the root port is on device #28. 14:12 function number (fn) ? ro. indicate s the root port is on function #2. 11:0 reserved bit description 31:24 target port number (pn) ? ro. indicates th e target port number is 4h (root port #4). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. indicates that the link points to a root port. 0 link valid (lv) ? ro. when rpc.pc (offset 0224h, bits 1:0) is ?10? or ?11?, or fd.pe4d (offset 3418h, bit 19) is set, the link for this root port is not valid (return 0). when rpc.pc is ?00? or ?01? and fd.pe4d is cl eared, the link for this root port is valid (return 1). bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. indica tes the root port is on bus #0. 19:15 device number (dn) ? ro. indicate s the root port is on device #28. 14:12 function number (fn) ? ro. indicate s the root port is on function #3. 11:0 reserved intel ? ich8 family datasheet 277 chipset configuration registers 7.1.26 hdd?intel ? high definition audi o descriptor register offset address: 0160?0163h attribute: r/wo, ro default value: 15xx0002h size: 32-bit 7.1.27 hdba?intel ? high definition audi o base address register offset address: 0168?016fh attribute: ro default value: 00000000000d8000h size: 64-bit 7.1.28 rp5d?root port 5 descriptor register offset address: 0170?0173h attribute: r/wo, ro default value: 05xx0002h size: 32-bit bit description 31:24 target port number (pn) ? ro. indicate s the target port number is 15h (intel ? high definition audio). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, sinc e the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. indicates that the link points to a root port. 0 link valid (lv) ? ro. when fd.zd (offset 3418h, bit 4) is set, the link to intel high definition audio is not valid (return 0). when fd.zd is cleared, the link to intel high definition audio is valid (return 1). bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. indicate s the root port is on bus #0. 19:15 device number (dn) ? ro. indicate s the root port is on device #27. 14:12 function number (fn) ? ro. indicate s the root port is on function #0. 11:0 reserved bit description 31:24 target port number (pn) ? ro. indicates th e target port number is 5h (root port #5). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, sinc e the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. indicates that the link points to a root port. 0 link valid (lv) ? ro. when fd.pe5d (offset 3418h, bit 20) is set, the link for this root port is not valid (return 0). when fd.pe5d is cleared, the link for this root port is valid (return 1). chipset configuration registers 278 intel ? ich8 family datasheet 7.1.29 rp5ba?root port 5 base address register offset address: 0178?017fh attribute: ro default value: 00000000000e4000h size: 64-bit 7.1.30 rp6d?root port 6 descriptor register offset address: 0180?0183h attribute: r/wo, ro default value: 06xx0002h size: 32-bit 7.1.31 rp6ba?root port 6 base address register offset address: 0188?018fh attribute: ro default value: 00000000000e5000h size: 64-bit bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. indica tes the root port is on bus #0. 19:15 device number (dn) ? ro. indicate s the root port is on device #28. 14:12 function number (fn) ? ro. indicate s the root port is on function #4. 11:0 reserved bit description 31:24 target port number (pn) ? ro. indicates th e target port number is 6h (root port #6). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. indicates that the link points to a root port. 0 link valid (lv) ? ro. when rpc.pc2 (offset 0224h, bits 1:0) is ?01? or fd.pe6d (offset 3418h, bit 21) is set, the link for th is root port is not valid (return 0). when rpc.pc is ?00? and fd.pe6d is cleared, the link for this r oot port is valid (return 1). bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. indica tes the root port is on bus 0. 19:15 device number (dn) ? ro. indicate s the root port is on device 28. 14:12 function number (fn) ? ro. indica tes the root port is on function 5. 11:0 reserved intel ? ich8 family datasheet 279 chipset configuration registers 7.1.32 ilcl?internal link ca pabilities list register offset address: 01a0?01a3h attribute: ro default value: 00010006h size: 32-bit 7.1.33 lcap?link capabilities register offset address: 01a4?01a7h attribute: ro/ r/wo default value: 00012441h size: 32-bit bit description 31:20 next capability offset (next) ? ro. indicates this is the last item in the list. 19:16 capability version (cv) ? ro. indicate s the version of the capability structure. 15:0 capability id (cid) ? ro. indica tes this is capability for dmi. bit description 31:18 reserved 17:15 l1 exit latency (el1) ? l1 not supported on dmi. 14:12 l0s exit latency (el0) ? r/wo. this field indicates that exit latency is 128 ns to less than 256 ns. 11:10 (desktop only) reserved 11:10 (mobile only) active state link pm support (apms) ? r/ wo. indicates that l0s is supported on dmi. 9:4 maximum link width (mlw) ? indicate s the maximum link width is 4 ports. 3:0 maximum link speed (mls) ? indicates the link speed is 2.5 gb/s. chipset configuration registers 280 intel ? ich8 family datasheet 7.1.34 lctl?link control register offset address: 01a8?01a9h attribute: r/w default value: 0000h size: 16-bit 7.1.35 lsts?link status register offset address: 01aa?01abh attribute: ro default value: 0041h size: 16-bit 7.1.36 cir2 ? chipset initialization register 2 offset address: 01f4?01f7h attribute: r/w default value: 00000000h size: 32-bit bit description 15:8 reserved 7 extended synch (es) ? r/w. when set, forces ex tended transmission of fts ordered sets when exiting l0s prior to entering l0. 6:2 reserved 1:0 (desktop only) reserved 1:0 (mobile only) active state link pm control (apmc) ? r/w. indicates whether dmi should enter l0s. 00 = disabled 01 = l0s entry enabled 10 = reserved 11 = reserved bit description 15:10 reserved 9:4 negotiated link width (nlw) ? ro. negotiated link width is x4 (000100b). ich8m may also indicate x2 (000010b), depending on (g)mch configuration. 3:0 link speed (ls) ? ro. link is 2.5 gb/s. bit description 31:0 cir2 field 1 ? r/w. bios shall program to 86000040h intel ? ich8 family datasheet 281 chipset configuration registers 7.1.37 cir3 ? chipset initialization register 3 offset address: 01fc?01fdh attribute: r/w, ro default value: 0000h size: 16-bit 7.1.38 cir4 ? chipset initialization register 4 offset address: 0200?0201h attribute: r/w, ro default value: 0000h size: 16-bit 7.1.39 bcr ? backbone co nfiguration register offset address: 0220?0223h attribute: r/w default value: 00000000h size: 32-bit bit description 15:11 reserved 10:8 cir3 field 3 ? r/w. bios must program this field to 110b. 7:4 reserved 3 cir3 field 2 ? r/w. bios must set this bit. 2 reserved 1:0 cir3 field 1 ? r/w. bios must program this field to 11b. bit description 15:14 reserved 13:8 cir4 field 2 ? r/w. bios must program this field to 10 0000b 7:6 reserved 5:0 cir4 field 1 ? r/w. bios must program this field to 00 1000b. bit description 31:7 reserved 6 bcr field 2 ? r/w. bios must set this bit. 5:3 reserved 2:0 bcr field 1 ? r/w. bios program this field to 101b chipset configuration registers 282 intel ? ich8 family datasheet 7.1.40 rpc?root port configuration register offset address: 0224?0227h attribute: r/w, ro default value: 0000000yh (y = 00xxb) size: 32-bit 7.1.41 dmic?dmi control register offset address: 0234?0237h attribute: r/w, ro default value: 00000000h size: 32-bit bit description 31:8 reserved 7 high priority port enable (hpe) ? r/w. 0 = the high priority path is not enabled. 1 = the port selected by the hpp field in this register is enabled for high priority. it will be arbitrated above all other vc0 (including integrated vc0) devices. 6:4 high priority port (hpp) ? r/w. this controls whic h port is enabled for high priority when the hpe bit in this register is set. 111 = reserved 110 = reserved 101 = port 6 100 = port 5 101 = port 4 010 = port 3 001 = port 2 000 = port 1 3 reserved 2 port configuration2 (pc2) ? ro. this controls how the pci bridges are organized in various modes of operation for ports 5 and 6. 1 = reserved 0 = 2 x1s, port 5 (x1), port 6 (x1) this bit is in the resume well and is only reset by rsmrst#. 1:0 port configuration (pc) ? ro. this field controls how the pci bridges are organized in various modes of operation for ports 1?4. for the following mappings, if a port is not shown, it is considered a x1 port with no connection. these bits represent the strap values of hda_sdout (bit 1) and hda_sync (bit 0) when tp[3] is not pulled low at the rising edge of pwrok. 11 = 1 x4, port 1 (x4) 10 = reserved 01 = 1 x2 & 2 x1s, port 1 (x2), port 3 (x1), port 4 (x1) 00 = 4 x1s, port 1 (x1), port 2 (x1), port 3 (x1), port 4 (x1) these bits live in the resume we ll and are only reset by rsmrst#. bit description 31:2 reserved 1:0 dmi clock gate enable (dmicgen) ? r/w. bios must program this field to 00b (desktop) or 11b (mobile only) intel ? ich8 family datasheet 283 chipset configuration registers 7.1.42 rpfn?root port function number for pci express* root ports offset address: 0238?1e03h attribute: r/wo, ro default value: 00543210h size: 32-bit for the pci express root ports, the assignment of a function number to a root port is not fixed. bios may re-assign the function numbers on a port by port basis. this capability will allow bios to disable/hide any root port and have still have functions 0 thru n-1 where n is the total number of enabled root ports. port numbers will remain fixed to a physical root port. the existing root port function disable registers operate on physical ports (not functions). port configuration (1x4, 4x1, etc.) is no t affected by the logical function number assignment and is associated with physical ports. bit description 31:23 reserved 22:20 root port 6 function number (rp6fn) ? r/wo. these bits set the function number for pci express root port 6. this root port function number must be a unique value from the other r oot port function numbers 19 reserved 18:16 root port 5 function number (rp5fn) ? r/wo. these bits set the function number for pci express root port 5. this root port function number must be a unique value from the other r oot port function numbers 15 reserved 14:12 root port 4 function number (rp4fn) ? r/wo. these bits set the function number for pci express root port 4. this root port function number must be a unique value from the other r oot port function numbers 11 reserved 10:8 root port 3 function number (rp3fn) ? r/wo. these bits set the function number for pci express root port 3. this root port function number must be a unique value from the other r oot port function numbers 7 reserved 6:4 root port 2 function number (rp2fn) ? r/wo. these bits set the function number for pci express root port 2. this root port function number must be a unique value from the other r oot port function numbers 3 reserved 2:0 root port 1 function number (rp1fn) ? r/wo. these bits set the function number for pci express root port 1. this root port function number must be a unique value from the other r oot port function numbers chipset configuration registers 284 intel ? ich8 family datasheet 7.1.43 cir5?chipset init ialization register 5 offset address: 1d40h?1d47h attribute: r/w, r/wl default value: 0000000000000000h size: 64-bit 7.1.44 trsr?trap status register offset address: 1e00?1e03h attribute: r/wc, ro default value: 00000000h size: 32-bit 7.1.45 trcr?trapped cycle register offset address: 1e10?1e17h attribute: ro default value: 0000000000000000h size: 64-bit this register saves information about the i/o cycle that was trapped and generated the smi# for software to read. bit description 63:1 reserved 0 cir5 field 1 ? r/w. bios must program this field to 1b bit description 31:4 reserved 3:0 cycle trap smi# status (ctss) ? r/wc. these bits are set by hardware when the corresponding cycle trap register is enable d and a matching cycle is received (and trapped). these bits are or?ed together to create a single status bit in the power management register space. note that the smi# and trapping must be enabled in order to set these bits. these bits are set before the completion is generated for the trapped cycle, thereby assuring that the processor can enter the smi# handler wh en the instruction completes. each status bit is cleared by writing a 1 to th e corresponding bit location in this register. bit description 63:25 reserved 24 read/write# (rwi) ? ro. 0 = trapped cycle was a write cycle. 1 = trapped cycle was a read cycle. 23:20 reserved 19:16 active-high byte enables (ahbe) ? ro. this is the dword-aligned byte enables associated with the trapped cycle. a 1 in any bit location indicates that the corresponding byte is enabled in the cycle. 15:2 trapped i/o address (tioa) ? ro. this is the dword-aligned address of the trapped cycle. 1:0 reserved intel ? ich8 family datasheet 285 chipset configuration registers 7.1.46 twdr?trapped write data register offset address: 1e18?1e1fh attribute: ro default value: 0000000000000000h size: 64-bit this register saves the data from i/o write cycles that are trapped for software to read. 7.1.47 iotrn ? i/o trap register (0?3) offset address: 1e80?1e87h register 0 attribute: r/w, ro 1e88?1e8fh register 1 1e90?1e97h register 2 1e98?1e9fh register 3 default value: 0000000000000000h size: 64-bit these registers are used to specify the set of i/o cycles to be trapped and to enable this functionality. bit description 63:32 reserved 31:0 trapped i/o data (tiod) ? ro. dword of i/o write data. this field is undefined after trapping a read cycle. bit description 63:50 reserved 49 read/write mask (rwm) ? r/w. 0 = the cycle must match the type specified in bit 48. 1 = trapping logic will operate on both read and write cycles. 48 read/write# (rwio) ? r/w. 0 = write 1 = read note: the value in this field does not matter if bit 49 is set. 47:40 reserved 39:36 byte enable mask (bem) ? r/w. a 1 in any bit position indicates that any value in the corresponding byte enable bit in a received cycle will be treated as a match. the corresponding bit in the byte en ables field, below, is ignored. 35:32 byte enables (tbe) ? r/w. active-high dword-aligned byte enables. 31:24 reserved 23:18 address[7:2] mask (adma) ? r/w. a 1 in any bit position indicates that any value in the corresponding address bit in a receiv ed cycle will be treated as a match. the corresponding bit in the addres s field, below, is ignored. the mask is only provided for the lower 6 bits of the dw ord address, allowing for trap s on address ranges up to 256 bytes in size. 17:16 reserved 15:2 i/o address[15:2] (ioad) ? r/w. dword-aligned address 1 reserved 0 trap and smi# enable (trse) ? r/w. 0 = trapping and smi# logic disabled. 1 = the trapping logic specified in this register is enabled. chipset configuration registers 286 intel ? ich8 family datasheet 7.1.48 dmc?dmi miscellaneous co ntrol register (mobile only) offset address: 2010?2013h attribute: r/w default value: na size: 32-bit 7.1.49 cir6?chipset initializati on register 6 (mobile only) offset address: 2024?2027h attribute: r/w, ro default value: 0b2030xxh size: 32-bit 7.1.50 cir7?chipset init ialization register 7 offset address: 2034?2037h attribute: r/w default value: b2b477cch size: 32-bit bit description 31:2 reserved 1 dmi misc. control field 1 ? r/w. bios shall always program this field as per the bios specification. 0 = disable dmi power savings. 1 = enable dmi power savings. 0 reserved bit description 31:24 reserved 23:21 cir6 field 2 ? r/w. (mobile only) bios must program this field to 011b. 20:8 reserved 7 cir6 field 1 ? r/w. bios must clear this bit. 6:0 reserved bit description 31:20 reserved 19:16 cir7 field 1 ? r/w. bios must program this field to 0101b. 15:0 reserved intel ? ich8 family datasheet 287 chipset configuration registers 7.1.51 tctl?tco configuration register offset address: 3000?3000h attribute: r/w default value: 00h size: 8-bit bit description 7 tco irq enable (ie) ? r/w. 0 = tco irq is disabled. 1 = tco irq is enabled, as sele cted by the tco_irq_sel field. 6:3 reserved 2:0 tco irq select (is) ? r/w. specifies on which irq the tco will internally appear. if not using the apic, the tco interrupt must be routed to irq9-11, and that interrupt is not sharable with the serirq stream, but is shar eable with other pci interrupts. if using the apic, the tco inte rrupt can also be mapped to irq20-23, and can be shared with other interrupt. 000 = irq 9 001 = irq 10 010 = irq 11 011 = reserved 100 = irq 20 (only if apic enabled) 101 = irq 21 (only if apic enabled) 110 = irq 22 (only if apic enabled) 111 = irq 23 (only if apic enabled) when setting the these bits, the ie bit should be cleared to prevent glitching. when the interrupt is mapped to apic interrupts 9, 10 or 11, the apic should be programmed for active-high reception. wh en the interrupt is mapped to apic interrupts 20 through 23, th e apic should be programme d for active-low reception. chipset configuration registers 288 intel ? ich8 family datasheet 7.1.52 d31ip?device 31 in terrupt pin register offset address: 3100?3103h attribute: r/w, ro default value: 03243210h size: 32-bit bit description 31:16 reserved 27:24 thermal throttle pin (ttip) ? r/w. this field indica tes which pin the thermal throttle controller drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 23:20 sata pin 2 (sip2) ? r/w. this field indicates which pin the sata controller 2 drives as its interrupt. 0h = no interrupt. 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 19:16 reserved 15:12 sm bus pin (smip) ? r/w. this field indicates which pin the smbus controller drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 11:8 sata pin (sip) ? r/w. this field indicates which pin the sata controller drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 7:4 pata pin (smip) ? r/w. this field indicates which pin the pata controller drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved 3:0 lpc bridge pin (pip) ? ro. currently, the lpc bridge does not gene rate an interrupt, so this field is read-only and 0. intel ? ich8 family datasheet 289 chipset configuration registers 7.1.53 d30ip?device 30 in terrupt pi n register offset address: 3104?3107h attribute: r/w, ro default value: 00000000h size: 32-bit 7.1.54 d29ip?device 29 in terrupt pi n register offset address: 3108?310bh attribute: r/w default value: 10004321h size: 32-bit bit description 31:4 reserved 3:0 pci bridge pin (lip) ? ro. currently, the pc i bridge does not generate an interrupt, so this field is read-only and 0. bit description 31:28 ehci pin (eip) ? r/w. this field indicates which pin the ehci contro ller drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved 27:12 reserved 11:8 uhci #2 pin (u2p) ? r/w. this field indicates wh ich pin the uhci controller #2 (ports 4 and 5) drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# (default) 4h = intd# 5h?7h = reserved 7:4 uhci #1 pin (u1p) ? r/w. this field indicates wh ich pin the uhci controller #1 (ports 2 and 3) drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 3:0 uhci #0 pin (u0p) ? r/w. this field indicates wh ich pin the uhci controller #0 (ports 0 and 1) drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved chipset configuration registers 290 intel ? ich8 family datasheet 7.1.55 d28ip?device 28 in terrupt pin register offset address: 310c?310fh attribute: r/w default value: 00214321h size: 32-bit bit description 31:16 reserved 23:20 pci express* #6 pin (p6ip) ? r/w. this field indicates which pin the pci express* port #6 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 19:16 pci express #5 pin (p5ip) ? r/w. this field indicates which pin the pci express port #5 drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved 15:12 pci express #4 pin (p4ip) ? r/w. this field indicate s which pin the pci express* port #4 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# 4h = intd# (default) 5h?7h = reserved 11:8 pci express #3 pin (p3ip) ? r/w. this field indicates which pin the pci express port #3 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# (default) 4h = intd# 5h?7h = reserved 7:4 pci express #2 pin (p2ip) ? r/w. this field indicates which pin the pci express port #2 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 3:0 pci express #1 pin (p1ip) ? r/w. this field indicates which pin the pci express port #1 drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved intel ? ich8 family datasheet 291 chipset configuration registers 7.1.56 d27ip?device 27 in terrupt pi n register offset address: 3110?3113h attribute: r/w default value: 00000001h size: 32-bit 7.1.57 d26ip?device 26 in terrupt pi n register offset address: 3114?3117h attribute: r/w, ro default value: 30000021h size: 32-bit bit description 31:4 reserved 3:0 intel ? high definition audio pin (zip) ? r/w. this field indicates which pin the intel high definition audio cont roller drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved bit description 31:28 ehci #2 pin (e2ip): this field indicates which pin th e ehci controller #2 drives as its interrupt: 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# (default) 4h = intd# 5h?fh = reserved 27:8 reserved 7:4 uhci #5 pin (u5p): this field applies to uhci controller #5 (ports 8 & 9) 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 3:0 uhci #4 pin (u4p): this field applies to uhci controller #4 (ports 6 and 7) 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved chipset configuration registers 292 intel ? ich8 family datasheet 7.1.58 d25ip?device 25 in terrupt pin register offset address: 3118?3121h attribute: ro, r/w default value: 00000001h size: 32-bit 7.1.59 d31ir?device 31 interrupt route register offset address: 3140?3141h attribute: r/w default value: 3210h size: 16-bit bit description 31:4 reserved 3:0 igbe lan pin (lip): this field indicates which pin the internal gbe lan controller drives as its interrupt 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicate s which physical pin on the intel ? ich8 is connected to the intd# pin reported fo r device 31 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intc# pin reported for device 31 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7:4 reserved 3 netdetect enable (nde) ? r/w. this register is in the rtc well instead of the sus well to maintain state if the su s well power is removed in s4. 0 = disabled 1 = gpio14 input signal is multiplexed onto the south mlink mlclk pin as a netdetect request signal to the wireless lan component. intel ? ich8 family datasheet 293 chipset configuration registers 7.1.60 d30ir?device 30 in terrupt route register offset address: 3142?3143h attribute: ro default value: 0000h size: 16-bit 7.1.61 d29ir?device 29 in terrupt route register offset address: 3144?3145h attribute: r/w default value: 3210h size: 16-bit 2:0 interrupt a pin route (iar) ? r/w. this field indicate s which physical pin on the ich8 is connected to the inta# pi n reported for device 31 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# bit description bit description 15:0 reserved. no interrupt s generated from device 30 bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicate s which physical pin on the intel ? ich8 is connected to the intd# pi n reported for device 29 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intc# pi n reported for device 29 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# chipset configuration registers 294 intel ? ich8 family datasheet 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intb# pin reported for device 29 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicate s which physical pin on the ich8 is connected to the inta# pin reported for device 29 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# bit description intel ? ich8 family datasheet 295 chipset configuration registers 7.1.62 d28ir?device 28 in terrupt route register offset address: 3146?3147h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicate s which physical pin on the intel ? ich8 is connected to the intd# pi n reported for device 28 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intc# pi n reported for device 28 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intb# pi n reported for device 28 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicate s which physical pin on the ich8 is connected to the inta# pi n reported for device 28 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# chipset configuration registers 296 intel ? ich8 family datasheet 7.1.63 d27ir?device 27 interrupt route register offset address: 3148?3149h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicate s which physical pin on the intel ? ich8 is connected to the intd# pin reported for device 27 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intc# pin reported for device 27 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intb# pin reported for device 27 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicate s which physical pin on the ich8 is connected to the inta# pin reported for device 27 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# intel ? ich8 family datasheet 297 chipset configuration registers 7.1.64 d26ir?device 26 in terrupt route register offset address: 314c?314dh attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) : this field indicates which physical pin on the ich8 is connected to the intd# pin repo rted for device 26 functions: 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intc# pi n reported for device 26 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intb# pi n reported for device 26 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicate s which physical pin on the ich8 is connected to the inta# pi n reported for device 26 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# chipset configuration registers 298 intel ? ich8 family datasheet 7.1.65 d25ir?device 25 interrupt route register offset address: 3150?3151h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr): this field indicates which ph ysical pin on the ich8 is connected to the intd# pin repo rted for device 25 functions: 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intc# pin reported for device 25 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicate s which physical pin on the ich8 is connected to the intb# pin reported for device 25 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicate s which physical pin on the ich8 is connected to the inta# pin reported for device 25 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# intel ? ich8 family datasheet 299 chipset configuration registers 7.1.66 oic?other interr upt control register offset address: 31ff?31ffh attribute: r/w default value: 00h size: 8-bit 7.1.67 rc?rtc configuration register offset address: 3400?3403h attribute: r/w, r/wlo default value: 00000000h size: 32-bit bit description 7:4 apic range select (asel): these bits define addres s bits 15:12 for the ioxapic range. the default value of 0h enables comp atibility with prior ich8 products as an initial value. this value must not be changed unless the ioxapic enable bit is cleared. 3:2 reserved 1 coprocessor error enable (cen) ? r/w. 0 = ferr# will not generate irq13 nor ignne#. 1 = if ferr# is low, the intel ? ich8 generates irq13 internally and holds it until an i/o port f0h write. it will also drive ignne# active. 0 apic enable (aen) ? r/w. 0 = the internal ioxapic is disabled. 1 = enables the internal ioxa pic and its a ddress decode. note: software should read this register after modifying apic enable bit prior to access to the ioxapic address range. bit description 31:5 reserved 4 upper 128 byte lock (ul) ? r/wlo. 0 = bytes not locked. 1 = bytes 38h-3fh in the upper 128-byte ba nk of rtc ram are locked and cannot be accessed. writes will be dr opped and reads will not return any assured data. bit reset on system reset. 3 lower 128 byte lock (ll) ? r/wlo. 0 = bytes not locked. 1 = bytes 38h-3fh in the lower 128-byte ba nk of rtc ram are locked and cannot be accessed. writes will be dr opped and reads will not return any assured data. bit reset on system reset. 2 upper 128 byte enable (ue) ? r/w. 0 = bytes locked. 1 = the upper 128-byte bank of rtc ram can be accessed. 1:0 reserved chipset configuration registers 300 intel ? ich8 family datasheet 7.1.68 hptc?high precision timer configuration register offset address: 3404?3407h attribute: r/w default value: 00000000h size: 32-bit bit description 31:8 reserved 7 address enable (ae) ? r/w. 0 = address disabled. 1 = the intel ? ich8 will decode the high precision timer memory address range selected by bits 1:0 below. 6:2 reserved 1:0 address select (as) ? r/w. this 2-bit field selects 1 of 4 possible memory address ranges for the high precision time r functionality. the encodings are: 00 = fed0_0000h - fed0_03ffh 01 = fed0_1000h - fed0_13ffh 10 = fed0_2000h - fed0_23ffh 11 = fed0_3000h - fed0_33ffh intel ? ich8 family datasheet 301 chipset configuration registers 7.1.69 gcs?general control and status register offset address: 3410?3413h attribute: r/w, r/wlo default value: 00000yy0h (yy = xx0000x0b) size: 32-bit bit description 31:12 reserved 11:10 boot bios straps (bbs): this field determines the destination of accesses to the bios memory range. the default values for these bits represent the strap values of gnt0# (bit 11) and spi_cs1# (bit 10) at the rising edge of pwrok. when pci is selected, the top 16mb of memory below 4gb (ff00_0000h to ffff_ffffh) is accepted by the primary si de of the pci p2p bridge and forwarded to the pci bus. this allows systems with corrupted or unprogrammed flash to boot from a pci device. the pci-to-pci bridge memory space enable bit does not need to be set (nor any other bits) in order for these cycles to go to pci. note that bios decode range bits and the other bios protec tion bits have no effect when pci is selected. when spi or lpc is selected, the range that is decoded is further qualified by other configuration bits described in the respective sections. the value in this field can be overwritten by software as long as the bios interface lock-down (bit 0) is not set. note: boot bios destination select to lpc/pci by functional strap or via boot bios destination bit will not affect spi accesses initiated by me or integrated gbe lan. 9 server error reporting mode (serm) ? r/w. 0 = the intel ? ich8 is the final target of all e rrors. the (g)mch sends a messages to the ich8 for the purpose of generating nmi. 1 = the (g)mch is the final target of all errors from pci express* and dmi. in this mode, if the ich8 detects a fatal, non-fa tal, or correctable error on dmi or its downstream ports, it sends a message to the (g)mch. if the ich8 receives an err_* message from the downstream po rt, it sends that message to the (g)mch. 8 reserved 7 (mobile only) mobile ide configuratio n lock down (micld) ? r/wlo. 0 = disabled. 1 = buc.prs (offset 3414h, bit 1) is locked and cannot be writ ten until a system reset occurs. this prevents rogue software from chan ging the default state of the pata pins during boot after bios co nfigures them. this bit is write once, and is cleared by system reset and wh en returning from th e s3/s4/s5 states. 7:6 (desktop only) reserved 6 (mobile only) ferr# mux enable (fme) ? r/w. this bit enables ferr# to be a processor break event indication. see chapter 5.13.5 for a function al description. 0 = disabled. 1 = the ich8 examines ferr# during a c2, c3, or c4 state as a break event. bits 11:10 description 0xb spi 10b pci 11b lpc chipset configuration registers 302 intel ? ich8 family datasheet 5 no reboot (nr) ? r/w. this bit is set when th e ?no reboot? strap (spkr pin on ich8) is sampled high on pwro k. this bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates ?no reboot?. 0 = system will reboot upon the second timeout of the tco timer. 1 = the tco timer will count down and generate the smi# on the first timeout, but will not reboot on the second timeout. 4 alternate access mode enable (ame) ? r/w. 0 = disabled. 1 = alternate access read only registers can be written, and write only registers can be read. before entering a low power state, several registers from powered down parts may need to be saved. in the majority of cases, this is not an issue, as registers have read and wr ite paths. however, several of the isa compatible registers are either read only or write only. to get data out of write- only registers, and to restore data into read-only registers, the ich8 implements an alternate access mode. for a list of these registers see section 5.13.10 . 3 shutdown policy select (sps) ? r/w. when cleared (default), the ich8 will drive init# in response to the shutdown vendor defined message (vdm). when set to 1, ich8 will treat the shutdown vdm similar to receiving a cf9h i/o write with data value o6h, and will drive pltrst# active. 2 reserved page route (rpr) ? r/w. determines where to send the reserved page registers. these addr esses are sent to pci or lpc for the purpose of generating post codes. the i/o addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8ch, 8dh, and 8eh. 0 = writes will be forwarded to lpc, shad owed within the ich, and reads will be returned from the internal shadow 1 = writes will be forwarded to pci, shadowed within the ich, and reads will be returned from the internal shadow. note, if some writes are done to lpc/pci to these i/o ranges, and then this bit is flipped, such that writes wi ll now go to the other interfa ce, the reads will not return what was last written. shadowing is performed on each interface. the aliases for these register s, at 90h, 94h, 95h, 96h, 98h, 9ch, 9dh, and 9eh, are always decoded to lpc. 1 reserved 0 bios interface lo ck-down (bild) ? r/wlo. 0 = disabled. 1 = prevents buc.ts (offset 3414, bit 0) and gcs.bbs (offset 3410h, bits 11:10) from being changed. this bit can only be written from 0 to 1 once. bit description intel ? ich8 family datasheet 303 chipset configuration registers 7.1.70 buc?backed up control register offset address: 3414?3414h attribute: r/w default value: 0000000xb (desktop) size: 8-bit 0000001xb (mobile) all bits in this register are in the rtc well and only cleared by rtcrst#. 7.1.71 fd?function disable register offset address: 3418?341bh attribute: r/w, ro default value: see bit description size: 32-bit the uhci functions must be disabled from highest function number to lowest within each pci device (device 29 or device 26). for example, if only two uhcis are wanted on device 29, software must disable uhci #3 (ud3 bit set). when disabling uhcis, the ehci structural parameters registers must be updated with coherent information in ?number of companion controllers? and ?n_ports? fields. when disabling a function, only the config uration space is disabled. software must ensure that all functionality within a controller that is not desired (such as memory spaces, i/o spaces, and dma engines) is di sabled prior to disabling the function. when a function is disabled, software must not attempt to re-enable it. a disabled function can only be re-enabled by a platform reset. bit description 7:3 reserved 2 cpu bist enable (cbe) ? r/w. this bit is in the resume well and is reset by rsmrst#, but not pltrst# nor cf9h writes. 0 = disabled. 1 = the init# signals will be driven ac tive when cpurst# is active. init# and init3_3v# will go inactive with the same timings as the other processor interface signals (hold time after cpurst# inactive). 1 (mobile only) pata reset state (prs) ? r/w. 0 = disabled. 1 = the reset state of the pata pins will be driven/tri-state. 1 (desktop only) reserved 0 top swap (ts) ? r/w. 0 = intel ? ich8 will not invert a16. 1 = ich8 will invert a16 for cycles going to the bios space (but not the feature space) in the fwh. if ich8 is strapped for top-swap (gnt3# is low at rising edge of pwrok), then this bit cannot be cleared by software. the strap jumper should be removed and the system rebooted. chipset configuration registers 304 intel ? ich8 family datasheet bit description 31:26 reserved 25 serial ata disable 2 (sad2) ? r/w. default is 0. 0 = the sata controller #2 (d31:f5) is enabled. 1 = the sata controller #2 (d31:f5) is disabled. 24 thermal throttle disable (ttd) ? r/w. default is 0. 0 = thermal throttle is enabled. 1 = thermal throttle is disabled. 23:22 reserved 21 pci express* 6 disable (pe6d) ? r/w. default is 0. when disabled, the link for this port is put into the ?link down? state. 0 = pci express* port #6 is enabled. 1 = pci express port #6 is disabled. 20 pci express 5 disable (pe5d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #5 is enabled. 1 = pci express port #5 is disabled. 19 pci express 4 disable (pe4d) ? r/w. default is 0. when disabled, the link for this port is put into th e ?link down? state. 0 = pci express* port #4 is enabled. 1 = pci express port #4 is disabled. 18 pci express 3 disable (pe3d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #3 is enabled. 1 = pci express port #3 is disabled. 17 pci express 2 disable (pe2d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #2 is enabled. 1 = pci express port #2 is disabled. 16 pci express 1 disable (pe1d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #1 is enabled. 1 = pci express port #1 is disabled. 15 ehci #1 disable (ehci1d) ? r/w. default is 0. 0 = the ehci #1 is enabled. 1 = the ehci #1 is disabled. 14 lpc bridge disable (lbd) ? r/w. default is 0. 0 = the lpc bridge is enabled. 1 = the lpc bridge is disabled. unlike the ot her disables in this register, the following additional spaces will no longer be decoded by the lpc bridge: ? memory cycles below 16 mb (1000000h) ? i/o cycles below 64 kb (10000h) ? the internal i/oxapic at fec0_0000 to fecf_ffff memory cycles in the lpc bios range below 4 gb will still be deco ded when this bit is set, but the aliases at the top of 1 mb (the e and f segment) no longer will be decoded. intel ? ich8 family datasheet 305 chipset configuration registers 13 ehci #2 disable (ehci2d) ? r/w. default is 0. 0 = the ehci #2 is enabled. 1 = the ehci #2 is disabled. note: when this bit is set, the uhci #5 func tion is not available and the uhci #4 must be disabled by setting bit 11 in this register. 12 usb1 #5 disable (u5d) ? r/w. default is 0 0 = the uhci #5 is enabled. 1 = the uhci #5 is disabled. note: when the ehci #2 device disable (ehci2 d) is set, this bit is a don?t care 11 uhci #4 disable (u4d) ? r/w. default is 0. 0 = the 4th uhci (ports 6 and 7) is enabled. 1 = the 4th uhci (ports 6 and 7) is disabled. note: uhci #4 must be disabled when ehci #2 is disabled with bit 13 in this register. 10 uhci #3 disable (u3d) ? r/w. default is 0. 0 = the 3rd uhci (ports 4 and 5) is enabled. 1 = the 3rd uhci (ports 4 and 5) is disabled. 9 uhci #2 disable (u2d) ? r/w. default is 0. 0 = the 2nd uhci (ports 2 and 3) is enabled. 1 = the 2nd uhci (ports 2 and 3) is disabled. 8 uhci #1 disable (u1d) ? r/w. default is 0. 0 = the 1st uhci (ports 0 and 1) is enabled. 1 = the 1st uhci (ports 0 and 1) is disabled. 7:5 reserved 4 intel ? high definition audio disable (zd) ? r/w. default is 0. 0 = the intel high definition audio controller is enabled. 1 = the intel high definition audio controll er is disabled and its pci configuration space is not accessible. 3 sm bus disable (sd) ? r/w. default is 0. 0 = the sm bus controller is enabled. 1 = the sm bus controller is disabled. in ich5 and previous, this also disabled the i/o space. in ich8, it only di sables the configuration space. 2 serial ata disable 1 (sad1) ? r/w. default is 0. 0 = the sata controller #1 (d31:f2) is enabled. 1 = the sata controller #1 (d31:f2) is disabled. 1 reserved 0 bios must set this bit to 0b bit description chipset configuration registers 306 intel ? ich8 family datasheet 7.1.72 cg?clock gating (mobile only) offset address: 341c?341fh attribute: r/w, ro default value: 00000000h size: 32-bit bit description 31 legacy (lpc) dynamic clock gate enable ? r/w. 0 = legacy dynamic clock gating is disabled 1 = legacy dynamic clock gating is enabled 30 pata dynamic clock gate enable ? r/w. 0 = pata dynamic clock gating is disabled 1 = pata dynamic clock gating is enabled 29:28 usb uhci dynamic clock gate enable ? r/w. 0 = usb uhci dynamic clock gating is disabled 1 = usb uhci dynamic clock gating is enabled 0 = reserved 1 = reserved 27 reserved 26 sata port 2 dynamic clock gate enable ? r/w. 0 = sata port 2 dynamic clock gating is disabled 1 = sata port 2 dynamic clock gating is enabled 25 sata port 1 dynamic clock gate enable ? r/w. 0 = sata port 1 dynamic clock gating is disabled 1 = sata port 1 dynamic clock gating is enabled 24 sata port 0 dynamic clock gate enable ? r/w. 0 = sata port 0 dynamic clock gating is disabled 1 = sata port 0 dynamic clock gating is enabled 23 lan static clock gating enable (lanscge) ? r/w. 0 = lan static clock gating is disabled 1 = lan static clock gating is enabled when the lan disable bit is set in the function disable sus well register. 22 high definition audio dynamic clock gate enable ? r/w. 0 = high definition audio dynamic clock gating is disabled 1 = high definition audio dyna mic clock gating is enabled 21 high definition audio static clock gate enable ? r/w. 0 = high definition audio static clock gating is disabled 1 = high definition audio static clock gating is enabled 20 usb ehci static clock gate enable ? r/w. 0 = usb ehci static cl ock gating is disabled 1 = usb ehci static clock gating is enabled 19 usb ehci dynamic clock gate enable ? r/w. 0 = usb ehci dynamic cl ock gating is disabled 1 = usb ehci dynamic clock gating is enabled 18:17 reserved 16 pci dynamic gate enable ? r/w. 0 = pci dynamic gating is disabled 1 = pci dynamic gating is enabled intel ? ich8 family datasheet 307 chipset configuration registers 7.1.73 fdsw?function disable sus well offset address: 3420h attribute: r/w, ro default value: 0000h size: 8-bit 15 ide c3 hv io biasin g disable (ic3hvbd) ? r/w. 0 = ide hv io biasing is always on 1 = ide hv io biasing is disabled on selected pins when in c3. 14:5 reserved 4 pci express* rx clock ga ting enable (prxcgen) ? r/w. 0 = afe rx clock gating is disabled 1 = afe rx clock gating is enabled when ever all pcie ports rx are in squelch 3 dmi and pci express* rx dynamic clock gate enable ? r/w. 0 = dmi and pci express root port rx dynamic clock gating is disabled 1 = dmi and pci express root port rx dynamic clock gating is enabled 2 pci express tx dynami c clock gate enable ? r/w. 0 = pci express root port tx dy namic clock gating is disabled 1 = pci express root port tx dy namic clock gating is enabled 1 dmi tx dynamic clock gate enable ? r/w. 0 = dmi tx dynamic clock gating is disabled 1 = dmi tx dynamic clock gating is enabled 0 pci express root port st atic clock gate enable ? r/w. 0 = pci express root port stat ic clock gating is disabled 1 = pci express root port stat ic clock gating is enabled bit description bit description 7 function disable sus well lockdown (fdswl) ? r/wl 0 = fdsw registers are not locked down 1 = fdsw registers are locked down note: this bit must be set when intel ? active management technology is enabled (ich8do and ich8m-e only). 6:1 reserved 0 lan disable ? r/wl 0 = lan is enabled 1 = lan is disabled. if the function disable sus well lockdown bit is set, this register is locked. chipset configuration registers 308 intel ? ich8 family datasheet 7.1.74 cir8?chipset init ialization register 8 offset address: 3430h attribute: r/w, ro default value: 00h size: 8-bit 7.1.75 cir9 ?chipset initialization register 9 offset address: 350ch?350fh attribute: r/w, ro default value: 00000000h size: 32-bit bit description 7:2 reserved 1:0 cir8 field 1 ? r/w. bios must program this field to 11b. bit description 31:28 reserved 27:26 cir9 field 1 ? r/w. bios must program this field to 10b. 25:0 reserved intel ? ich8 family datasheet 309 gigabit lan configuration registers 8 gigabit lan configuration registers 8.1 gigabit lan configuration registers (gigabit lan ? d25:f0) note: register address locations that are not shown in table 143 and should be treated as reserved. / table 104. gigabit lan configuration registers address map (gigabit lan ?d25:f0) (sheet 1 of 2) offset mnemonic register name function 0 default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h r/wc, ro 08h rid revision identification see register description ro 09h?0bh cc class code 020000 ro 0ch cls cache line size 00h r/w 0dh plt primary latency timer 00h ro 0eh headtyp header type 00h ro 10h?13h mbara memory base address a 00000000h r/w, ro 14h?17h mbarb memory base address b 00000000h r/w, ro 18h?1bh mbarc memory base address c 00000000h r/w, ro 2ch?2dh sid subsystem id see register description. ro 2eh?2fh svid subsystem vendor id see register description ro 30h?33h erba expansion rom base address see register description ro 34h capp capabilities list pointer c8h ro 3ch?3dh intr interrupt information see register description. r/w, ro 3eh mlmg maximum latency/minimum grant 00h ro c8h?c9h clist1 capabilities list 1 d001h ro cah?cbh pmc pci power ma nagement capability see register description ro cch?cdh pmcs pci power management control and status see register description r/wc, r/w, ro gigabit lan configuration registers 310 intel ? ich8 family datasheet 8.1.1 vid?vendor identification register (gigabit lan?d25:f0) address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 8.1.2 did?device identi fication register (gigabit lan?d25:f0) address offset: 02h?03h attribute: ro default value: see bit description size: 16 bits cfh dr data register see register description ro d0h?d1h clist2 capabilities list 2 0005h ro d2h?d3h mctl message control 0080h r/w, ro d4h?d7h maddl message address low see register description r/w d8h?dbh maddh message address high see register description r/w dch?ddh mdat message data see register description r/w table 104. gigabit lan configur ation registers address map (gigabit lan ?d25:f0) (sheet 2 of 2) offset mnemonic register name function 0 default type bit description 15:0 vendor id ? ro. this is a 16-bit value assi gned to intel. the fi eld may be auto-loaded from the nvm at address 0eh during init ti me depending on the "load vendor/device id" bit field in nvm word 0ah with a default value of 8086h. bit description 15:0 device id ? ro. this is a 16-b it value assigned to the intel ? ich8 gigabit lan controller. the field may be auto-loaded from the nvm word 0dh during initialization time depending on the "load vendor/d evice id" bit field in nvm word 0ah. intel ? ich8 family datasheet 311 gigabit lan configuration registers 8.1.3 pcicmd?pci command register (gigabit lan?d25:f0) address offset: 04h?05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. this disables pin-based intx# interrupts on enabled hot- plug and power management events. this bit has no e ffect on msi operation. 0 = internal intx# messages are generated if there is an interrupt for hot-plug or power management and msi is not enabled. 1 = internal intx# messages will not be generated. this bit does not affect inte rrupt forwarding from devices connected to the root port. assert_intx and deassert_intx messages wi ll still be forwarded to the internal interrupt controllers if this bit is set. 9 fast back to back enable (fbe) ? ro. hardwired to ?0?. 8 serr# enable (see) ? r/w. 0 = disable 1 = enables the gb lan controller to gene rate an serr# message when psts.sse is set. 7 wait cycle control (wcc) ? ro. hardwired to ?0?. 6 parity error response (per) ? r/w. 0 = disable. 1 = indicates that the device is capable of reporting pa rity errors as a master on the backbone. 5 palette snoop enable (pse) ? ro. hardwired to ?0?. 4 postable memory write enable (pmwe) ? ro. hardwired to ?0?. 3 special cycle enable (sce) ? ro. hardwired to ?0?. 2 bus master enable (bme) ? r/w. 0 = disable. all cycles from the device are master aborted 1 = enable. allows the root port to forwar d cycles onto the backbone from a gigabit lan* device. 1 memory space enable (mse) ? r/w. 0 = disable. memory cycles within the rang e specified by the memory base and limit registers are master aborted on the backbone. 1 = enable. allows memory cycles within th e range specified by the memory base and limit registers can be forwarde d to the gigabi t lan device. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disable. i/o cycles within the range spec ified by the i/o base and limit registers are master aborted on the backbone. 1 = enable. allows i/o cycles within the range specified by the i/o base and limit registers can be forwarded to the gigabit lan device. gigabit lan configuration registers 312 intel ? ich8 family datasheet 8.1.4 pcists?pci status register (gigabit lan?d25:f0) address offset: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = set when the gb lan controller receiv es a command or data from the backbone with a parity error. this is set even if pcimd.per (d25:f0, bit 6) is not set. 14 signaled system error (sse) ? r/wc. 0 = no system error signaled. 1 = set when the gb lan controller signals a system error to the internal serr# logic. 13 received master abort (rma) ? r/wc. 0 = root port has not received a completion with unsupported re quest status from the backbone. 1 = set when the gb lan controller receiv es a completion with unsupported request status from the backbone. 12 received target abort (rta) ? r/wc. 0 = root port has not received a completion with completer abort from the backbone. 1 = set when the gb lan controller receiv es a completion with completer abort from the backbone. 11 signaled target abort (sta) ? r/wc. 0 = no target abort received. 1 = set whenever the gb lan controller fo rwards a target abort received from the downstream device onto the backbone. 10:9 devsel# timing status (dev_sts) ? ro. hardwired to ?0?. 8 master data parity error detected (dped) ? r/wc. 0 = no data parity error received. 1 = set when the gb lan controller receives a completion with a data parity error on the backbone and pcimd.per (d25:f0, bit 6) is set. 7 fast back to back capable (fb2bc) ? ro. hardwired to ?0?. 6 reserved 5 66 mhz capable ? ro. hardwired to ?0?. 4 capabilities list ? ro. hardwired to ?1?. in dicates the presence of a capabilities list. 3 interrupt status ? ro. indicates status of hot-plug and power management interrupts on the root port that result in intx# message generation. 0 = interrupt is deasserted. 1 = interrupt is asserted. this bit is not set if msi is enabled. if msi is not enabled, this bit is set regardless of the state of pcicmd.interrupt disable bit (d25:f0:04h:bit 10). 2:0 reserved intel ? ich8 family datasheet 313 gigabit lan configuration registers 8.1.5 rid?revision identification register (gigabit lan?d25:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 8.1.6 cc?class code register (gigabit lan?d25:f0) address offset: 09h ? 0bh attribute: ro default value: 020000h size: 24 bits 8.1.7 cls?cache line size register (gigabit lan?d25:f0) address offset: 0ch attribute: r/w default value: 00h size: 8 bits 8.1.8 plt?primary latency timer register (gigabit lan?d25:f0) address offset: 0dh attribute: ro default value: 00h size: 8 bits 8.1.9 ht?header type register (gigabit lan?d25:f0) address offset: 0eh attribute: ro default value: 00h size: 8 bits bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 8 (ich8) family specification update for the value of the revision id register. bit description 23:0 class code? ro. this fiel d indicates the device as an ethernet adapter. 020000h = ethernet adapter. bit description 7:0 cache line size ? r/w. this field is implemented by pci devices as a readwrite field for legacy compatibility purposes but has no impact on any device functionality. bit description 7:0 latency timer (lt) ? ro. hardwired to 0. bit description 7:0 header type (ht) ? ro. 00h = indicates this is a single function device. gigabit lan configuration registers 314 intel ? ich8 family datasheet 8.1.10 mbara?memory base address register a (gigabit lan?d25:f0) address offset: 10h ? 13h attribute: r/w, ro default value: 00000000h size: 32 bits the internal csr registers and memories are accessed as direct memory mapped offsets from the base address register. sw may only access whole dword at a time. 8.1.11 mbarb?memory base address register b (gigabit lan?d25:f0) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits the internal registers that are used to access the lan space in the external flash device. accessed to these registers are dire ct memory mapped offsets from the base address register. sw may only access a dword at a time. bit description 31:15 base address (ba) ? r/w . software programs this fiel d with the base address of this region. 14:4 memory size (msize) ? r/w . memory size is 32 kb. 3 prefetchable memory (pm) ? ro. the gb lan controller does not implement prefetchable memory. 2:1 memory type (mt) ? ro. set to 00b indicating a 32 bit bar. 0 memory / io space (mios) ? ro. set to ?0? indicating a memory space bar. bit description 31:12 base address (ba) ? r/w . software programs this fiel d with the base address of this region. 11:4 memory size (msize) ? r/w . memory size is 4k bytes. 3 prefetchable memory (pm) ? ro. the gb lan controller does not implement prefetchable memory. 2:1 memory type (mt) ? ro. set to 00b indicating a 32 bit bar. 0 memory / io space (mios) ? ro. set to ?0? indicating a memory space bar. intel ? ich8 family datasheet 315 gigabit lan configuration registers 8.1.12 mbarc?memory base address register c (gigabit lan?d25:f0) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000000h size: 32 bits internal registers, and memories, can be accessed using i/o operations. there are two 4b registers in the io mapping window: addr reg and data reg. sw may only access a dword at a time. 8.1.13 sid?subsystem id register (gigabit lan?d25:f0) address offset: 2ch ? 2dh attribute: ro default value: see bit description size: 16 bits 8.1.14 svid?subsystem vendor id register (gigabit lan?d25:f0) address offset: 2eh ? 2fh attribute: ro default value: see bit description size: 16 bits bit description 31:5 base address (ba) ? r/w . software programs this fiel d with the base address of this region. 4:1 i/o size (iosize) ? ro. i/o space size is 32 bytes. 0 memory / io space (mios) ? ro. set to ?1? indicating an io space bar. bit description 15:0 subsystem id (sid) ? ro. this value may be loaded automatically from the nvm word 0ch upon power up depending on the "load subsystem id" bit field in nvm word 0ah. a value of 8086h is default for this field upon power up if the nvm does not respond or is not programmed. all functi ons are initialized to the same value. bit description 15:0 subsystem vendor id (svid) ? ro. this va lue may be loaded automatically from the nvm word 0bh upon power up or reset depe nding on the "load subsystem id" bit field in nvm word 0ah with a default value of 00 00h. this value is loadable from nvm word location 0bh. gigabit lan configuration registers 316 intel ? ich8 family datasheet 8.1.15 erba?expansion ro m base address register (gigabit lan?d25:f0) address offset: 30h ? 33h attribute: ro default value: see bit description size: 32 bits 8.1.16 capp?capabilities list pointer register (gigabit lan?d25:f0) address offset: 34h attribute: r0 default value: c8h size: 8 bits 8.1.17 intr?interrupt information register (gigabit lan?d25:f0) address offset: 3ch?3dh attribute: r/w, ro default value: 0100h size: 16 bits 8.1.18 mlmg?maximum latenc y/minimum grant register (gigabit lan?d25:f0) address offset: 3eh attribute: ro default value: 00h size: 8 bits bit description 31:0 expansion rom base address (erba) ? ro. this register is used to define the address and size information for boot-time access to the optional flash memory. if no flash memory exists this register reports 00000000h. bit description 7:0 capabilities pointer (ptr) ? ro. this field indicates th at the pointer for the first entry in the capabilities list is at c8h in configuration space. bit description 15:8 interrupt pin (ipin) ? ro. this field indicates the inte rrupt pin driven by the gb lan controller. 01h = the gb lan controller implem ents legacy interrupts on inta. 7:0 interrupt line (iline) ? r/w. default = 00h. software written value to indicate which interrupt line (vector) the interrupt is connected to. no hardware action is taken on this register. bit description 7:0 maximum latency/minimum grant (mlmg) ? ro. not used. hardwired to 00h. intel ? ich8 family datasheet 317 gigabit lan configuration registers 8.1.19 clist 1?capabiliti es list register 1 (gigabit lan?d25:f0) address offset: c8h?c9h attribute: ro default value: d001h size: 16 bits 8.1.20 pmc?pci power manageme nt capabilities register (gigabit lan?d25:f0) address offset: cah ? cbh attribute: ro default value: see bit descriptions size: 16 bits bit description 15:8 next capability (next) ? ro. value of d0h indicates the location of the next pointer. 7:0 capability id (cid) ? ro. indicates the linked list item is a pci power management register. bit description 15:11 pme_support (pmes) ? ro. this five-bit field indicates the power states in which the function may assert pm e#. it depend on pm ena and au x-pwr bits in word 0ah in the nvm: condition functionality value pm ena=0 no pme at all states 00000b pm ena & aux-pwr=0 pme at d0 and d3hot 01001b pm ena & aux-pwr=1 pme at d0, d3hot and d3cold 11001b. 10 d2_support (d2s) ? ro. the d2 state is not supported. 9 d1_support (d1s) ? ro the d1 state is not supported. 8:6 aux_current (ac) ? ro. required cu rrent defined in th e data register. 5 device specific initialization (dsi) ? ro. set to 1. the gb lan controller requires its device driver to be executed following tr ansition to the d0 un-initialized state. 4 reserved 3 pme clock (pmec) ? ro. hardwired to ?0?. 2:0 version (vs) ? ro. hardwired to 010b to indicate support for revision 1.1 of the pci power management specification . gigabit lan configuration registers 318 intel ? ich8 family datasheet 8.1.21 pmcs?pci power mana gement control and status register (gigabit lan?d25:f0) address offset: cch ? cdh attribute: r/wc, r/w, ro default value: see bit description size: 16 bits 8.1.22 dr?data register (gigabit lan?d25:f0) address offset: cfh attribute: ro default value: see bit description size: 8 bits bit description 15 pme status (pmes) ? r/wc. this bit is set to 1 when the function detects a wake-up event independent of the state of the pmee bit. writing a 1 will clear this bit. 14:13 data scale (dsc) ? r/w. this field indicates the sc aling factor to be used when interpreting the value of the data register. for the gbe lan and common functions this fi eld equals 01b (indicating 0.1 watt units) if the pm is enabled in the nvm, and the data_s elect field is set to 0, 3, 4, 7, (or 8 for function 0). else it equals 00b. for the manageability functions, this field eq uals 10b (indicating 0.01 watt units) if the pm is enabled in the nvm, and the data_select field is set to 0, 3, 4, 7; otherwise, it equals 00b. 12:9 data select (dsl) ? r/w. this four-bit field is used to select which data is to be reported through the data register (offset cfh) and data_scale fi eld. these bits are writeable only when the power management is enabled via nvm. 0h = d0 power consumption 3h = d3 power consumption 4h = d0 power dissipation 7h = d3 power dissipation 8h = common power all other values are reserved. 8 pme enable (pmee) ? r/w. if power management is enabled in the nvm, writing a 1 to this register will enable wakeup. if power management is di sabled in the nvm, writing a 1 to this bit has no affe ct, and will not set the bit to 1. 7:2 reserved - returns a value of ?000000?. 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the gb lan controller and to se t a new power state. the values are: 00 = d0 state (default) 01 = ignored 10 = ignored 11 = d3 state (power management must be enables in the nvm or this cycle will be ignored). bit description 7:0 reported data (rd) ? ro. this register is used to report power consumption and heat dissipation. this register is controlled by the data_select field in the pmcs (offset cch, bits 12:9), and the power scal e is reported in the data_sca le field in the pmcs (offset cch, bits 14:13). the data of th is field is loaded from the nv m if pm is enabled in the nvm or with a default value of 0x00 otherwise. intel ? ich8 family datasheet 319 gigabit lan configuration registers 8.1.23 clist 2?capabiliti es list register 2 (gigabit lan?d25:f0) address offset: d0h?d1h attribute: ro default value: 0005h size: 16 bits 8.1.24 mctl?message control register (gigabit lan?d25:f0) address offset: d2h?d3h attribute: r/w, ro default value: 0080h size: 16 bits 8.1.25 maddl?message address low register (gigabit lan?d25:f0) address offset: d4h?d7h attribute: r/w default value: see bit description size: 32 bits bit description 15:8 next capability (next) ? ro. value of 00h indicates the end of the list. 7:0 capability id (cid) ? ro. indicates the linked list item is a message signaled interrupt register. bit description 15:8 reserved 7 64-bit capable (cid) ? ro. set to 1 to indicate that the gb lan controller is capable of generating 64-bit message addresses. 6:4 multiple message enable (mme) ? ro. returns 000b to indicate that the gb lan controller only supports a single message. 3:1 multiple message capable (mmc) ? ro. the gb lan controller does not support multiple messages. 0 msi enable (msie) ? r/w. 0 = msi generation is disabled. 1 = the gb lan controller will generate ms i for interrupt assertion instead of intx signaling. bit description 31:0 message addre ss low (maddl) ? r/w. this field is wr itten by the system to indicate the lower 32 bits of the address to use for the msi memory write transaction. the lower two bits will always return 0 regardless of the write operation. gigabit lan configuration registers 320 intel ? ich8 family datasheet 8.1.26 maddh?message address high register (gigabit lan?d25:f0) address offset: d8h?dbh attribute: r/w default value: see bit description size: 32 bits 8.1.27 mdat?message data register (gigabit lan?d25:f0) address offset: dch?ddh attribute: r/w default value: see bit description size: 16 bits bit description 31:0 message address high (maddh) ? r/w. this field is written by the system to indicate the upper 32 bits of the address to use for the msi memory write transaction. bit description 31:0 message data (mdat) ? r/w. this field is written by the system to indicate the lower 16 bits of the data written in th e msi memory write dword transaction. the upper 16 bits of the transaction are written as 0000h. intel ? ich8 family datasheet 321 gigabit lan configuration registers 8.2 gbar0?gigabit lan base address register 0 registers 8.2.1 ldcr1?lan device control register 1 (gigabit lan memory mapped base address register) address offset: gbar0 + 00h attribute: r/w, ro default value: 00100201h size: 32 bits 8.2.2 ldcr2?lan device control register 2 (gigabit lan memory mapped base address register) address offset: gbar0 + 18h attribute: r/w, ro default value: 001000000h size: 32 bits 8.2.3 ldr1?lan device in itialization register 1 (gigabit lan memory mapped base address register) address offset: gbar0 + 20h attribute: r/w, ro default value: 1000xxxxh size: 32 bits bit description 31:25 reserved 24 plcd power down (plcdpd) ? r/w. when the bit is cleared to '0', the plcd power down setting is controlled by the internal lo gic of the lan controller. when set to '1' and the ldcr.lppde is set as well, the lan controller sets the external plcd to power down mode. further, if the lan phy power control functionality is implemented, the lan controller disconnects the lcd power supply (mobile only - see section 5.3.6 ). 23:0 reserved bit description 31:21 reserved 20 lan phy power down enable (lppde) ? r/w. when set, enables the phy to enter a low-power state when the lan contro ller is at the moff / d3 no wol. this bit is loaded from word 13h in the nvm 19:0 reserved bit description 31:0 ldr1 field 1 ? r/w. gigabit lan configuration registers 322 intel ? ich8 family datasheet 8.2.4 extcnf_ctrl?extended co nfiguration control register (gigabit lan memory mapped base address register) address offset: gbar0 + f00h attribute: r/w, ro default value: 000000002h size: 32 bits 8.2.5 ldr2?lan device init ialization register 2 (gigabit lan memory mapped base address register) address offset: gbar0 + 3004h attribute: r/w default value: b2b47cch size: 32 bits bit description 31:6 reserved 5 sw semaphore flag (swflag) ? r/w. this bit is set by the device driver to gain access permission to shared csr regi sters with the firmware and hardware 4:0 reserved bit description 31:10 reserved 19:16 ldr2 field 1 ? r/w. bios must program this field to 0101b. 15:0 reserved intel ? ich8 family datasheet 323 lpc interface bridge registers (d31:f0) 9 lpc interface bridge registers (d31:f0) the lpc bridge function of the ich8 resides in pci device 31:function 0. this function contains many other functional units, such as dma and interrupt controllers, timers, power management, system management , gpio, rtc, and lpc configuration registers. registers and functions associated with othe r functional units (ehci, uhci, ide (mobile only), etc.) are described in their respective sections. 9.1 pci configuration registers (lpc i/f?d31:f0) note: address locations that are not shown should be treated as reserved. . table 105. lpc interface pci register address map (lpc i/f?d31:f0) (sheet 1 of 2) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0007h r/w, ro 06h?07h pcists pci status 0200h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 01h ro 0bh bcc base class code 06h ro 0dh plt primary latency timer 00h ro 0eh headtyp header type 80h ro 2ch?2fh ss sub system identifiers 00000000h r/wo 40h?43h pmbase acpi base address 00000001h r/w, ro 44h acpi_cntl acpi control 00h r/w 48h?4bh gpiobase gpio base address 00000001h r/w, ro 4c gc gpio control 00h r/w 60h?63h pirq[ n ]_rout pirq[a?d] routing control 80h r/w 64h sirq_cntl serial irq control 10h r/w, ro 68h?6bh pirq[ n ]_rout pirq[e?h] routing control 80h r/w 80h lpc_i/o_dec i/o decode ranges 0000h r/w 82h?83h lpc_en lpc i/f enables 0000h r/w 84h?87h gen1_dec lpc i/f generic decode range 1 00000000h r/w 88h?8bh gen2_dec lpc i/f generic decode range 2 00000000h r/w 8ch?8eh gen3_dec lpc i/f generic decode range 3 00000000h r/w lpc interface bridge registers (d31:f0) 324 intel ? ich8 family datasheet 9.1.1 vid?vendor identification register (lpc i/f?d31:f0) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16-bit lockable: no power well: core 9.1.2 did?device identification register (lpc i/f?d31:f0) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16-bit lockable: no power well: core 90h?93h gen4_dec lpc i/f generic decode range 4 00000000h r/w a0h?cfh power management (see section 9.8.1 ) d0h?d3h fwh_sel1 firmware hub select 1 00112233h r/w, ro d4h?d5h fwh_sel2 firmware hub select 2 4567h r/w d8h?d9h fwh_dec_en1 firmware hub decode enable 1 ffcfh r/w, ro dch bios_cntl bios control 00h r/wlo, r/w e0h?e1h fdcap feature detect ion capability id 0000h ro e2h fdlen feature detection capability length 0ch ro e3h fdver feature detection version 10h ro e4h-ebh fdvct feature vector see description ro f0h?f3h rcba root complex base address 00000000h r/w table 105. lpc interface pci register addr ess map (lpc i/f?d31:f0) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich8 lpc bridge. refer to the intel ich8 family specification update for the value of the device id register. intel ? ich8 family datasheet 325 lpc interface bridge registers (d31:f0) 9.1.3 pcicmd?pci command re gister (lpc i/f?d31:f0) offset address: 04h ? 05h attribute: r/w, ro default value: 0007h size: 16-bit lockable: no power well: core 9.1.4 pcists?pci status register (lpc i/f?d31:f0) offset address: 06 ? 07h attribute: ro, r/wc default value: 0210h size: 16-bit lockable: noh power well: core note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15:10 reserved 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. the lpc bridge generate s serr# if this bit is set. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error respon se enable (pere) ? r/w. 0 = no action is taken when detecting a parity error. 1 = enables the ich8 lpc bridge to respond to parity errors de tected on backbone interface. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. hardwired to 0. 3 special cycle en able (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? ro. bus masters cannot be disabled. 1 memory space enable (mse) ? ro. memo ry space cannot be disabled on lpc. 0 i/o space enable (iose) ? ro. i/o space cannot be disabled on lpc. bit description 15 detected parity error (dpe) ? r/wc. set when the lpc bridge detects a parity error on the internal backbone. set even if the pcicmd.pere bit (d31:f0:04, bit 6) is 0. 0 = parity error not detected. 1 = parity error detected. 14 signaled system error (sse) ? r/wc. set when the lpc bridge signals a system error to the internal serr# logic. 13 master abort status (rma) ? r/wc. 0 = unsupported request status not received. 1 = the bridge received a completion wi th unsupported requ est status from the backbone. 12 received target abort (rta) ? r/wc. 0 = completion abort not received. 1 = completion with completion ab ort received from the backbone. lpc interface bridge registers (d31:f0) 326 intel ? ich8 family datasheet 9.1.5 rid?revision identification register (lpc i/f?d31:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 9.1.6 pi?programming interface register (lpc i/f?d31:f0) offset address: 09h attribute: ro default value: 00h size: 8 bits 11 signaled target abort (sta) ? r/wc. 0 = target abort not generated on the backbone. 1 = lpc bridge generated a completion pa cket with target abort status on the backbone. 10:9 devsel# timing status (dev_sts) ? ro. 01 = medium timing. 8 data parity error detected (dped) ? r/wc. 0 = all conditions listed below not met. 1 = set when all three of the following conditions are met: ? lpc bridge receives a completion packet fr om the backbone from a previous request, ? parity error has been detected (d31:f0:06, bit 15) ? pcicmd.pere bit (d31:f0:04, bit 6) is set. 7 fast back to back capable (fbc): reserv ed ? bit has no meaning on the internal backbone. 6 reserved. 5 66 mhz capable (66mhz_cap) ? reserved ? bit has no meaning on internal backbone. 4 capabilities list (clist) ? ro. capabi lity list exists on the lpc bridge. 3 interrupt status (is) ? ro. the lpc bridge does not ge nerate interrupts. 2:0 reserved. bit description bit description 7:0 revision id (rid) ? ro. refer to the intel ? i/o controller hub 8 (ich8) family specification update for the value of the revision id register bit description 7:0 programming interface ? ro. intel ? ich8 family datasheet 327 lpc interface bridge registers (d31:f0) 9.1.7 scc?sub class code re gister (lpc i/f?d31:f0) offset address: 0ah attribute: ro default value: 01h size: 8 bits 9.1.8 bcc?base class code re gister (lpc i/f?d31:f0) offset address: 0bh attribute: ro default value: 06h size: 8 bits 9.1.9 plt?primary latency time r register (lpc i/f?d31:f0) offset address: 0dh attribute: ro default value: 00h size: 8 bits 9.1.10 headtyp?header type register (lpc i/f?d31:f0) offset address: 0eh attribute: ro default value: 80h size: 8 bits bit description 7:0 sub class code ? ro. 8-bit value that indicates th e category of bridge for the lpc bridge. 01h = pci-to-isa bridge. bit description 7:0 base class code ? ro. 8-bit value that indicates the type of device for the lpc bridge. 06h = bridge device. bit description 7:3 master latency count (mlc) ? reserved. 2:0 reserved. bit description 7 multi-function device ? ro. this bit is 1 to indicate a multi-function device. 6:0 header type ? ro. this 7-bit field identifi es the header layout of the configuration space. lpc interface bridge registers (d31:f0) 328 intel ? ich8 family datasheet 9.1.11 ss?sub system identifier s register (lpc i/f?d31:f0) offset address: 2ch ? 2fh attribute: r/wo default value: 00000000h size: 32 bits this register is initialized to logic 0 by th e assertion of pltrst#. this register can be written only once after pltrst# de-assertion. 9.1.12 pmbase?acpi ba se address register (lpc i/f?d31:f0) offset address: 40h ? 43h attribute: r/w, ro default value: 00000001h size: 32 bit lockable: no usage: acpi, legacy power well: core sets base address for acpi i/o registers, gpio registers and tco i/o registers. these registers can be mapped anywhere in the 64-k i/o space on 128-byte boundaries. bit description 31:16 subsystem id (ssid) ? r/wo this is written by bios. no hardware action taken on this value. 15:0 subsystem vendor id (ssvid) ? r/wo this is written by bios. no hardware action taken on this value. bit description 31:16 reserved 15:7 base address ? r/w. this field provides 128 by tes of i/o space for acpi, gpio, and tco logic. this is placed on a 128-byte boundary. 6:1 reserved 0 resource type indicator (rte) ? ro. ha rdwired to 1 to indicate i/o space. intel ? ich8 family datasheet 329 lpc interface bridge registers (d31:f0) 9.1.13 acpi_cntl?acpi control register (lpc i/f ? d31:f0) offset address: 44h attribute: r/w default value: 00h size: 8 bit lockable: no usage: acpi, legacy power well: core 9.1.14 gpiobase?gpio base ad dress register (lpc i/f ? d31:f0) offset address: 48h?4bh attribute: r/w, ro default value: 00000001h size: 32 bit bit description 7 acpi enable (acpi_en) ? r/w. 0 = disable. 1 = decode of the i/o range pointed to by th e acpi base register is enabled, and the acpi power management fu nction is enabled. no te that the apm power management ranges (b2/b3h) are always en abled and are not affected by this bit. 6:3 reserved 2:0 sci irq select (sci_irq_sel) ? r/w. this field specifies on which irq the sci will internally appear. if not using the apic, th e sci must be routed to irq9?11, and that interrupt is not sharable with the serirq stream, but is shar eable with other pci interrupts. if using the apic, the sci can also be mapped to ir q20?23, and can be shared with other interrupts. note: when the interrupt is mapped to apic inte rrupts 9, 10 or 11, the apic should be programmed for active-high reception. when the interrupt is mapped to apic interrupts 20 through 23, the apic shou ld be programmed for active-low reception. bits sci map 000b irq9 001b irq10 010b irq11 011b reserved 100b irq20 (only available if apic enabled) 101b irq21 (only available if apic enabled) 110b irq22 (only available if apic enabled) 111b irq23 (only available if apic enabled) bit description 31:16 reserved. always 0. 15:6 base address (ba) ? r/w. provides the 64 bytes of i/o space for gpio. 5:1 reserved. always 0. 0 ro. hardwired to 1 to indicate i/o space. lpc interface bridge registers (d31:f0) 330 intel ? ich8 family datasheet 9.1.15 gc?gpio control regi ster (lpc i/f ? d31:f0) offset address: 4ch attribute: r/w default value: 00h size: 8 bit 9.1.16 pirq[n]_rout?pirq[a,b,c, d] routing control register (lpc i/f?d31:f0) offset address: pirqa ? 60h, pirqb ? 61h, attribute: r/w pirqc ? 62h, pirqd ? 63h default value: 80h size: 8 bit lockable: no power well: core bit description 7:5 reserved. 4 gpio enable (en) ? r/w. this bit enables/disables decode of the i/o range pointed to by the gpio base address register (d31:f0:48h) and enables the gpio function. 0 = disable. 1 = enable. 3:0 reserved. bit description 7 interrupt routing enable (irqen) ? r/w. 0 = the corresponding pirq is routed to one of the isa-compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 reserved 3:0 irq routing ? r/w. (isa compatible.) value irq value irq 0000b reserved 1000b reserved 0001b reserved 1001b irq9 0010b reserved 1010b irq10 0011b irq3 1011b irq11 0100b irq4 1100b irq12 0101b irq5 1101b reserved 0110b irq6 1110b irq14 0111b irq7 1111b irq15 intel ? ich8 family datasheet 331 lpc interface bridge registers (d31:f0) 9.1.17 sirq_cntl?serial irq control register (lpc i/f?d31:f0) offset address: 64h attribute: r/w, ro default value: 10h size: 8 bit lockable: no power well: core bit description 7 serial irq enable (sirqen) ? r/w. 0 = the buffer is input only and internally serirq will be a 1. 1 = serial irqs will be recognized. the se rirq pin will be configured as serirq. 6 serial irq mode select (sirqmd) ? r/w. 0 = the serial irq machine will be in quiet mode. 1 = the serial irq machine will be in continuous mode. note: for systems using quiet mode, this bit should be set to 1 (continuous mode) for at least one frame after coming out of reset before switch ing back to quiet mode. failure to do so will result in the ich8 not recogniz ing serirq interrupts. 5:2 serial irq frame size (sirqsz) ? ro. fixed field that indicates the size of the serirq frame as 21 frames. 1:0 start frame pulse width (sfpw) ? r/w. this is the number of pci clocks that the serirq pin will be driven low by the serial irq machine to signal a start frame. in continuous mode, the ich8 will drive the start frame for the number of clocks specified. in quiet mode, the ich8 will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = reserved lpc interface bridge registers (d31:f0) 332 intel ? ich8 family datasheet 9.1.18 pirq[n]_rout?pirq[e,f,g,h] routing control register (lpc i/f?d31:f0) offset address: pirqe ? 68h, pirqf ? 69h, attribute: r/w pirqg ? 6ah, pirqh ? 6bh default value: 80h size: 8 bit lockable: no power well: core bit description 7 interrupt routing enable (irqen) ? r/w. 0 = the corresponding pirq is routed to one of the isa-compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may su bsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 reserved 3:0 irq routing ? r/w. (isa compatible.) value irq value irq 0000b reserved 1000b reserved 0001b reserved 1001b irq9 0010b reserved 1010b irq10 0011b irq3 1011b irq11 0100b irq4 1100b irq12 0101b irq5 1101b reserved 0110b irq6 1110b irq14 0111b irq7 1111b irq15 intel ? ich8 family datasheet 333 lpc interface bridge registers (d31:f0) 9.1.19 lpc_i/o_dec?i/o decode ranges register (lpc i/f?d31:f0) offset address: 80h attribute: r/w default value: 0000h size: 16 bit bit description 15:13 reserved 12 fdd decode range ? r/w. determines which range to decode for the fdd port 0 = 3f0h ? 3f5h, 3f7h (primary) 1 = 370h ? 375h, 377h (secondary) 11:10 reserved 9:8 lpt decode range ? r/w. this field determines which range to decode for the lpt port. 00 = 378h ? 37fh and 778h ? 77fh 01 = 278h ? 27fh (port 279h is read only) and 678h ? 67fh 10 = 3bch ?3beh and 7bch ? 7beh 11 = reserved 7 reserved 6:4 comb decode range ? r/w. this field determines which range to decode for the comb port. 000 = 3f8h ? 3ffh (com1) 001 = 2f8h ? 2ffh (com2) 010 = 220h ? 227h 011 = 228h ? 22fh 100 = 238h ? 23fh 101 = 2e8h ? 2efh (com4) 110 = 338h ? 33fh 111 = 3e8h ? 3efh (com3) 3 reserved 2:0 coma decode range ? r/w. this field determines which range to decode for the coma port. 000 = 3f8h ? 3ffh (com1) 001 = 2f8h ? 2ffh (com2) 010 = 220h ? 227h 011 = 228h ? 22fh 100 = 238h ? 23fh 101 = 2e8h ? 2efh (com4) 110 = 338h ? 33fh 111 = 3e8h ? 3efh (com3) lpc interface bridge registers (d31:f0) 334 intel ? ich8 family datasheet 9.1.20 lpc_en?lpc i/f enables register (lpc i/f?d31:f0) offset address: 82h ? 83h attribute: r/w default value: 0000h size: 16 bit power well: core bit description 15:14 reserved 13 cnf2_lpc_en ? r/w. microcontroller enable # 2. 0 = disable. 1 = enables the decoding of the i/o locati ons 4eh and 4fh to the lpc interface. this range is used for a microcontroller. 12 cnf1_lpc_en ? r/w. super i/o enable. 0 = disable. 1 = enables the decoding of the i/o locati ons 2eh and 2fh to the lpc interface. this range is used for super i/o devices. 11 mc_lpc_en ? r/w. microcontroller enable # 1. 0 = disable. 1 = enables the decoding of the i/o location s 62h and 66h to the lpc interface. this range is used for a microcontroller. 10 kbc_lpc_en ? r/w. keyboard enable. 0 = disable. 1 = enables the decoding of the i/o location s 60h and 64h to the lpc interface. this range is used for a microcontroller. 9 gameh_lpc_en ? r/w. high gameport enable 0 = disable. 1 = enables the decoding of the i/o locations 208h to 20fh to the lpc interface. this range is used for a gameport. 8 gamel_lpc_en ? r/w. low gameport enable 0 = disable. 1 = enables the decoding of the i/o locations 200h to 207h to the lpc interface. this range is used for a gameport. 7:4 reserved 3 fdd_lpc_en ? r/w. floppy drive enable 0 = disable. 1 = enables the decoding of the fdd range to the lpc interface. this range is selected in the lpc_fdd/lpt decode range register (d31:f0:80h, bit 12). 2 lpt_lpc_en ? r/w. parallel port enable 0 = disable. 1 = enables the decoding of the lptrange to th e lpc interface. this range is selected in the lpc_fdd/lpt decode range register (d31:f0:80h, bit 9:8). 1 comb_lpc_en ? r/w. com port b enable 0 = disable. 1 = enables the decoding of the comb rang e to the lpc interface. this range is selected in the lpc_com decode rang e register (d31:f0:80h, bits 6:4). 0 coma_lpc_en ? r/w. com port a enable 0 = disable. 1 = enables the decoding of the coma ra nge to the lpc interface. this range is selected in the lpc_com decode rang e register (d31:f0:80h, bits 3:2). intel ? ich8 family datasheet 335 lpc interface bridge registers (d31:f0) 9.1.21 gen1_dec?lpc i/f generi c decode range 1 register (lpc i/f?d31:f0) offset address: 84h ? 87h attribute: r/w default value: 00000000h size: 32 bit power well: core 9.1.22 gen2_dec?lpc i/f gene ric decode range 2register (lpc i/f?d31:f0) offset address: 88h ? 8bh attribute: r/w default value: 00000000h size: 32 bit power well: core bit description 31:24 reserved 23:18 generic i/o decode rang e address[7:2] mask: a ?1? in any bit position indicates that any value in the corresponding address bi t in a received cycle will be treated as a match. the corresponding bit in the address fi eld, below, is ignored. the mask is only provided for the lower 6 bits of the dword a ddress, allowing for decoding blocks up to 256 bytes in size. 17:16 reserved 15:2 generic i/o decode range 1 base address (gen1_base) ? r/w. this address is aligned on a 128-byte boundary, and must have address lines 31:16 as 0. note: the ich8 does not provide decode down to the word or byte level 1 reserved 0 generic decode range 1 enable (gen1_en) ? r/w. 0 = disable. 1 = enable the gen1 i/o range to be forwarded to the lpc i/f bit description 31:24 reserved 23:18 generic i/o decode rang e address[7:2] mask: a ?1? in any bit position indicates that any value in the corresponding address bi t in a received cycle will be treated as a match. the corresponding bit in the address fi eld, below, is ignored. the mask is only provided for the lower 6 bits of the dword a ddress, allowing for decoding blocks up to 256 bytes in size. 17:16 reserved 15:2 generic i/o decode range 2base address (gen1_base) ? r/w. note: the ich8 does not provide decode down to the word or byte level 1 reserved 0 generic decode range 2enable (gen2_en) ? r/w. 0 = disable. 1 = enable the gen2 i/o range to be forwarded to the lpc i/f lpc interface bridge registers (d31:f0) 336 intel ? ich8 family datasheet 9.1.23 gen3_dec?lpc i/f gene ric decode range 3register (lpc i/f?d31:f0) offset address: 8ch ? 8eh attribute: r/w default value: 00000000h size: 32 bit power well: core 9.1.24 gen4_dec?lpc i/f gene ric decode range 4register (lpc i/f?d31:f0) offset address: 90h ? 93h attribute: r/w default value: 00000000h size: 32 bit power well: core bit description 31:24 reserved 23:18 generic i/o decode range address[7:2] mask: a ?1? in any bit position indicates that any value in the correspon ding address bit in a received cycle will be treated as a match. the corresponding bit in the address field, below, is ignored. the mask is only provided for the lower 6 bits of the dword ad dress, allowing for decoding blocks up to 256 bytes in size. 17:16 reserved 15:2 generic i/o decode range 3base address (gen3_base) ? r/w. note: the ich8 does not provide decode down to the word or byte level 1 reserved 0 generic decode range 3enable (gen3_en) ? r/w. 0 = disable. 1 = enable the gen3 i/o range to be forwarded to the lpc i/f bit description 31:24 reserved 23:18 generic i/o decode range address[7:2] mask: a 1 in any bit position indicates that any value in the correspon ding address bit in a received cycle will be treated as a match. the corresponding bit in the address field, below, is ignored. the mask is only provided for the lower 6 bits of the dword ad dress, allowing for decoding blocks up to 256 bytes in size. 17:16 reserved 15:2 generic i/o decode range 4base address (gen4_base) ? r/w. note: the ich8 does not provide decode down to the word or byte level 1 reserved 0 generic decode range 4enable (gen4_en) ? r/w. 0 = disable. 1 = enable the gen4 i/o range to be forwarded to the lpc i/f intel ? ich8 family datasheet 337 lpc interface bridge registers (d31:f0) 9.1.25 fwh_sel1?firmware hub select 1 register (lpc i/f?d31:f0) offset address: d0h ? d3h attribute: r/w, ro default value: 00112233h size: 32 bits bit description 31:28 fwh_f8_idsel ? ro. idsel for two 512-kb firm ware hub memory ranges and one 128-kb memory range. this field is fixed at 0000. the idsel programmed in this field addresses the following memory ranges: fff8 0000h ? ffff ffffh ffb8 0000h ? ffbf ffffh 000e 0000h ? 000f ffffh 27:24 fwh_f0_idsel ? r/w. idsel for two 512-kb fi rmware hub memo ry ranges. the idsel programmed in this field addr esses the following memory ranges: fff0 0000h ? fff7 ffffh ffb0 0000h ? ffb7 ffffh 23:20 fwh_e8_idsel ? r/w. idsel for two 512-kb fi rmware hub memory ranges. the idsel programmed in this field addr esses the following memory ranges: ffe8 0000h ? ffef ffffh ffa8 0000h ? ffaf ffffh 19:16 fwh_e0_idsel ? r/w. idsel for two 512-kb fi rmware hub memory ranges. the idsel programmed in this field addr esses the following memory ranges: ffe0 0000h ? ffe7 ffffh ffa0 0000h ? ffa7 ffffh 15:12 fwh_d8_idsel ? r/w. idsel for two 512-kb fi rmware hub memo ry ranges. the idsel programmed in this field addr esses the following memory ranges: ffd8 0000h ? ffdf ffffh ff98 0000h ? ff9f ffffh 11:8 fwh_d0_idsel ? r/w. idsel for two 512-kb fi rmware hub memo ry ranges. the idsel programmed in this field addr esses the following memory ranges: ffd0 0000h ? ffd7 ffffh ff90 0000h ? ff97 ffffh 7:4 fwh_c8_idsel ? r/w. idsel for two 512-kb fi rmware hub memo ry ranges. the idsel programmed in this field addr esses the following memory ranges: ffc8 0000h ? ffcf ffffh ff88 0000h ? ff8f ffffh 3:0 fwh_c0_idsel ? r/w. idsel for two 512-kb fi rmware hub memo ry ranges. the idsel programmed in this field addr esses the following memory ranges: ffc0 0000h ? ffc7 ffffh ff80 0000h ? ff87 ffffh lpc interface bridge registers (d31:f0) 338 intel ? ich8 family datasheet 9.1.26 fwh_sel2?firmware hub select 2 register (lpc i/f?d31:f0) offset address: d4h ? d5h attribute: r/w default value: 4567h size: 16 bits 9.1.27 fwh_dec_en1?firmware hu b decode enable register (lpc i/f?d31:f0) offset address: d8h ? d9h attribute: r/w, ro default value: ffcfh size: 16 bits bit description 15:12 fwh_70_idsel ? r/w. idsel for two, 1-m firmware hub memory ranges. the idsel programmed in this field a ddresses the following memory ranges: ff70 0000h ? ff7f ffffh ff30 0000h ? ff3f ffffh 11:8 fwh_60_idsel ? r/w. idsel for two, 1-m firmware hub memory ranges. the idsel programmed in this field a ddresses the following memory ranges: ff60 0000h ? ff6f ffffh ff20 0000h ? ff2f ffffh 7:4 fwh_50_idsel ? r/w. idsel for two, 1-m firmware hub memory ranges. the idsel programmed in this field a ddresses the following memory ranges: ff50 0000h ? ff5f ffffh ff10 0000h ? ff1f ffffh 3:0 fwh_40_idsel ? r/w. idsel for two, 1-m firmware hub memory ranges. the idsel programmed in this field a ddresses the following memory ranges: ff40 0000h ? ff4f ffffh ff00 0000h ? ff0f ffffh bit description 15 fwh_f8_en ? ro. this bit enables decoding two 512-kb firmware hub memory ranges, and one 128-kb memory range. 0 = disable 1 = enable the following ranges for the firmware hub fff80000h ? ffffffffh ffb80000h ? ffbfffffh 14 fwh_f0_en ? r/w. this bit enables decoding two 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub: fff00000h ? fff7ffffh ffb00000h ? ffb7ffffh 13 fwh_e8_en ? r/w. this bit enables decoding two 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub: ffe80000h ? ffeffffh ffa80000h ? ffafffffh intel ? ich8 family datasheet 339 lpc interface bridge registers (d31:f0) 12 fwh_e0_en ? r/w. this bit enables decoding two 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub: ffe00000h ? ffe7ffffh ffa00000h ? ffa7ffffh 11 fwh_d8_en ? r/w. this bit enables decoding two 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ffd80000h ? ffdfffffh ff980000h ? ff9fffffh 10 fwh_d0_en ? r/w. this bit enables decoding two 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ffd00000h ? ffd7ffffh ff900000h ? ff97ffffh 9 fwh_c8_en ? r/w. this bit enables decoding two 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ffc80000h ? ffcfffffh ff880000h ? ff8fffffh 8 fwh_c0_en ? r/w. this bit enables decoding two 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ffc00000h ? ffc7ffffh ff800000h ? ff87ffffh 7 fwh_legacy_f_en ? r/w. this enables the decoding of the legacy 128-k range at f0000h ? fffffh. 0 = disable. 1 = enable the following legacy ranges for the firmware hub f0000h ? fffffh 6 fwh_legacy_e_en ? r/w. this enables the decoding of the legacy 128-k range at e0000h ? effffh. 0 = disable. 1 = enable the following legacy ranges for the firmware hub e0000h ? effffh 5:4 reserved 3 fwh_70_en ? r/w. enables decoding two 1- m firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ff70 0000h ? ff7f ffffh ff30 0000h ? ff3f ffffh bit description lpc interface bridge registers (d31:f0) 340 intel ? ich8 family datasheet note: this register effects the bios decode regardless of whether the bios is resident on lpc or spi. the concept of feature space does not apply to spi-based flash. the ich8 simply decodes these ranges as memory accesses when enabled for the spi flash interface. 2 fwh_60_en ? r/w. enables decoding two 1- m firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ff60 0000h ? ff6f ffffh ff20 0000h ? ff2f ffffh 1 fwh_50_en ? r/w. enables decoding two 1-m firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ff50 0000h ? ff5f ffffh ff10 0000h ? ff1f ffffh 0 fwh_40_en ? r/w. enables decoding two 1- m firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ff40 0000h ? ff4f ffffh ff00 0000h ? ff0f ffffh bit description intel ? ich8 family datasheet 341 lpc interface bridge registers (d31:f0) 9.1.28 bios_cntl?bios control register (lpc i/f?d31:f0) offset address: dch attribute: r/wlo, r/w, ro default value: 00h size: 8 bit lockable: no power well: core 9.1.29 fdcap?feature dete ction capability id (lpc i/f?d31:f0) offset address: e0h-e1h attribute: ro default value: 0000h size: 16 bit power well: core bit description 7:5 reserved 4 top swap status (tss) ? ro: this bit provides a read-only path to view the state of the top swap bit that is at offset 3414h, bit 0. 3:2 spi read configuration (src) ? r/w: this 2-bit field controls two policies related to bios reads on the spi interface: bit 3- prefetch enable bit 2- cache disable settings are su mmarized below: 1 bios lock enable (ble) ? r/wlo. 0 = setting the bioswe will not cause smis. 1 = enables setting the bioswe bit to caus e smis. once set, this bit can only be cleared by a pltrst# 0 bios write enable (bioswe) ? r/w. 0 = only read cycles result in firmware hub i/f cycles. 1 = access to the bios space is enabled for both read and write cycles. when this bit is written from a 0 to a 1 and bios lock en able (ble) is also set, an smi# is generated. this ensu res that only smi co de can update bios. bits 3:2 description 00b no prefetching, but caching enabled. 64b demand reads load the read buffer cache with ?valid ? data, allowing repeated code fetches to the same line to complete quickly 01b no prefetching and no caching. one-to-one co rrespondence of host bios reads to spi cycles. this value can be used to invalidate the cache. 10b prefetching and caching enabled. this mode is used for long sequences of short reads to consecutive addresses (i.e., shadowing). 11b reserved. this is an invalid configuration , caching must be enabled when prefetching is enabled. bit description 15:8 next item pointer (next): configuration offset of the next capability item. 00h indicates the last item in the capability list. 7:0 capability id: indicates a vendor specific capability lpc interface bridge registers (d31:f0) 342 intel ? ich8 family datasheet 9.1.30 fdlen?feature detection capability length (lpc i/f?d31:f0) offset address: e2h attribute: ro default value: 0ch size: 8 bit power well: core 9.1.31 fdver?feature detection version (lpc i/f?d31:f0) offset address: e3h attribute: ro default value: 10h size: 8 bit power well: core 9.1.32 fdvct?feature vector (lpc i/f?d31:f0) offset address: e4h-ebh attribute: ro default value: see description size: 64 bit power well: core bit description 7:0 capability length: indicates the length of this vendor specific capability, as required by pci spec. bit description 7:4 vendor-specific capability id: a value of 1h in this 4-bit fi eld identifies this capability as feature detection type. this field allo ws software to differentiate the feature detection capability from othe r vendor-specific capabilities 3:0 capability version: this field indicates the version of the feature detection capability bit description 63:40 reserved 39 (ich8dh only) quick resume technology capability? ro: 0 = capable 1 = disabled 39 (ich8 base, ich8r, ich8do , mobile only) reserved 38:19 reserved 18 sata raid 5 capability? ro: 0 = capable 1 = disabled 17:10 reserved intel ? ich8 family datasheet 343 lpc interface bridge registers (d31:f0) 9.1.33 rcba?root complex base address register (lpc i/f?d31:f0) offset address: f0h attribute: r/w default value: 00000000h size: 32 bit 9 (mobile only) mobile features capability? ro: 0 = disabled 1 = capable 9 (desktop only) reserved 8 reserved 7 pci express* 6 x1 capability? ro: 0 = capable 1 = disabled ? 4 pci express x1 ports available 6 reserved 5 sata raid 0/1/10 capability? ro: 0 = capable 1 = disabled 4 reserved 3 sata ahci capability? ro: 0 = capable 1 = disabled 2:0 reserved bit description bit description 31:14 base address (ba) ? r/w. base address for the root complex register block decode range. this address is aligned on a 16-kb boundary. 13:1 reserved 0 enable (en) ? r/w. when set, enables the range specified in ba to be claimed as the root complex register block. lpc interface bridge registers (d31:f0) 344 intel ? ich8 family datasheet 9.2 dma i/o registers (lpc i/f?d31:f0) table 106. dma registers (sheet 1 of 2) port alias register name default type 00h 10h channel 0 dma base & current address undefined r/w 01h 11h channel 0 dma base & current count undefined r/w 02h 12h channel 1 dma base & current address undefined r/w 03h 13h channel 1 dma base & current count undefined r/w 04h 14h channel 2 dma base & current address undefined r/w 05h 15h channel 2 dma base & current count undefined r/w 06h 16h channel 3 dma base & current address undefined r/w 07h 17h channel 3 dma base & current count undefined r/w 08h 18h channel 0?3 dma command undefined wo channel 0?3 dma status undefined ro 0ah 1ah channel 0?3 dma write single mask 000001xxb wo 0bh 1bh channel 0?3 dma channel mode 000000xxb wo 0ch 1ch channel 0?3 dma clear byte pointer undefined wo 0dh 1dh channel 0?3 dma master clear undefined wo 0eh 1eh channel 0?3 dma clear mask undefined wo 0fh 1fh channel 0?3 dma write all mask 0fh r/w 80h 90h reserved page undefined r/w 81h 91h channel 2 dma memory low page undefined r/w 82h ? channel 3 dma memory low page undefined r/w 83h 93h channel 1 dma memory low page undefined r/w 84h?86h 94h?96h reserved pages undefined r/w 87h 97h channel 0 dma memory low page undefined r/w 88h 98h reserved page undefined r/w 89h 99h channel 6 dma memory low page undefined r/w 8ah 9ah channel 7 dma memory low page undefined r/w 8bh 9bh channel 5 dma memory low page undefined r/w 8ch?8eh 9ch?9eh reserved page undefined r/w 8fh 9fh refresh low page undefined r/w c0h c1h channel 4 dma base & current address undefined r/w c2h c3h channel 4 dma base & current count undefined r/w c4h c5h channel 5 dma base & current address undefined r/w c6h c7h channel 5 dma base & current count undefined r/w c8h c9h channel 6 dma base & current address undefined r/w cah cbh channel 6 dma base & current count undefined r/w cch cdh channel 7 dma base & current address undefined r/w intel ? ich8 family datasheet 345 lpc interface bridge registers (d31:f0) 9.2.1 dmabase_ca?dma base and current address registers (lpc i/f?d31:f0) i/o address: ch. #0 = 00h; ch. #1 = 02h attribute: r/w ch. #2 = 04h; ch. #3 = 06h size: 16 bit (per channel), ch. #5 = c4h ch. #6 = c8h but accessed in two 8-bit ch. #7 = cch; quantities default value: undef lockable: no power well: core ceh cfh channel 7 dma base & current count undefined r/w d0h d1h channel 4?7 dma command undefined wo channel 4?7 dma status undefined ro d4h d5h channel 4?7 dma write single mask 000001xxb wo d6h d7h channel 4?7 dma channel mode 000000xxb wo d8h d9h channel 4?7 dma clear byte pointer undefined wo dah dbh channel 4?7 dma master clear undefined wo dch ddh channel 4?7 dma clear mask undefined wo deh dfh channel 4?7 dma write all mask 0fh r/w table 106. dma registers (sheet 2 of 2) port alias register name default type bit description 15:0 base and current address ? r/w. this register determin es the address for the transfers to be performed. the address specified po ints to two separate registers. on writes, the value is stored in the base address register and copied to the current address register. on read s, the value is returned from the current address register. the address increments/decrements in the current address register after each transfer, depending on the mode of the transfer. if the channel is in auto-initialize mode, the current address register will be reloaded from the base address register after a terminal count is generated. for transfers to/from a 16-bit slave (channel?s 5-7), the address is shifted left one bit location. bit 15 will be shifted into bit 16. the register is accessed in 8 bit quantities. the byte is po inted to by the current byte pointer flip/flop. before acce ssing an address regi ster, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first lpc interface bridge registers (d31:f0) 346 intel ? ich8 family datasheet 9.2.2 dmabase_cc?dma base and current count registers (lpc i/f?d31:f0) i/o address: ch. #0 = 01h; ch. #1 = 03h attribute: r/w ch. #2 = 05h; ch. #3 = 07h size: 16-bit (per channel), ch. #5 = c6h; ch. #6 = cah but accessed in two 8-bit ch. #7 = ceh; quantities default value: undefined lockable: no power well: core 9.2.3 dmamem_lp?dma memory low page registers (lpc i/f?d31:f0) i/o address: ch. #0 = 87h; ch. #1 = 83h ch. #2 = 81h; ch. #3 = 82h ch. #5 = 8bh; ch. #6 = 89h ch. #7 = 8ah; attribute: r/w default value: undefined size: 8-bit lockable: no power well: core bit description 15:0 base and current count ? r/w. this register determines the number of transfers to be performed. the address spec ified points to two separate registers. on writes, the value is stored in the base count register and copied to the current count register. on reads, the value is returned from the current count register. the actual number of transfers is one more than the number programmed in the base count register (i.e., programming a count of 4h results in 5 transfers). the count is decrements in the current count register after each transfer. when the value in the register rolls from 0 to ffffh, a terminal count is generated. if the channel is in auto- initialize mode, the current count register will be re loaded from the base count register after a termin al count is generated. for transfers to/from an 8-bit slave (channels 0?3), the count register indicates the number of bytes to be transferred. for tran sfers to/from a 16-bit slave (channels 5?7), the count register indicates the nu mber of words to be transferred. the register is accessed in 8 bit quantities. the byte is po inted to by the current byte pointer flip/flop. before acce ssing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is ac cessed first. bit description 7:0 dma low page (isa address bits [23:16]) ? r/w. this register works in conjunction with the dma controller's cu rrent address register to de fine the complete 24-bit address for the dma channel. this register remains static throughout the dma transfer. bit 16 of this register is ignored when in 16 bit i/o count by words mode as it is replaced by the bit 15 shifted out from the current address register. intel ? ich8 family datasheet 347 lpc interface bridge registers (d31:f0) 9.2.4 dmacmd?dma command re gister (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 08h; ch. #4 ? 7 = d0h attribute: wo default value: undefined size: 8-bit lockable: no power well: core 9.2.5 dmasta?dma status re gister (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 08h; ch. #4 ? 7 = d0h attribute: ro default value: undefined size: 8-bit lockable: no power well: core bit description 7:5 reserved. must be 0. 4 dma group arbitration priority ? wo. each channel group is individually assigned either fixed or rotating arbitration priority. at part reset, each group is initialized in fixed priority. 0 = fixed priority to the channel group 1 = rotating priority to the group. 3 reserved. must be 0. 2 dma channel group enable ? wo. both channel groups are enabled following part reset. 0 = enable the dma channel group. 1 = disable. disabling channel group 4?7 al so disables channel group 0?3, which is cascaded through channel 4. 1:0 reserved. must be 0. bit description 7:4 channel request status ? ro. when a valid dma reques t is pending for a channel, the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware or a software request. note that channel 4 is the cascade channel, so the request status of channel 4 is a logical or of the requ est status for chan nels 0 through 3. 4 = channel 0 5 = channel 1 (5) 6 = channel 2 (6) 7 = channel 3 (7) 3:0 channel terminal count status ? ro. when a channel reaches terminal count (tc), its status bit is set to 1. if tc has not been reached, the status bit is set to 0. channel 4 is programmed for cascade, so the tc bi t response for channel 4 is irrelevant: 0 = channel 0 1 = channel 1 (5) 2 = channel 2 (6) 3 = channel 3 (7) lpc interface bridge registers (d31:f0) 348 intel ? ich8 family datasheet 9.2.6 dma_wrsmsk?dma write single mask register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0ah; ch. #4 ? 7 = d4h attribute: wo default value: 0000 01xx size: 8-bit lockable: no power well: core bit description 7:3 reserved. must be 0. 2 channel mask select ? wo. 0 = enable dreq for the selected channel. the channel is selected through bits [1:0]. therefore, only one ch annel can be masked / unmasked at a time. 1 = disable dreq for the selected channel. 1:0 dma channel select ? wo. these bits select the dma channel mode register to program. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7) intel ? ich8 family datasheet 349 lpc interface bridge registers (d31:f0) 9.2.7 dmach_mode?dma ch annel mode register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0bh; ch. #4 ? 7 = d6h attribute: wo default value: 0000 00xx size: 8-bit lockable: no power well: core bit description 7:6 dma transfer mode ? wo. each dma channel can be programmed in one of four different modes: 00 = demand mode 01 = single mode 10 = reserved 11 = cascade mode 5 address increment/decrement select ? wo. this bit controls address increment/ decrement during dma transfers. 0 = address increment. (default af ter part reset or master clear) 1 = address decrement. 4 autoinitialize enable ? wo. 0 = autoinitialize feature is disabled and dma transfers te rminate on a terminal count. a part reset or master clear disables autoinitialization. 1 = dma restores the base address and co unt registers to th e current registers following a terminal count (tc). 3:2 dma transfer type ? wo. these bits represent the direction of the dma transfer. when the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant. 00 = verify ? no i/o or memory strobes generated 01 = write ? data transferred from the i/o devices to memory 10 = read ? data transferred from memory to the i/o device 11 = invalid 1:0 dma channel select ? wo. these bits select the dma ch annel mode register that will be written by bits [7:2]. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7) lpc interface bridge registers (d31:f0) 350 intel ? ich8 family datasheet 9.2.8 dma clear byte pointer register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0ch; ch. #4 ? 7 = d8h attribute: wo default value: xxxx xxxx size: 8-bit lockable: no power well: core 9.2.9 dma master clear re gister (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0dh; ch. #4 ? 7 = dah attribute: wo default value: xxxx xxxx size: 8-bit bit description 7:0 clear byte pointer ? wo. no specific pattern. comm and enabled with a write to the i/o port address. writing to this register initializes the byte pointer flip/flop to a known state. it clears the internal latch used to address the uppe r or lower byte of the 16-bit address and word count registers. the latch is also cleared by part reset and by the master clear command. this command precedes the first access to a 16-bit dma controller register. the first ac cess to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte. bit description 7:0 master clear ? wo. no specific pattern. enabled with a write to the port. this has the same effect as the hardware reset. the co mmand, status, reques t, and byte pointer flip/flop registers are cleared and the mask register is set. intel ? ich8 family datasheet 351 lpc interface bridge registers (d31:f0) 9.2.10 dma_clmsk?dma clear mask register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0eh; ch. #4 ? 7 = dch attribute: wo default value: xxxx xxxx size: 8-bit lockable: no power well: core 9.2.11 dma_wrmsk?dma write all mask register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0fh; ch. #4 ? 7 = deh attribute: r/w default value: 0000 1111 size: 8-bit lockable: no power well: core bit description 7:0 clear mask register ? wo. no specific pattern. command enabled with a write to the port. bit description 7:4 reserved. must be 0. 3:0 channel mask bits ? r/w. this register permit s all four channels to be simultaneously enabled/disabled instead of enabling/disabling each channel individually, as is the case with the mask re gister ? write single mask bit. in addition, this register has a read path to allow the st atus of the channel mask bits to be read. a channel's mask bit is automatically set to 1 when the current byte/word count register reaches terminal count (unless the chan nel is in auto-initialization mode). setting the bit(s) to a 1 disables the corre sponding dreq(s). setting the bit(s) to a 0 enables the corresponding dreq(s). bits [3:0 ] are set to 1 upon part reset or master clear. when read, bits [3:0] indicate the dma channel [3:0] ([7:4]) mask status. bit 0 = channel 0 (4) 1 = masked, 0 = not masked bit 1 = channel 1 (5) 1 = masked, 0 = not masked bit 2 = channel 2 (6) 1 = masked, 0 = not masked bit 3 = channel 3 (7) 1 = masked, 0 = not masked note: disabling channel 4 also disables channels 0?3 due to the cascade of channel?s 0 ? 3 through channel 4. lpc interface bridge registers (d31:f0) 352 intel ? ich8 family datasheet 9.3 timer i/o registers (lpc i/f?d31:f0) port aliases register name default value type 40h 50h counter 0 interval time status byte format 0xxxxxxxb ro counter 0 counter access port undefined r/w 41h 51h counter 1 interval time status byte format 0xxxxxxxb ro counter 1 counter access port undefined r/w 42h 52h counter 2 interval time status byte format 0xxxxxxxb ro counter 2 counter access port undefined r/w 43h 53h timer control word undefined wo timer control word register xxxxxxx0b wo counter latch command x0h wo intel ? ich8 family datasheet 353 lpc interface bridge registers (d31:f0) 9.3.1 tcw?timer control word register (lpc i/f?d31:f0) i/o address: 43h attribute: wo default value: all bits undefined size: 8 bits this register is programmed prior to any counter being accessed to specify counter modes. following component reset, the cont rol words for each register are undefined and each counter output is 0. each timer must be programmed to bring it into a known state. there are two special commands that can be issued to the counters through this register, the read back command and th e counter latch command. when these commands are chosen, several bits within this register are redefined. these register formats are described in the following sub-sections: rdbk_cmd?read back comma nd (lpc i/f?d31:f0) the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. status and/or count may be latched in any or all of the counters by selecting the counter during the register write. the count and status remain latched until read, and further latch commands are ignored until the count is read. both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 bit description 7:6 counter select ? wo. the counter selection bits select the counter the control word acts upon as shown below. the read back command is selected when bits[7:6] are both 1. 00 = counter 0 select 01 = counter 1 select 10 = counter 2 select 11 = read back command 5:4 read/write select ? wo. these bits are the read/w rite control bits. the actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 counter mode selection ? wo. these bits select one of six possible modes of operation for the selected counter. 0 binary/bcd countdown select ? wo. 0 = binary countdown is used. the la rgest possible binary count is 2 16 1 = binary coded decimal (bcd) count is us ed. the largest possible bcd count is 10 4 b i t va l ue mo d e 000b mode 0 out signal on end of count (=0) 001b mode 1 hardware retriggerable one-shot x10b mode 2 rate generator (divide by n counter) x11b mode 3 square wave output 100b mode 4 software triggered strobe 101b mode 5 hardware triggered strobe lpc interface bridge registers (d31:f0) 354 intel ? ich8 family datasheet to 0. if both are latched, the first read op eration from that counter returns the latched status. the next one or two reads, depend ing on whether the counter is programmed for one or two byte counts, returns the latched count. subsequent reads return an unlatched count. ltch_cmd?counter latch command (lpc i/f?d31:f0) the counter latch command latches the current count value. this command is used to ensure that the count read from the counter is accurate. the count value is then read from each counter's count register through the counter ports access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2). the count must be read according to the programmed format, i.e., if the counter is programmed for two byte counts, two bytes must be read. the two byte s do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). if a counter is latche d once and then latched again before the count is read, the second counter latch command is ignored. bit description 7:6 read back command. must be 11 to select the read back command 5 latch count of selected counters . 0 = current count value of the se lected counters will be latched 1 = current count will not be latched 4 latch status of selected counters . 0 = status of the selected counters will be latched 1 = status will not be latched 3 counter 2 select . 1 = counter 2 count and/or status will be latched 2 counter 1 select . 1 = counter 1 count and/or status will be latched 1 counter 0 select . 1 = counter 0 count and/or status will be latched. 0 reserved. must be 0. bit description 7:6 counter selection. these bits select the counter for la tching. if ?11? is written, then the write is interpreted as a read back command. 00 = counter 0 01 = counter 1 10 = counter 2 5:4 counter latch command . 00 = selects the counter latch command. 3:0 reserved. must be 0. intel ? ich8 family datasheet 355 lpc interface bridge registers (d31:f0) 9.3.2 sbyte_fmt?interval timer status byte format register (lpc i/f?d31:f0) i/o address: counter 0 = 40h, counter 1 = 41h, attribute: ro counter 2 = 42h size: 8 bits per counter default value: bits[6:0] undefined, bit 7=0 each counter's status byte can be read follo wing a read back command. if latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns th e status byte. the status byte returns the following: bit description 7 counter out pin state ? ro. 0 = out pin of the counter is also a 0 1 = out pin of the counter is also a 1 6 count register status ? ro. this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the counter mode, but until the count is loaded into the counting element (ce), the count value will be incorrect. 0 = count has been transf erred from cr to ce and is available for reading. 1 = null count. count has not been transferre d from cr to ce and is not yet available for reading. 5:4 read/write selection status ? ro. these reflect the re ad/write selection made through bits[5:4] of the control register. th e binary codes returned during the status read match the codes used to progra m the counter read/write selection. 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 mode selection status ? ro. these bits return the counter mode programming. the binary code returned matche s the code used to program the counter mode, as listed under the bit function above. 000 = mode 0 ? out signal on end of count (=0) 001 = mode 1 ? hardware retriggerable one-shot x10 = mode 2 ? rate generator (divide by n counter) x11 = mode 3 ? square wave output 100 = mode 4 ? software triggered strobe 101 = mode 5 ? hardware triggered strobe 0 countdown type status ? ro. this bit reflects the current countdown type. 0 = binary countdown 1 = binary coded decimal (bcd) countdown. lpc interface bridge registers (d31:f0) 356 intel ? ich8 family datasheet 9.3.3 counter access ports register (lpc i/f?d31:f0) i/o address: counter 0 ? 40h, counter 1 ? 41h, attribute: r/w counter 2 ? 42h default value: all bits undefined size: 8 bit 9.4 8259 interrupt controller (pic) registers (lpc i/f?d31:f0) 9.4.1 interrupt controller i/o map (lpc i/f?d31:f0) the interrupt controller registers are located at 20h and 21h for the master controller (irq 0?7), and at a0h and a1h for the slave controller (irq 8?13). these registers have multiple functions, dependin g upon the data written to them. table 107 shows the different register possibilities for each address. note: refer to note addressing active-low interrupt sources in 8259 interrupt controllers section ( chapter 5.8 ). bit description 7:0 counter port ? r/w. each counter port address is used to program the 16-bit count register. the order of progra mming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control regi ster at port 43h. the counter port is also used to read the current count from the coun t register, and return the status of the counter programming follow ing a read back command. table 107. pic registers (lpc i/f?d31:f0) port aliases register name default value type 20h 24h, 28h, 2ch, 30h, 34h, 38h, 3ch master pic icw1 init. cmd word 1 undefined wo master pic ocw2 op ctrl word 2 001xxxxxb wo master pic ocw3 op ctrl word 3 x01xxx10b wo 21h 25h, 29h, 2dh, 31h, 35h, 39h, 3dh master pic icw2 init. cmd word 2 undefined wo master pic icw3 init. cmd word 3 undefined wo master pic icw4 init. cmd word 4 01h wo master pic ocw1 op ctrl word 1 00h r/w a0h a4h, a8h, ach, b0h, b4h, b8h, bch slave pic icw1 init. cmd word 1 undefined wo slave pic ocw2 op ctrl word 2 001xxxxxb wo slave pic ocw3 op ctrl word 3 x01xxx10b wo a1h a5h, a9h, adh, b1h, b5h, b9h, bdh slave pic icw2 init. cmd word 2 undefined wo slave pic icw3 init. cmd word 3 undefined wo slave pic icw4 init. cmd word 4 01h wo slave pic ocw1 op ctrl word 1 00h r/w 4d0h ? master pic edge/level triggered 00h r/w 4d1h ? slave pic edge/level triggered 00h r/w intel ? ich8 family datasheet 357 lpc interface bridge registers (d31:f0) 9.4.2 icw1?initialization command word 1 register (lpc i/f?d31:f0) offset address: master controller ? 20h attribute: wo slave controller ? a0h size: 8 bit /controller default value: all bits undefined a write to initialization command word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. the interrupt mask register is cleared. 2. irq7 input is assigned priority 7. 3. the slave mode address is set to 7. 4. special mask mode is cleared and status read is set to irr. once this write occurs, the controller expects writes to icw2, icw3, and icw4 to complete the initialization sequence. bit description 7:5 icw/ocw select ? wo. these bits are mcs-85 specific, and not needed. 000 = should be programmed to ?000? 4 icw/ocw select ? wo. 1 = this bit must be a 1 to select icw1 and enable the icw2, icw3, and icw4 sequence. 3 edge/level bank select (ltim) ? wo. disabled. replac ed by the edge/level triggered control registers (elc r, d31:f0:4d0h, d31:f0:4d1h). 2 adi ? wo. 0 = ignored for the ich8. should be programmed to 0. 1 single or cascade (sngl) ? wo. 0 = must be programmed to a 0 to indicate two controllers operating in cascade mode. 0 icw4 write required (ic4) ? wo. 1 = this bit must be programmed to a 1 to indicate that icw4 needs to be programmed. lpc interface bridge registers (d31:f0) 358 intel ? ich8 family datasheet 9.4.3 icw2?initialization command word 2 register (lpc i/f?d31:f0) offset address: master controller ? 21h attribute: wo slave controller ? a1h size: 8 bit /controller default value: all bits undefined icw2 is used to initialize the interrupt contro ller with the five most significant bits of the interrupt vector address. the value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each irq on the controller. typical isa icw2 values are 08h for the master controller and 70h for the slave controller. 9.4.4 icw3?master controller initialization command word 3 register (lpc i/f?d31:f0) offset address: 21h attribute: wo default value: all bits undefined size: 8 bits bit description 7:3 interrupt vector base address ? wo. bits [7:3] define the base address in the interrupt vector table for the interrupt routines as sociated with each interrupt request level input. 2:0 interrupt request level ? wo. when writing icw2, these bits should all be 0. during an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. this is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second inta# cycle. the code is a three bit binary code: code master interrupt slave interrupt 000b irq0 irq8 001b irq1 irq9 010b irq2 irq10 011b irq3 irq11 100b irq4 irq12 101b irq5 irq13 110b irq6 irq14 111b irq7 irq15 bit description 7:3 0 = these bits must be programmed to 0. 2 cascaded interrupt controller irq connection ? wo. this bit indicates that the slave controller is cascaded on irq2. when irq8#?irq15 is asserted, it goes through the slave controller?s priority resolver. the slave controller?s intr output onto irq2. irq2 then goes through the master controlle r?s priority solver. if it wins, the intr signal is asserted to the processor, and th e returning interrupt ac knowledge returns the interrupt vector for the slave controller. 1 = this bit must always be programmed to a 1. 1:0 0 = these bits must be programmed to 0. intel ? ich8 family datasheet 359 lpc interface bridge registers (d31:f0) 9.4.5 icw3?slave controller initialization command word 3 register (lpc i/f?d31:f0) offset address: a1h attribute: wo default value: all bits undefined size: 8 bits 9.4.6 icw4?initialization command word 4 register (lpc i/f?d31:f0) offset address: master controller ? 021h attribute: wo slave controller ? 0a1h size: 8 bits default value: 01h bit description 7:3 0 = these bits must be programmed to 0. 2:0 slave identification code ? wo. these bits are compared against the slave identification code broadcast by the master co ntroller from the trailing edge of the first internal inta# pulse to the trailing edge of the second internal inta# pulse. these bits must be programmed to 02h to match the co de broadcast by the master controller. when 02h is broadcast by the master contro ller during the inta# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. bit description 7:5 0 = these bits must be programmed to 0. 4 special fully nested mode (sfnm) ? wo. 0 = should normally be disabled by writing a 0 to this bit. 1 = special fully nested mode is programmed. 3 buffered mode (buf) ? wo. 0 = must be programmed to 0 for the ich8. this is non-buffered mode. 2 master/slave in buffered mode ? wo. not used. 0 = should always be programmed to 0. 1 automatic end of interrupt (aeoi) ? wo. 0 = this bit should normally be programmed to 0. this is the normal end of interrupt. 1 = automatic end of interrupt (aeoi) mode is programmed. 0 microprocessor mode ? wo. 1 = must be programmed to 1 to indicate that the controller is operating in an intel architecture-based system. lpc interface bridge registers (d31:f0) 360 intel ? ich8 family datasheet 9.4.7 ocw1?operational contro l word 1 (interrupt mask) register (lpc i/f?d31:f0) offset address: master controller ? 021h attribute: r/w slave controller ? 0a1h size: 8 bits default value: 00h 9.4.8 ocw2?operational control word 2 register (lpc i/f?d31:f0) offset address: master controller ? 020h attribute: wo slave controller ? 0a0h size: 8 bits default value: bit[4:0]=undefined, bit[7:5]=001 following a part reset or icw initialization, the controller enters the fully nested mode of operation. non-specific eoi without rotati on is the default. both rotation mode and specific eoi mode are disabled following initialization. bit description 7:0 interrupt request mask ? r/w. when a 1 is written to any bit in this register, the corresponding irq line is masked. when a 0 is written to any bit in this register, the corresponding irq mask bit is cleared, and in terrupt requests will again be accepted by the controller. masking irq2 on the master controller will also mask the interrupt requests from the slave controller. bit description 7:5 rotate and eoi codes (r, sl, eoi) ? wo. these three bits control the rotate and end of interrupt modes and combinations of the two. 000 = rotate in auto eoi mode (clear) 001 = non-specific eoi command 010 = no operation 011 = *specific eoi command 100 = rotate in auto eoi mode (set) 101 = rotate on non-specific eoi command 110 = *set priority command 111 = *rotate on specific eoi command *l0 ? l2 are used 4:3 ocw2 select ? wo. when selecting ocw2, bits 4:3 = ?00? 2:0 interrupt level select (l2, l1, l0) ? wo. l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined below, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; prog ramming l2, l1 and l0 to 0 is sufficient in this case. code interrupt level c ode interrupt level 000b irq0/8 000b irq4/12 001b irq1/9 001b irq5/13 010b irq2/10 010b irq6/14 011b irq3/11 011b irq7/15 intel ? ich8 family datasheet 361 lpc interface bridge registers (d31:f0) 9.4.9 ocw3?operational control word 3 register (lpc i/f?d31:f0) offset address: master controller ? 020h attribute: wo slave controller ? 0a0h size: 8 bits default value: bit[6,0]=0, bit[7,4:2]=undefined, bit[5,1]=1 bit description 7 reserved. must be 0. 6 special mask mode (smm) ? wo. 1 = the special mask mode can be used by an interrupt service ro utine to dynamically alter the system priority structure while th e routine is executing, through selective enabling/disabling of the other channel's mask bits. bit 5, the esmm bit, must be set for this bit to have any meaning. 5 enable special mask mode (esmm) ? wo. 0 = disable. the smm bit becomes a ?don't care?. 1 = enable the smm bit to set or reset the special mask mode. 4:3 ocw3 select ? wo. when selecting ocw3, bits 4:3 = 01 2 poll mode command ? wo. 0 = disable. poll command is not issued. 1 = enable. the next i/o read to the interru pt controller is treated as an interrupt acknowledge cycle. an encoded byte is driv en onto the data bus, representing the highest priority level requesting service. 1:0 register read command ? wo. these bits provide cont rol for reading the in-service register (isr) and the interrupt request regi ster (irr). when bit 1=0, bit 0 will not affect the register read sele ction. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. if bit 0=0, the irr will be read. if bit 0=1, the isr will be read. following icw initialization, th e default ocw3 port address read will be ?read irr?. to retain the curre nt selection (read isr or read irr), always write a 0 to bit 1 when programming this register. the se lected register can be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. 00 = no action 01 = no action 10 = read irq register 11 = read is register lpc interface bridge registers (d31:f0) 362 intel ? ich8 family datasheet 9.4.10 elcr1?master controller edge/level trig gered register (lpc i/f?d31:f0) offset address: 4d0h attribute: r/w default value: 00h size: 8 bits in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the cascade channel, irq2, the heart beat timer (irq 0), and the keyboard controller (irq1), cannot be put into level mode. bit description 7 irq7 ecl ? r/w. 0 = edge. 1 = level. 6 irq6 ecl ? r/w. 0 = edge. 1 = level. 5 irq5 ecl ? r/w. 0 = edge. 1 = level. 4 irq4 ecl ? r/w. 0 = edge. 1 = level. 3 irq3 ecl ? r/w. 0 = edge. 1 = level. 2:0 reserved. must be 0. intel ? ich8 family datasheet 363 lpc interface bridge registers (d31:f0) 9.4.11 elcr2?slave controller e dge/level triggered register (lpc i/f?d31:f0) offset address: 4d1h attribute: r/w default value: 00h size: 8 bits in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recogn ized by a high level. the real time clock, irq8#, and the floating point error interru pt, irq13, cannot be programmed for level mode. bit description 7 irq15 ecl ? r/w. 0 = edge 1 = level 6 irq14 ecl ? r/w. 0 = edge 1 = level 5 reserved. must be 0. 4 irq12 ecl ? r/w. 0 = edge 1 = level 3 irq11 ecl ? r/w. 0 = edge 1 = level 2 irq10 ecl ? r/w. 0 = edge 1 = level 1 irq9 ecl ? r/w. 0 = edge 1 = level 0 reserved. must be 0. lpc interface bridge registers (d31:f0) 364 intel ? ich8 family datasheet 9.5 advanced programmable interrupt controller (apic)(d31:f0) 9.5.1 apic register map (lpc i/f?d31:f0) the apic is accessed via an indirect addre ssing scheme. two registers are visible by software for manipulation of most of the apic registers. these registers are mapped into memory space. the address bits 15:12 of the address range are programmable through bit 7:4 of oic register (chipset configuration register, offset 31ffh.) the registers are shown in table 108 . table 109 lists the registers which can be accessed within the apic via the index register. when accessing these registers, accesses must be done one dword at a time. for example, software should never access byte 2 from the data register before accessing bytes 0 and 1. the hardware will not attempt to recover from a bad programming model in this case. 9.5.2 ind?index regist er (lpc i/f?d31:f0) memory address fec0_0000h attribute: r/w default value: 00h size: 8 bits the index register will select which apic indirect register to be manipulated by software. the selector values for the indirect registers are listed in table 109 . software will program this register to select the desired apic internal register . table 108. apic direct re gisters (lpc i/f?d31:f0) address mnemonic register name size type fec0_0000h ind index 8 bits r/w fec0_0010h dat data 32 bits r/w feco_0040h eoir eoi 32 bits wo table 109. apic indirect re gisters (lpc i/f?d31:f0) index mnemonic register name size type 00 id identification 32 bits r/w 01 ver version 32 bits ro 02?0f ? reserved ? ro 10?11 redir_tbl0 redirection table 0 64 bits r/w, ro 12?13 redir_tbl1 redirection table 1 64 bits r/w, ro ... ... ... ... ... 3e?3f redir_tbl23 redirection table 23 64 bits r/w, ro 40?ff ? reserved ? ro bit description 7:0 apic index ? r/w. this is an 8-bit pointer into the i/o apic register table. intel ? ich8 family datasheet 365 lpc interface bridge registers (d31:f0) 9.5.3 dat?data register (lpc i/f?d31:f0) memory address fec0_0010h attribute: r/w default value: 00000000h size: 32 bits this is a 32-bit register specifying the data to be read or written to the register pointed to by the index register. this register can only be accessed in dword quantities. 9.5.4 eoir?eoi register (lpc i/f?d31:f0) memory address fec0h_0040h attribute: wo default value: n/a size: 32 bits the eoi register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. when a write is issued to this register, th e i/o apic will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, the remote_irr bit (index offset 10h, bit 14) for that i/o redirection entry will be cleared. note: if multiple i/o redirection entries, for any reason, assign the same vector for more than one interrupt input, each of those entr ies will have the remote_irr bit reset to 0. the interrupt which was prematurely reset will not be lost because if its input remained active when the remote_irr bit is cleared, the interrupt will be reissued and serviced at a later time. note: only bits 7:0 are ac tually used. bits 31:8 are ignored by the ich8. note: to provide for future expansion, the proce ssor should always write a value of 0 to bits 31:8. bit description 7:0 apic data ? r/w. this is a 32-bit register for the da ta to be read or written to the apic indirect register ( figure 109 ) pointed to by the index register (memory address fec0_0000h). bit description 31:8 reserved. to provide for future expansion, th e processor should always write a value of 0 to bits 31:8. 7:0 redirection entry clear ? wo. when a write is issued to this register, the i/o apic will check this field, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, th e remote_irr bit for that i/o redirection entry will be cleared. lpc interface bridge registers (d31:f0) 366 intel ? ich8 family datasheet 9.5.5 id?identification re gister (lpc i/f?d31:f0) index offset: 00h attribute: r/w default value: 00000000h size: 32 bits the apic id serves as a physical name of the apic. the apic bus arbitration id for the apic is derived from its i/o apic id. this register is reset to 0 on power-up reset. 9.5.6 ver?version regist er (lpc i/f?d31:f0) index offset: 01h attribute: ro default value: 00170020h size: 32 bits each i/o apic contains a hardwired version register that identifies different implementation of apic and their versions . the maximum redirection entry information also is in this register, to let software kn ow how many interrupt are supported by this apic. bit description 31:28 reserved 27:24 apic id ? r/w. software must program th is value before using the apic. 23:16 reserved 15 scratchpad bit. 14:0 reserved bit description 31:24 reserved 23:16 maximum redirection entries ? ro. this is the entry number (0 being the lowest entry) of the highest entry in the redirection table. it is equal to the number of interrupt input pins minus one and is in the range 0 through 239. in the ich8 this field is hardwired to 17h to indicate 24 interrupts. 15 prq ? ro. indicate that the ioxapic does not implement the pin assertion register. 14:8 reserved 7:0 version ? ro. this is a version number that iden tifies the implementation version. intel ? ich8 family datasheet 367 lpc interface bridge registers (d31:f0) 9.5.7 redir_tbl?redirection table (lpc i/f?d31:f0) index offset: 10h ? 11h (vector 0) through attribute: r/w, ro 3e ? 3fh (vector 23) default value: bit 16 = 1,. size: 64 bits each, (accessed as all other bits undefined two 32 bit quantities) the redirection table has a dedicated entry for each interrupt input pin. the information in the redirection table is used to translate the interrupt manifestation on the corresponding interrupt pin into an apic message. the apic will respond to an edge triggered in terrupt as long as the interrupt is held until after the acknowledge cycle has begun. once the interrupt is detected, a delivery status bit internally to the i/o apic is se t. the state machine will step ahead and wait for an acknowledgment from the apic unit th at the interrupt message was sent. only then will the i/o apic be able to recognize a new edge on that interrupt pin. that new edge will only result in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from 0 to 1. (in other words, if the interrupt was not already pending at the destination.) bit description 63:56 destination ? r/w. if bit 11 of this entry is 0 (physical), then bits 59:56 specifies an apic id. in this case, bits 63:59 shou ld be programmed by software to 0. if bit 11 of this entry is 1 (logical), then bits 63:56 specify the logical destination address of a set of processors. 55:48 extended destination id (edid) ? ro. these bits are sent to a local apic only when in processor system bus mode. th ey become bits 11:4 of the address. 47:17 reserved 16 mask ? r/w. 0 = not masked: an edge or level on this in terrupt pin results in the delivery of the interrupt to the destination. 1 = masked: interrupts are not delivered nor held pending. setting this bit after the interrupt is accepted by a local apic has no effect on that inte rrupt. this behavior is identical to the device withdrawing th e interrupt before it is posted to the processor. it is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been ac cepted by a local apic unit but before the interrupt is dispen sed to the processor. 15 trigger mode ? r/w. this field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = edge triggered. 1 = level triggered. 14 remote irr ? r/w. this bit is used for level triggered interrupts; its meaning is undefined for edge tr iggered interrupts. 0 = reset when an eoi message is received from a local apic. 1 = set when local apic/s accept the level interrupt sent by the i/o apic. 13 interrupt input pin polarity ? r/w. this bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = active high. 1 = active low. 12 delivery status ? ro. this field contains the current st atus of the delivery of this interrupt. writes to th is bit have no effect. 0 = idle. no activity for this interrupt. 1 = pending. interrupt has been inject ed, but delivery is not complete. lpc interface bridge registers (d31:f0) 368 intel ? ich8 family datasheet note: delivery mode encoding: 000 = fixed. deliver the signal on the intr signal of all processor cores listed in the destination. trigger mode can be edge or level. 001 = lowest priority. deliver the signal on the intr signal of the processor core that is executing at the lowest priority among all the processors listed in the specified dest ination. trigger mode can be edge or level. 010 = smi (system management in terrupt). requires th e interrupt to be pr ogrammed as edge triggered. the vector informat ion is ignored but must be programmed to all 0?s for future compatibility: not supported 011 = reserved 100 = nmi. deliver the signal on the nmi signal of all processor cores listed in the destination. vector information is ignored. nmi is treated as an edge triggered inte rrupt even if it is programmed as level triggered. for proper oper ation this redirection table entry must be programmed to edge triggered. the nmi delivery mode does not set the rirr bit. if the redirection table is incorrectly set to level, the loop count will co ntinue counting through the redirection table addresses. once the co unt for the nmi pin is reached again, the interrupt will be sent again: not supported 101 = init. deliver the signal to all processor cores listed in the destination by asserting the ini t signal. all addressed local apics will assume thei r init state. init is always treated as an edge triggered interrupt even if programmed as level triggered. for proper operation this redirection table entry must be programmed to edge triggered. the init delivery mode does not set the rirr bit. if the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. once the count for the init pin is reached again, the inte rrupt will be sent again: not supported 110 = reserved 111 = extint. deliver the signal to the intr signal of all processor cores listed in the destination as an interrupt that originated in an exte rnally connected 8259a compatible interrupt controller. the inta cycle that corresponds to this extint delivery will be routed to the external controller that is expected to supply the vector. requires the interrupt to be programmed as edge triggered. 11 destination mode ? r/w. this field dete rmines the interpretati on of the destination field. 0 = physical. destination apic id is identified by bits 59:56. 1 = logical. destinations are identified by matching bit 63:56 with the logical destination in the destination format regi ster and logical destination register in each local apic. 10:8 delivery mode ? r/w. this field specifies how the apics listed in the destination field should act upon reception of this signal. certain delivery modes will only operate as intended when used in conjunction with a specific trigger mode. these encodings are listed in the note below: 7:0 vector ? r/w. this field contains the interrupt vector for this interrupt. values range between 10h and feh. bit description intel ? ich8 family datasheet 369 lpc interface bridge registers (d31:f0) 9.6 real time clock regi sters (lpc i/f?d31:f0) 9.6.1 i/o register addres s map (lpc i/f?d31:f0) the rtc internal registers and ram are or ganized as two banks of 128 bytes each, called the standard and extended banks. the first 14 bytes of the standard bank contain the rtc time and date information along with four registers, a?d, that are used for configuration of the rtc. the extended bank contains a full 128 bytes of battery backed sram, and will be accessible even when the rtc module is disabled (via the rtc configuration register). registers a?d do not physically exist in the ram. all data movement between the host processor and the real-time clock is done through registers mapped to the standard i/o space. the register map appears in table 110 . notes: 1. i/o locations 70h and 71h are the standard legacy location for the real-time clock. the map for this bank is shown in table 111 . locations 72h and 73h are for accessing the extended ram. the extended ram bank is also accessed using an indexed scheme. i/o address 72h is used as the address pointer and i/o address 73h is used as the data register. index addresses above 127h are not valid. if the extended ram is not needed, it may be disabled. 2. software must preserve the value of bit 7 at i/o addresses 70h and 74h. when writing to this address, software must firs t read the value, and then write the same value for bit 7 during the sequential address write. note that port 70h is not directly readable. the only way to read this register is through alt access mode. although rtc index bits 6:0 are readable fr om port 74h, bit 7 will always return 0. if the nmi# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. table 110. rtc i/o registers (lpc i/f?d31:f0) i/o locations if u128e bit = 0 function 70h and 74h also alias to 72h and 76h real- time clock (standard ram) index register 71h and 75h also alias to 73h and 77h real-time clock (standard ram) target register 72h and 76h extended ram index register (if enabled) 73h and 77h extended ram targ et register (if enabled) lpc interface bridge registers (d31:f0) 370 intel ? ich8 family datasheet 9.6.2 indexed registers (lpc i/f?d31:f0) the rtc contains two sets of indexed registers that are accessed using the two separate index and target registers (70/71h or 72/73h), as shown in table 111 . table 111. rtc (standard) ra m bank (lpc i/f?d31:f0) index name 00h seconds 01h seconds alarm 02h minutes 03h minutes alarm 04h hours 05h hours alarm 06h day of week 07h day of month 08h month 09h year 0ah register a 0bh register b 0ch register c 0dh register d 0eh?7fh 114 bytes of user ram intel ? ich8 family datasheet 371 lpc interface bridge registers (d31:f0) 9.6.2.1 rtc_rega?register a (lpc i/f?d31:f0) rtc index: 0a attribute: r/w default value: undefined size: 8-bit lockable: no power well: rtc this register is used for general configuratio n of the rtc functions. none of the bits are affected by rsmrst# or any other ich8 reset signal. bit description 7 update in progress (uip) ? r/w. this bit may be monito red as a status flag. 0 = the update cycle will not start for at least 488 s. the time, calendar, and alarm information in ram is always av ailable when the uip bit is 0. 1 = the update is soon to occur or is in progress. 6:4 division chain select (dv[2:0]) ? r/w. these three bits contro l the divider chain. the division chain itself is reset by rsmrst# to all 0?s and it can also be cleared to 0?s by firmware thru programming of dv. the pe riodic event (setting of rtcis.pf and the associated interrupt) can be based on the time as measur ed from rsmrst# deassertion until a divider reset (dv=?11x? to ?010?) is performed by firmware. dv2 corresponds to bit 6. 010 = normal operation 11x = divider reset 101 = bypass 15 stages (test mode only) 100 = bypass 10 stages (test mode only) 011 = bypass 5 stages (test mode only) 001 = invalid 000 = invalid 3:0 rate select (rs[3:0]) ? r/w. selects one of 13 taps of the 15 stage divider chain. the selected tap can generate a periodic interrupt if the pi e bit is set in register b. otherwise this tap will set the pf flag of register c. if the periodic interrupt is not to be used, these bits should all be set to 0. rs3 corresponds to bit 3. 0000 = interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 s 0100 = 244.141 s 0101 = 488.281 s 0110 = 976.5625 s 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms lpc interface bridge registers (d31:f0) 372 intel ? ich8 family datasheet 9.6.2.2 rtc_regb?register b (general configuration) (lpc i/f?d31:f0) rtc index: 0bh attribute: r/w default value: u0u00uuu (u: undefined) size: 8-bit lockable: no power well: rtc bit description 7 update cycle inhibit (set) ? r/w. enables/inhibits the update cycles. this bit is not affected by rsmrst# nor any other reset signal. 0 = update cycle occurs normally once each second. 1 = a current update cy cle will abort and subs equent update cycles will not occur until set is returned to 0. when set is one, the bios may in itialize time and calendar bytes safely. note: this bit should be set then cleared ea rly in bios post after each powerup directly after coin-cell battery insertion. 6 periodic interrupt enable (pie) ? r/w. this bit is cleare d by rsmrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur with a time base set with the rs bits of register a. 5 alarm interrupt enable (aie) ? r/w. this bit is cleared by rtcrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur when the af is set by an alarm match from the update cycle. an alarm can occur once a se cond, one an hour, once a day, or one a month. 4 update-ended interrupt enable (uie) ? r/w. this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur when the update cycle ends. 3 square wave enable (sqwe) ? r/w. this bit serves no functi on in the ich8. it is left in this register bank to provide comp atibility with the motorola 146818b. the ich8 has no sqw pin. this bit is cleared by rsmrst#, but not on any other reset. 2 data mode (dm) ? r/w. this bit specifies either binary or bcd data representation. this bit is not affected by rs mrst# nor any other reset signal. 0 = bcd 1 = binary 1 hour format (hourform) ? r/w. this bit indicates the hour byte format. this bit is not affected by rsmrst# no r any other reset signal. 0 = twelve-hour mode. in twelve-hour mode, the seventh bit represents am as 0 and pm as one. 1 = twenty-four hour mode. 0 daylight savings enable (dse) ? r/w. this bit triggers two sp ecial hour updates per year. the days for the hour adjustment are those specified in united states federal law as of 1987, which is different than previous years. this bit is not affected by rsmrst# nor any other reset signal. 0 = daylight savings time updates do not occur. 1 = a) update on the fi rst sunday in april, where time increments from 1:59:59 am to 3:00:00 am. b) update on the last sunday in october when the time first reaches 1:59:59 am, it is changed to 1:00:00 am. the time must increment normally for at least two update cycles (seconds) previous to these conditions for the ti me change to occur properly. intel ? ich8 family datasheet 373 lpc interface bridge registers (d31:f0) 9.6.2.3 rtc_regc?register c (flag register) (lpc i/f?d31:f0) rtc index: 0ch attribute: ro default value: 00u00000 (u: undefined) size: 8-bit lockable: no power well: rtc writes to register c have no effect. 9.6.2.4 rtc_regd?register d (flag register) (lpc i/f?d31:f0) rtc index: 0dh attribute: r/w default value: 10uuuuuu (u: undefined) size: 8-bit lockable: no power well: rtc bit description 7 interrupt request flag (irqf) ? ro. irqf = (pf * pie) + (af * aie) + (uf *ufe). this bit also causes the rtc interrupt to be asserted. this bit is cleared upon rsmrst# or a read of register c. 6 periodic interrupt flag (pf) ? ro. this bit is cleared upon rsmrst# or a read of register c. 0 = if no taps are specified via the rs bits in register a, this flag will not be set. 1 = periodic interrupt flag will be 1 when the tap specified by the rs bits of register a is 1. 5 alarm flag (af) ? ro. 0 = this bit is cleared upon rtcrst# or a read of register c. 1 = alarm flag will be set after all alarm values match the current time. 4 update-ended flag (uf) ? ro. 0 = the bit is cleared upon rsmrst# or a read of register c. 1 = set immediately following an update cycle for each second. 3:0 reserved. will always report 0. bit description 7 valid ram and time bit (vrt) ? r/w. 0 = this bit should always be written as a 0 fo r write cycle, however it will return a 1 for read cycles. 1 = this bit is hardwired to 1 in the rtc power well. 6 reserved. this bit always returns a 0 and should be set to 0 for write cycles. 5:0 date alarm ? r/w. these bits store the date of month alarm value. if set to 000000b, then a don?t care state is as sumed. the host must configure the date alarm for these bits to do anything, yet they can be written at any time. if the date alarm is not enabled, these bits will return 0?s to mimi c the functionality of the motorola 146818b. these bits are not affected by any reset assertion. lpc interface bridge registers (d31:f0) 374 intel ? ich8 family datasheet 9.7 processor interface registers (lpc i/f?d31:f0) table 112 is the register address map for the processor interface registers. 9.7.1 nmi_sc?nmi status and control register (lpc i/f?d31:f0) i/o address: 61h attribute: r/w, ro default value: 00h size: 8-bit lockable: no power well: core table 112. processor interface pci regi ster address map (lpc i/f?d31:f0) offset mnemonic register name default type 61h nmi_sc nmi status and control 00h r/w, ro 70h nmi_en nmi enable 80h r/w (special) 92h port92 fast a20 and init 00h r/w f0h coproc_err coprocessor error 00h wo cf9h rst_cnt reset control 00h r/w bit description 7 serr# nmi source status (serr#_nmi_sts) ? ro. 1 = bit is set if a pci agent detected a syst em error and pulses th e pci serr# line and if bit 2 (pci_serr_en) is cleared. this in terrupt source is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 1 and then set it to 0. when writing to port 61h, this bit must be 0. note: this bit is set by any of the ich8 intern al sources of serr; this includes serr assertions forwarded from the secondary pci bus, errors on a pci express* port, or other inte rnal functions that generate serr#. 6 iochk# nmi source status (iochk_nmi_sts) ? ro. 1 = bit is set if an lpc agent (via serirq) asserted iochk# and if bit 3 (iochk_nmi_en) is cleared. th is interrupt source is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 1 and then set it to 0. when writing to port 61h, this bit must be a 0. 5 timer counter 2 out status (tmr2_out_sts) ? ro. this bit reflects the current state of the 8254 counter 2 output. counter 2 must be programmed following any pci reset for this bit to have a de terminate value. when writing to port 61h, this bit must be a 0. 4 refresh cycle toggle (ref_toggle) ? ro. this signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. when writing to port 61h, this bit must be a 0. 3 iochk# nmi enable (iochk_nmi_en) ? r/w. 0 = enabled. 1 = disabled and cleared. 2 pci serr# enable (pci_serr_en) ? r/w. 0 = serr# nmis are enabled. 1 = serr# nmis are di sabled and cleared. intel ? ich8 family datasheet 375 lpc interface bridge registers (d31:f0) 9.7.2 nmi_en?nmi enable (and real time clock index) register (lpc i/f?d31:f0) i/o address: 70h attribute: r/w (special) default value: 80h size: 8-bit lockable: no power well: core note: the rtc index field is write-only for normal op eration. this field can only be read in alt- access mode. note, however, that this register is aliased to port 74h (documented in), and all bits are readable at that address. 9.7.3 port92?fast a20 and init register (lpc i/f?d31:f0) i/o address: 92h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 1 speaker data enable ( spkr_dat_en) ? r/w. 0 = spkr output is a 0. 1 = spkr output is equivalent to the counter 2 out signal value. 0 timer counter 2 enable (tim_cnt2_en) ? r/w. 0 = disable 1 = enable bit description bits description 7 nmi enable (nmi_en) ? r/w (special). 0 = enable nmi sources. 1 = disable all nmi sources. 6:0 real time clock index address (rtc_indx) ? r/w (special). th is data goes to the rtc to select which register or cmos ram address is being accessed. bit description 7:2 reserved 1 alternate a20 gate (alt_a20_gate) ? r/w. this bit is or?d with the a20gate input signal to generate a20m# to the processor. 0 = a20m# signal can po tentially go active. 1 = this bit is set when init# goes active. 0 init_now ? r/w. when this bit transitions from a 0 to a 1, the ich8 will force init# active for 16 pci clocks. lpc interface bridge registers (d31:f0) 376 intel ? ich8 family datasheet 9.7.4 coproc_err?coproc essor error register (lpc i/f?d31:f0) i/o address: f0h attribute: wo default value: 00h size: 8-bits lockable: no power well: core 9.7.5 rst_cnt?reset control register (lpc i/f?d31:f0) i/o address: cf9h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core bits description 7:0 coprocessor error (coproc_err) ? wo. any value written to this register will cause ignne# to go active, if ferr# had ge nerated an internal irq13. for ferr# to generate an internal irq13, the coproc_err_en bit (chips et configuration register, offset 31ffh, bit 1) must be 1. bit description 7:4 reserved 3 full reset (full_rst) ? r/w. this bit is used to de termine the states of slp_s3#, slp_s4#, and slp_s5# after a cf9 hard rese t (sys_rst =1 and rst_cpu is set to 1), after pwrok going low (with rsmrst# high), or after two tco timeouts. 0 = ich8 will keep slp_s3#, slp_s4# and slp_s5# high. 1 = ich8 will drive slp_s3#, slp_s4# and slp_s5# low for 3 ? 5 seconds. note: when this bit is set, it also causes the full power cycle (slp_s3/4/5# assertion) in response to sysreset#, pwrok# , and watchdog timer reset sources. 2 reset cpu (rst_cpu) ? r/w. when this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as de termined by the sys_rst bit (bit 1 of this register). 1 system reset (sys_rst) ? r/w. this bit is used to determine a hard or soft reset to the processor. 0 = when rst_cpu bit goes from 0 to 1, the ich8 performs a soft reset by activating init# for 16 pci clocks. 1 = when rst_cpu bit goes from 0 to 1, the ich8 performs a hard reset by activating pltrst# and sus_stat# active for abou t 5-6 milliseconds. in this case, slp_s#3, slp_s4#, and slp_s5# state (a ssertion or de-assertion) depends on full_rst bit setting. the ich8 main power well is rese t when this bit is 1. it also resets the resume well bits (except for those noted throughout the datasheet). 0 reserved intel ? ich8 family datasheet 377 lpc interface bridge registers (d31:f0) 9.8 power management registers (pm?d31:f0) the power management registers are distributed within the pci device 31: function 0 space, as well as a separate i/o range. each register is described below. unless otherwise indicate, bits are in the main (core) power well. bits not explicitly defined in each register are assumed to be reserved. when writing to a reserved bit, the value should always be 0. software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0. 9.8.1 power management pci configuration registers (pm?d31:f0) table 113 shows a small part of the configuratio n space for pci device 31: function 0. it includes only those registers dedicated for power management. some of the registers are only used for legacy power management schemes. table 113. power manage ment pci register a ddress map (pm?d31:f0) offset mnemonic register name default type a0h gen_pmcon_1 general power management configuration 1 0000h r/w, ro, r/wo a2h gen_pmcon_2 general power management configuration 2 00h r/w, r/ wc a4h gen_pmcon_3 general power management configuration 3 00h r/w, r/ wc a9h cx-state_cnf cx state configuration (mobile only). 00h r/w aah c4-timing_cnt c4 timing control (mobile only). 00h r/w abh bm_break_en bm_break_en (mobile only) 00h r/w ach pmir power management initialization 00h r/w adh msc_fun miscellaneous functionality 00h r/w b0h qrt_sts quick resume technology status register (ich8dh only) 00h r/wc, ro b1h-b2h qrt_cntl1 quick resume technology control 1 register (ich8dh only) f000h r/w, ro, wo b3h qrt_cntl2 quick resume technology control 2 register (ich8dh only) 00h r/w, ro b8?bbh gpi_rout gpi route control 0000000 0h r/w lpc interface bridge registers (d31:f0) 378 intel ? ich8 family datasheet 9.8.1.1 gen_pmcon_1?general pm configuration 1 register (pm?d31:f0) offset address: a0h attribute: r/w, ro, r/wo default value: 0000h size: 16-bit lockable: no usage: acpi, legacy power well: core bit description 15:13 reserved 12 (desktop only) reserved 12 (mobile only) c4 disable: this bit di sables the c4 feature. 0 = enables c4 1 = disables c4 11 (desktop) reserved 11 (mobile only) c5_enable: this bit enables the c5 and c6 fe atures. when this bit is 0, the platform does not enable the c5 and c6 fe atures. when this bit is 1, the platform enables c5/c6 features. this bit also, along with gpio_use_sel[0 ] bit, enables selection of bm_busy#/ pmsync# function on ich pin as shown below: when this bit is 0: ? the r/w bits of the c5 exit timing register become scratchpad with no effect on hardware functions. ? i/o reads to the lvl5 and lvl6 registers will be retired normally, but with no other action. ? all attempts to enter deeper c-states that re quire a transition through the c5 timing logic will be ignored. 10 bios_pci_exp_en ? r/w. this bit acts as a glob al enable for the sci associated with the pci express* ports. 0 = the various pci express ports and (g )mch cannot cause the pci_exp_sts bit to go active. 1 = the various pci express ports and (g )mch can cause the pci_exp_sts bit to go active. 9 pwrbtn_lvl ? ro. this bit indicates the curre nt state of the pwrbtn# signal. 0 = low. 1 = high. 8 reserved 7 (desktop only) reserved 7 (mobile only) enter c4 when c3 invoked (c4onc3_en) ? r/w. if this bit is set, then when software does a lvl3 read, the ic h8 transitions to the c4 state. gpio_use_sel[0] c5_enable result 1 x gpio 0 0 bm_busy# 0 1 pmsync# intel ? ich8 family datasheet 379 lpc interface bridge registers (d31:f0) 6 i64_en . software sets this bit to indicate that the processor is an ia_64 processor, not an ia_32 processor. this may be used in various state machines where there are behavioral differences. 5 cpu slp# enable (cpuslp_en) ? r/w. 0 = disable. 1 = enables the cpuslp# signal to go acti ve in the s1 state. this reduces the processor power. note: cpuslp# will go active during intel speedstep ? technology transitions and on entry to c3 and c4 states even if this bit is not set. 4 smi_lock ? r/wo. when this bit is set, writes to the glb_smi_en bit (pmbase + 30h, bit 0) will have no effect. once th e smi_lock bit is set, writes of 0 to smi_lock bit will have no effect (i.e., on ce set, this bit can only be cleared by pltrst#). 3:2 (desktop only) reserved 3 (mobile only) intel speedstep enable (ss_en) ? r/w. 0 = intel speedstep technology logic is di sabled and the ss_cnt register will not be visible (reads to ss_cnt will return 00h and writes will have no effect). 1 = intel speedstep technology logic is enabled. 2 (mobile only) pci clkrun# enable (clkrun_en) ? r/w. 0 = disable. ich8 drives the clkrun# signal low. 1 = enable clkrun# logic to control the system pci clock via the clkrun# and stp_pci# signals. note: when the slp_en# bit is set, the ich8 drives the clkrun# signal low regardless of the state of the clkrun_en bit. this ensures that the pci and lpc clocks continue running during a transition to a sleep state. 1:0 periodic smi# rate select ( per_smi_sel) ? r/w. set by software to control the rate at which periodic smi# is generated. 00 = 64 seconds 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds bit description lpc interface bridge registers (d31:f0) 380 intel ? ich8 family datasheet 9.8.1.2 gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) offset address: a2h attribute: r/w, r/wc default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: resume bit description 7 dram initialization bit ? r/w. this bit does not effe ct hardware functionality in any way. bios is expected to set this bit prior to starting the dram initialization sequence and to clear this bit after completing the dram initialization sequence. bios can detect that a dram initializatio n sequence was interru pted by a reset by reading this bit during the boot sequence. ? if the bit is 1, then the dram initialization was interrupted. ? this bit is reset by the assertion of the rsmrst# pin. 6:5 (desktop only) reserved 6:5 (mobile only) cpu pll lock time (cplt) ? r/w. this field indicates the amount of time that the processor needs to lock its plls. this is used wherever timing t250?t274 (see chapter 23 ) applies. 00 = min 30.7 s (default) 01 = min 61.4 s 10 = min 122.8 s 11 = min 245.6 s it is the responsibility of the bios to prog ram the correct value in this field prior to the first transition to c3 or c4 states (or performing intel speedstep technology transitions). note: the new dpslp-to-slp bits (d31:fo:aah, bits 1:0) act as an override to these bits. note: these bits are not cleared by any type of reset except rsmrst# or a cf9 write 4 system reset status (srs) ? r/wc. software clears this bit by writing a 1 to it. 0 = sys_reset# button not pressed. 1 = ich8 sets this bit when the sys_reset# button is pressed. bi os is expected to read this bit and clear it, if it is set. note: this bit is also reset by rsmrst# and cf9h resets. 3 cpu thermal trip status (cts) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when pltrst# is inacti ve and thrmtrip# goes active while the system is in an s0 or s1 state. notes: 1. this bit is also reset by rsmrst#, an d cf9h resets. it is not reset by the shutdown and reboot associated with the cputhrmtrip# event. 2. the cf9h reset in the desc ription refers to cf9h ty pe core well reset which includes sys_rst#, pwrok/vrmpwrgd low, smbus hard reset, tco timeout. this type of reset will clear cts bit. intel ? ich8 family datasheet 381 lpc interface bridge registers (d31:f0) note: vrmpwrok is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the ich8. 9.8.1.3 gen_pmcon_3?general pm configuration 3 register (pm?d31:f0) offset address: a4h attribute: r/w, r/wc default value: 00h size: 16-bit lockable: no usage: acpi, legacy power well: rtc 2 minimum slp_s4# assertion width violation status ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = hardware sets this bit when the slp_s4# assertion width is less than the time programmed in the slp_s4# minimum as sertion width field (d31:f0:offset a4h:bits 5:4). the ich8 be gins the timer when slp_s4 # is asserted during s4/ s5 entry, or when the rsmrst# input is deasserted during g3 exit. note that this bit is functional regardless of the value in the slp_s4# assertion stretch enable (d31:f0:offset a4h:bit 3). note: this bit is reset by the assertion of th e rsmrst# pin, but ca n be set in some cases before the default value is readable. 1 cpu power failure (cpupwr_flr) ? r/w. 0 = software (typically bios) clears this bit by writing a 0 to it. 1 = indicates that the vrmpwrgd signal from the processor?s vrm went low while the system was in an s0 or s1 state. note: vrmpwrgd is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may no t be detected by the intel ich8. 0 pwrok failure (pwrok_flr) ? r/wc. 0 = software clears this bit by writing a 1 to it, or when the system goes into a g3 state. 1 = this bit will be set any time pwrok goes low, when the system was in s0, or s1 state. the bit will be cleare d only by software by writin g a 1 to this bit or when the system goes to a g3 state. note: see chapter 5.13.11.3 for more details about th e pwrok pin functionality. note: in the case of true pwrok failure, pwrok will go low first before the vrmpwrgd. bit description bit description 15:9 reserved 8 s4_state# pin disable ? r/w. 0 = the traditional slp_s4# signal (without me overrides) is driven on the s4_state# pin. 1 = the s4_state# pin functionality is disa bled and the pin can be used for other functionality. this bit is cleared by rtcrst#. 7:6 swsmi_rate_sel ? r/w. this field indicates when the swsmi timer will time out. valid values are: 00 = 1.5 ms 0.6 ms 01 = 16 ms 4 ms 10 = 32 ms 4 ms 11 = 64 ms 4 ms these bits are not cleared by an y type of reset except rtcrst#. lpc interface bridge registers (d31:f0) 382 intel ? ich8 family datasheet note: rsmrst# is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the ich8. 5:4 slp_s4# minimum assertion width ? r/w. this field indicates the minimum assertion width of the slp_s4 # signal to assure that th e drams have been safely power-cycled. valid values are: 11 = 1 to 2 seconds 10 = 2 to 3 seconds 01 = 3 to 4 seconds 00 = 4 to 5 seconds this value is used in two ways: 1. if the slp_s4# assertion width is ever shorter than this time, a status bit is set for bios to read when s0 is entered. 2. if enabled by bit 3 in this register, th e hardware will prevent the slp_s4# signal from deasserting within this minimum time pe riod after asserting. rtcrst# forces this field to the conservative default state (00b) 3 slp_s4# assertion stretch enable ? r/w. 0 = the slp_s4# minimum assertion time is 1 to 2 rtcclk. 1 = the slp_s4# signal minimally assert for the time specified in bits 5:4 of this register. this bit is cleared by rtcrst# 2 rtc power status (rtc_pwr_sts) ? r/w. this bit is set when rtcrst# indicates a weak or missing battery. the bit is not cl eared by any type of reset. the bit will remain set until the software clears it by writing a 0 back to this bit position. 1 power failure (pwr_flr) ? r/wc. this bit is in the rt c well, and is not cleared by any type of reset except rtcrst#. 0 = indicates that the trickle current has not failed since the last time the bit was cleared. software clears this bit by writing a 1 to it. 1 = indicates that the trickle current (from the main battery or trickle supply) was removed or failed. note: clearing cmos in an ich- based platform can be done by using a jumper on rtcrst# or gpi, or using safemode strap. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. 0 afterg3_en ? r/w. this bit determin es what state to go to when power is re-applied after a power failure (g3 state) . this bit is in the rtc well and is not cleared by any type of reset except writes to cf9h or rtcrst#. 0 = system will return to s0 stat e (boot) after power is re-applied. 1 = system will return to the s5 state (except if it was in s4, in which case it will return to s4). in the s5 state, the only enable d wake event is the power button or any enabled wake event that was preserved through the power failure. note: bit will be set when thrmtr ip#-based shutdown occurs. bit description intel ? ich8 family datasheet 383 lpc interface bridge registers (d31:f0) 9.8.1.4 gen_pmcon_lock?general power management configuration lock register offset address: a6h attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi power well: core this register is used to enable new c-state related modes. c bit description 7 (mobile only) unlocked c-state transition: this bit is set by hardware when a cpu power state (c-state) transition deeper than c2 oc curs and the c-state_config_lock bit is not set. this bit is cleared by pltr st# and is not writable by software. 6:2 (mobile only) 7:2 (desktop only) reserved 1 acpi_base_lock: when set to 1, this bit lock s down the acpi base address register (abase) at offs et 40h. the base address field becomes read-only. this bit becomes locked when a value of 1b is written to it. writes of 0 to this bit are always ignored. once locked by writing 1, the only way to clear this bit is to perform a platform reset. 0 (mobile only) c-state_config_lock : when set to 1, this bit locks down the c-state configuration parameters. the following configuration bits become read-only when this bit is set: ? geyserville_en (gen_pmcon_1, bit 3) ? ia64_en (gen_pmcon_1, bit 6) ? c4_disable (gen_pmcon_1, bit 12) ? cpu_pll_lock_time (gen_pmcon_2, bits 6:5) ? the entire c4 timing control register (c4_timing_cnt) ? the entire c5 exit timing register (c5_exit_timing_cnt) this bit becomes locked when a value of 1b is written to it. writes of 0 to this bit are always ignored. once locked by writing 1, the only way to clear this bit is to perform a platform reset. 0 (desktop only) reserved lpc interface bridge registers (d31:f0) 384 intel ? ich8 family datasheet 9.8.1.5 cx-state_cnf?cx state configuration register (pm?d31:f0) (mobile only) offset address: a9h attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: core this register is used to enable new c-state related modes. bit description 7 scratchpad (sp) ? r/w. 6:5 reserved 4 popdown mode enable (pdme) ? r/w. this bit is used in conjunction with the pume bit (d31:f0:a9h, bit 3). if pume is 0, then this bit must also be 0. 0 = the ich8 will not attempt to automatica lly return to a previous c3 or c4 state. 1 = when this bit is a 1 and intel ? ich8 observes that there are no bus master requests, it can return to a previous c3 or c4 state. note: this bit is separate from the pume bi t to cover cases where latency issues permit popup but not popdown. 3 popup mode enable (pume) ? r/w. when this bit is a 0, the ich8 behaves like ich5, in that bus master traffic is a break ev ent, and it will retu rn from c3/c4 to c0 based on a break event. see chapter 5.13.5 for additional deta ils on this mode. 0 = the ich8 will treat bus master traffic a break event, and will return from c3/c4 to c0 based on a break event. 1 = when this bit is a 1 and ich8 observes a bus master request, it will take the system from a c3 or c4 state to a c2 stat e and auto enable bus masters. this will let snoops and memory access occur. 2 report zero for bm_s ts (bm_sts_zero_en) ? r/w. 0 = the ich8 sets bm_sts (pmbase + 00h, bi t 4) if there is bus master activity from pci, pci express* and internal bus masters. 1 = when this bit is a 1, ich8 will not set the bm_sts if there is bus master activity from pci, pci express an d internal bus masters. notes: 1. if the bm_sts bit is already set when the bm_sts_zero_en bit is set, the bm_sts bit will remain set. software wi ll still need to clear the bm_sts bit. 2. it is expected that if the pume bi t (this register, bit 3) is set, the bm_sts_zero_en bit should also be se t. setting one without the other would mainly be for debug or errata workaround. 3. bm_sts will be set by lpc dma or lp c masters, even if bm_sts_zero_en is set. 1:0 reserved intel ? ich8 family datasheet 385 lpc interface bridge registers (d31:f0) 9.8.1.6 c4-timing_cnt?c4 timing control register (pm?d31:f0) (mobile only) offset address: aah attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: core this register is used to enable c-state related modes. bit description 7 reserved 6 slow-c4 exit enable ?when 1, this bit enables the slow-c4 exit functionality. 5:4 slow-c4 exit delay . this field selects the amount of time that the ich8 waits from deassertion of dprstp# until starting th e t266 timer when performing the slow-c4 exit. 3:2 dprslpvr to stpcpu ? r/w. this field selects the am ount of time that the ich8 waits for from the deassertion of dprslpvr to the deassertion of stp_cpu#. this provides a programmable time for the processor?s voltage to stabilize when exiting from a c4 state. thus, thus changes the value for t266. 1:0 dpslp-to-slp ? r/w. this field selects the dpslp# deassertion to cpu_slp# deassertion time (t270). normally this value is determined by the cpu_pll_lock_time field in th e gen_pmcon_2 register. when this field is non-zero, then the values in this register have higher priority. it is software?s responsibility to program these fields in a consistent manner. bits min max comment 00b 73 s 76 s default. compatible with 01b setting of t266 01b 67 s 70 s 10b 61 s 64 s compatible with 10b setting of t266 11b 46 s 49 s compatible with 11b setting of t266 bits t266 min t266 max comment 00b 95 s 101 s default 01b 22 s 28 s value used for ?fast? vrms 10b 34 s 40 s value used for ?fast? vrms 11b reserved bits t270 00b use value is cpu_pll_lock_time field (default is 30 s) 01b 20 s 10b 15 s 11b 10 s lpc interface bridge registers (d31:f0) 386 intel ? ich8 family datasheet 9.8.1.7 bm_break_en register (pm?d31:f0) (mobile only) offset address: abh attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: core bit description 7 ide_break_en ? r/w. 0 = parallel ide or serial ata traf fic will not act as a break event. 1 = parallel ide or serial ata traffic acts as a break event, even if the bm_sts- zero_en and popup_en bits are set. parallel ide or serial ata ma ster activity will cause bm_sts to be set and will cause a break from c3/c4. 6 pcie_break_en ? r/w. 0 = pci express* traffic will not act as a break event. 1 = pci express traffic acts as a break event, even if the bm_sts-zero_en and popup_en bits are set. pci express master activity will cause bm_sts to be set and will cause a break from c3/c4. 5 pci_break_en ? r/w. 0 = pci traffic will no t act as a break event. 1 = pci traffic acts as a break event, even if the bm_sts-zero_en and popup_en bits are set. pci master activity will cause bm_sts to be set and will cause a break from c3/c4. 4:3 reserved 2 ehci_break_en ? r/w. 0 = ehci traffic will not act as a break event. 1 = ehci traffic acts as a break event, even if the bm_sts-zero_en and popup_en bits are set. ehci master activity will cause bm_sts to be set and will cause a break from c3/c4. 1 uhci_break_en ? r/w. 0 = uhci traffic will not act as a break event. 1 = usb traffic from any of the internal uh cis acts as a break event, even if the bm_sts-zero_en and popup_en bits are se t. uhci master activity will cause bm_sts to be set and will cause a break from c3/c4. 0 az_break_en ? r/w. 0 = intel ? high definition audio traffic will not act as a break event. 1 = intel high definition audio traffic acts as a break event, even if the bm_sts- zero_en and popup_en bits are set. intel high definition audio master activity will cause bm_sts to be set and will cause a break from c3/c4. intel ? ich8 family datasheet 387 lpc interface bridge registers (d31:f0) 9.8.1.8 pmir?power management initialization register offset address: ach attribute: r/w, r/wl default value: 00000000h size: 32-bit 9.8.1.9 qrt_sts (pm?d31:f0): quick re sume technology status register (intel ? ich8dh only) offset address: b0h attribute: r/w default value: 00h size: 8-bit lockable: no usage: quick resume technology power well: resume bit description 31:21 reserved 20 cf9h global reset (cf9gr) ? r/w. when set, a cf9h writ e of 6h or eh will cause a global reset of both the host and the me part itions. if this bit is cleared, a cf9h write of 6h or eh will only reset the host partition. 19:0 reserved bit description 7:5 reserved 4 qrt_sci_now_sts ? r/wc: this bit goes active when software writes a ?1? to qrt_cnt1.sci_now_cnt. it can be enabled to cause an sci which will allow the qrt software to transition the reaction to an qrt event from an smi# handler to an sci handler. this bit remains set until a 1 is written to this bit position. once a 1 is written to this bit position, the logic will ?re-arm? to allow the bit to be set on the next write of ?1? to sci_now_cnt (offset b1h:bit 8). 3 qrt_pb_sci_sts ? r/wc: this bit goes active when the pwrbtn# pin goes from high to low (post-debounce). it can be en abled to cause an sci which will allow the qrt software to see when the power button has been pressed. it is a separate bit from pwrbtn_sts because the os clears the pw rbtn_sts bit and does not provide any indication to other (i.e. qrt) software. the qrt software clears qrt_pb_sci_sts by writing a 1 to this bit position. 2 reserved 1 qrt_pb_smi_sts ? r/wc: this bit goes active when the pwrbtn# pin goes from high to low (post-debounce). it can be enab led to cause an smi# which will allow the qrt software to see when the power button has been pressed. it is a separate bit from pwrbtn_sts because the os clears the pw rbtn_sts bit and does not provide any indication to other (i.e. qrt) software. the qrt software clears qrt_pb_smi_sts by writing a 1 to this bit position. 0 reserved. lpc interface bridge registers (d31:f0) 388 intel ? ich8 family datasheet 9.8.1.10 qrt_cnt1 (pm?d31:f0): qu ick resume technology control 1 register (intel ? ich8dh only) offset address: b1h attribute: r/w default value: 0000h size: 16-bit lockable: no usage: quick resume technology power well: resume bit description 15:10 reserved 9 smi_option_cnt ?r/w : when this bit is set to 1 the platform generates an smi when an qrt event occurs (rather than gene rating an sci). the smi handler can cause the sci by setting the sci_now_cnt. 8 sci_now_cnt ?wo : when software writes a ?1? to this bit, it causes qrt_sci_now_sts (offset b0:bit 4) to assert (which ca n be enabled to cause an sci). this allows the smi handler to cause the sci. 7 pwrbtn_int_en ?r/w : when this bit is set to 1, the qrt logic is enabled to intercept the power button to cause the qrt smi or sci, and not immediately setting the pwrbtn_sts bit. the qrt software will later set the pwrbtn_sts bit by setting the pwrbtn_evnt bit. note: this bit is effective only in s0. 6 pwrbtn_evnt ?wo : when this bit is set to 1 by software, the pwrbtn_sts bit is set to 1. this allows software to communicate pwr_btn event to os. notes: 1. power button ove rride still possible 2. software does not need to clear this bit, as it is treated as an event 5:4 qrt_state1_cnt[1:0] ?r/w : these bits controls th e qrt_state1 pin. the qrt_state[1:0] pins can be used to control a multi color led to indicate the platform power states to user. if qrt_led_own is 0 then these bits have no impact. 00 = low 01 = high 10 = blinking. note that the blink rate is ~ 1 hz 11 = reserved. software must not set this combination 3:2 qrt_state0_cnt[1:0] ?r/w : these bits controls th e qrt_state0 pin. the qrt_state[1:0] pins can be used to control a multi-color led to indicate the platform power states to user. if qrt_led_own is 0 then these bits have no impact. 00 = low 01 = high 10 = blinking. note that the blink rate is ~ 1 hz 11 = reserved. software must not set this combination 1 qrt_led_own ?r/w : software sets this bit to 1 to configure the multiplexed pins to be qrt_state[1:0] rather than gpio[28:27]. 0 reserved intel ? ich8 family datasheet 389 lpc interface bridge registers (d31:f0) 9.8.1.11 qrt_cnt2 (pm?d31:f0): qu ick resume technology control 2 register (intel ? ich8dh only) offset address: b3h attribute: r/w default value: 00h size: 8-bit lockable: no usage: quick resume technology power well: rtc 9.8.1.12 gpio_rout?gpio routing control register (pm?d31:f0) offset address: b8h ? bbh attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: resume note: gpios that are not implemented will not have the corresponding bits implemented in this register. bit description 7:1 reserved 0 qrt_en ?r/w : this bit enables quick resume technology 0 = qrt disabled 1 = qrt enabled when this bit is 0, the r/w bits of qr t control registers (qrt_cnt1, el_cnt2) scratchpad with no effect on hardware func tions. also, wo bits have no effect on hardware functions. bios software is expected to set this bit af ter booting. default value for this bit is 0. bit description 31:30 gpio15 route ? r/w. see bits 1:0 for description. same pattern for gpio14 through gpio3 5:4 gpio2 route ? r/w. see bits 1:0 for description. 3:2 gpio1 route ? r/w. see bits 1:0 for description. 1:0 gpio0 route ? r/w. gpio[15:0] can be routed to cause an smi or sci when the gpio[n]_sts bit is set. if the gpio0 is not set to an input, this field has no effect. if the system is in an s1?s5 state and if the gpe0_en bit is also set, then the gpio can cause a wake event, even if the gpio is not routed to cause an smi# or sci. 00 = no effect. 01 = smi# (if corresponding alt_gpi_smi_en bit is also set) 10 = sci (if corresponding gpe0_en bit is also set) 11 = reserved lpc interface bridge registers (d31:f0) 390 intel ? ich8 family datasheet 9.8.2 apm i/o decode table 114 shows the i/o registers associated with apm support. this register space is enabled in the pci device 31: function 0 space (apmdec_en), and cannot be moved (fixed i/o location). 9.8.2.1 apm_cnt?advanced powe r management control port register i/o address: b2h attribute: r/w default value: 00h size: 8-bit lockable: no usage: legacy only power well: core 9.8.2.2 apm_sts?advanced power management status port register i/o address: b3h attribute: r/w default value: 00h size: 8-bit lockable: no usage: legacy only power well: core table 114. apm register map address mnemonic register name default type b2h apm_cnt advanced power management control port 00h r/w b3h apm_sts advanced power management status port 00h r/w bit description 7:0 used to pass an apm command between the os and the smi handler. writes to this port not only store data in the apmc regi ster, but also generates an smi# when the apmc_en bit is set. bit description 7:0 used to pass data between the os and the smi handler. basically, this is a scratchpad register and is not affected by any other register or functi on (other than a pci reset). intel ? ich8 family datasheet 391 lpc interface bridge registers (d31:f0) 9.8.3 power management i/o registers table 115 shows the registers associated with acpi and legacy power management support. these registers are enabled in the pci device 31: function 0 space (pm_io_en), and can be moved to any i/o lo cation (128-byte aligned). the registers are defined to support the acpi 2.0 specification, and use the same bit names. note: all reserved bits and registers will always re turn 0 when read, and will have no effect when written. table 115. acpi and legacy i/o register map (sheet 1 of 2) pmbase + offset mnemonic register name acpi pointer default type 00h?01h pm1_sts pm1 status pm1a_evt_blk 0000h r/wc 02h?03h pm1_en pm1 enable pm1a_evt_blk+2 0000h r/w 04h?07h pm1_cnt pm1 control pm1a_cnt_blk 00000000h r/w, wo 08h?0bh pm1_tmr pm1 timer pmtmr_blk xx000000h ro 0ch?0fh ? reserved ? ? ? 10hh?13h proc_cnt processor control p_blk 00000000h r/w, ro, wo 14h lv2 level 2 (mobile only) p_blk+4 00h ro 15h?16h ? reserved (desktop only) ? ? ? 15h lv3 level 3 (mobile only) p_blk+5 00h ro 16h lv4 level 4 (mobile only) p_blk+6 00h ro 17h?18h ? reserved (desktop only) ? ? ? 17h lv5 level 5 (mobile only) p_blk+7 00h ro 18h lv6 level 6 (mobile only) p_blk+8 00h ro 19h ? reserved ? ? ? 20h ? reserved (desktop only) ? ? ? 20h pm2_cnt pm2 control (mobile only) pm2a_cnt_blk 00h r/w 28h?2bh gpe0_sts general purpose event 0 status gpe0_blk 00000000h r/wc 2ch?2fh gpe0_en general purpose event 0 enables gpe0_blk+4 00000000h r/w 30h?33h smi_en smi# control and enable ? 00000000h r/w, wo, r/w (special) 34h?37h smi_sts smi status ? 00000000h r/wc, ro 38h?39h alt_gp_smi_en alternate gpi smi enable ? 0000h r/w 3ah?3bh alt_gp_smi_sts alternate gpi smi status ? 0000h r/wc 3dh?41h ? reserved ? ? ? 42h gpe_cntl general purpose event control ? 00h ro, r/w 43h ? reserved ? ? ? 44h?45h devact_sts device activity status ? 0000h r/wc 46h?4fh ? reserved ? ? ? 50h ? reserved (desktop only) ? ? ? 50h ss_cnt intel speedstep ? technology control (mobile only) 01h r/w (special) 51h?53h ? reserved ? ? ? lpc interface bridge registers (d31:f0) 392 intel ? ich8 family datasheet 54h?5bh ? reserved (desktop only) ? ? ? 54h?57h c3_res c3-residency register (mobile only) ? 00000000h ro, r/w 58h?5bh c5_res c5-residency register (mobile only) ? 00000000h ro, r/w 5ch?5fh ? reserved ? ? ? 60h?7fh ? reserved for tco ? ? ? table 115. acpi and legacy i/o register map (s heet 2 of 2) pmbase + offset mnemonic register name acpi pointer default type intel ? ich8 family datasheet 393 lpc interface bridge registers (d31:f0) 9.8.3.1 pm1_sts?power management 1 status register i/o address: pmbase + 00h ( acpi pm1a_evt_blk ) attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 15: resume, except bit 11 in rtc if bit 10 or 8 in this register is set, an d the corresponding _en bit is set in the pm1_en register, then the ich8 will generate a wake event. once back in an s0 state (or if already in an s0 state when the event occurs), the ich8 will also generate an sci if the sci_en bit is set, or an smi# if the sci_en bit is not set. note: bit 5 does not cause an smi# or a wake event. bit 0 does not cause a wake event but can cause an smi# or sci. bit description 15 wake status (wak_sts) ? r/wc. this bit is not affect ed by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bi t by writing a 1 to it. 1 = set by hardware when the system is in one of the sleep states (via the slp_en bit) and an enabled wake event occurs. upon setting this bit, the ich8 will transition the system to the on state. if the afterg3_en bit is not set and a po wer failure (such as removed batteries) occurs without the slp_en bit set, the system will return to an s0 state when power returns, and the wak_sts bit will not be set. if the afterg3_en bit is set and a powe r failure occurs without the slp_en bit having been set, the system will go into an s5 state when power returns, and a subsequent wake event will cause the wak_sts bit to be set. note that any subsequent wake event would have to be ca used by either a power button press, or an enabled wake event that was preserved through the power failure (enable bit in the rtc well). 14 pci express wake status (pciexpwak_sts) ? r/wc. 0 = software clears this bit by writing a 1 to it. if the wake# pin is still active during the write or the pme message received indication has not been cleared in the root port, then the bit will remain active (i.e. all inputs to this bit are level- sensitive). 1 = this bit is set by hardware to indica te that the system woke due to a pci express wakeup event. this wakeup event can be caused by the pci express wake# pin being active or receipt of a pci express pme message at a root port. this bit is set only when one of these events causes the system to transition from a non-s0 system power state to the s0 system power state. this bit is set independent of the state of the pciexp_wake_dis bit. note: this bit does not itself cause a wa ke event or prevent entry to a sleeping state. thus if the bit is 1 and the system is put into a sleeping state, the system will not automatically wake. 13:12 reserved lpc interface bridge registers (d31:f0) 394 intel ? ich8 family datasheet 11 power button override status (prbtnor_sts) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a power button ov erride occurs (i.e., the power button is pressed for at least 4 consecutive second s), or due to the corresponding bit in the smbus slave message. the power butt on override causes an unconditional transition to the s5 state, as well as sets the afterg# bit. the bios or sci handler clears this bit by writing a 1 to it . this bit is not affe cted by hard resets via cf9h writes, and is not reset by rsmrst#. thus, this bit is preserved through power failures. note that if this bit is still asserted when the global sci_en is set then an sci will be generated. 10 rtc status (rtc_sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the rtc genera tes an alarm (assertion of the irq8# signal). additionally if the rtc_en bit (pmbase + 02h, bit 10) is set, the setting of the rtc_sts bit will generate a wake event. 9 me_sts : this bit is set when the me generates a non-maskable wake event, and is not affected by any other enable bit. wh en this bit is set, the host power management logic wakes to s0. this bit is only set by hardware and can on ly be reset by writin g a one to this bit position. this bit is not affected by hard re sets caused by a cf9 write, but is reset by rsmrst#. 8 power button status ( pwrbtn__sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write. 0 = if the pwrbtn# signal is held low for mo re than 4 seconds, the hardware clears the pwrbtn_sts bit, sets the pwrbtnor_sts bit, and the system transitions to the s5 state with only pwrbtn# enabled as a wake event. this bit can be cleared by software by writing a one to the bit position. 1 = this bit is set by hardware when the pwrbtn# signal is asserted low, independent of any other enable bit. in the s0 state, while pwrbtn_en and pwrbtn_sts are both set, an sci (or smi# if sci_en is not set) will be generated. in any sleeping state s1?s5, while pwrbtn_en (pmbase + 02h, bit 8) and pwrbtn_sts are both set, a wake event is generated. note: if the pwrbtn_sts bit is cleared by software while the pwrbtn# signal is sell asserted, this will not cause the pwrbn_sts bit to be set. the pwrbtn# signal must go inactive and active again to set the pwrbtn_sts bit. 7:6 reserved 5 global status (gbl _sts) ? r/wc. 0 = the sci handler should th en clear this bit by writing a 1 to the bit location. 1 = set when an sci is generated due to bios wanting the attention of the sci handler. bios has a corresponding bit, bios_rls, which will cause an sci and set this bit. 4 (desktop only) reserved bit description intel ? ich8 family datasheet 395 lpc interface bridge registers (d31:f0) 4 (mobile only) bus master status (bm_sts) ? r/wc. this bit will not cause a wake event, sci or smi#. 0 = software clears this bi t by writing a 1 to it. 1 = set by the ich8 when a bus master requests access to main memory. bus master activity is detected by any of th e pci requests being active, any internal bus master request being active, the bmbusy# sign al being active, or req-c2 message received while in c3 or c4 state. notes: 1. if the bm_sts_zero_en bit is set, then this bit will generally report as a 0. lpc dma and bus master activity will always set the bm_sts bit, even if the bm_sts_zero_en bit is set. 3:1 reserved 0 timer overflow status (tmrof_sts) ? r/wc. 0 = the sci or smi# handler clears this bit by writing a 1 to the bit location. 1 = this bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). this will oc cur every 2.3435 seconds. when the tmrof_en bit (pmbase + 02h, bit 0) is set, then the setting of the tmrof_sts bit will additionally gene rate an sci or smi# (depending on the sci_en). bit description lpc interface bridge registers (d31:f0) 396 intel ? ich8 family datasheet 9.8.3.2 pm1_en?power management 1 enable register i/o address: pmbase + 02h ( acpi pm1a_evt_blk + 2 ) attribute: r/w default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 9, 11 ? 15: resume, bit 10: rtc bit description 15 reserved 14 pci express* wake di sable(pciexpwak_dis) ? r/w. modification of this bit has no impact on the value of the pciexp_wake_sts bit. 0 = inputs to the pciexp_wake_sts bit in the pm1 status register enabled to wake the system. 1 = inputs to the pciexp_wake_sts bit in the pm1 status register disabled from waking the system 13:11 reserved 10 rtc event enable (rtc_en) ? r/w. this bit is in the rtc well to allow an rtc event to wake after a power failure. this bit is not cleared by any reset other than rtcrst# or a power button override event. 0 = no sci (or smi#) or wake event is ge nerated then rtc_sts (pmbase + 00h, bit 10) goes active. 1 = an sci (or smi#) or wake event will occur when this bit is set and the rtc_sts bit goes active. 9 reserved. 8 power button enable (pwrbtn_en) ? r/w. this bit is used to enable the setting of the pwrbtn_sts bit to generate a power management event (smi#, sci). pwrbtn_en has no effect on the pwrbtn_sts bit (pmbase + 00h, bit 8) being set by the assertion of the power bu tton. the power button is always enabled as a wake event. 0 = disable. 1 = enable. 7:6 reserved. 5 global enable (gbl_en) ? r/w. when both the gb l_en and the gbl_sts bit (pmbase + 00h, bit 5) are set, an sci is raised. 0 = disable. 1 = enable sci on gbl_sts going active. 4:1 reserved. 0 timer overflow interrupt enable (tmrof_en) ? r/w. works in conjunction with the sci_en bit (pmbase + 04h, bit 0) as described below: tmrof _ en sci _ en eff ec t w h en tmrof _ sts i s se t 0 x no smi# or sci 1 0 smi# 1 1 sci intel ? ich8 family datasheet 397 lpc interface bridge registers (d31:f0) 9.8.3.3 pm1_cnt?power management 1 control i/o address: pmbase + 04h ( acpi pm1a_cnt_blk ) attribute: r/w, wo default value: 00000000h size: 32-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 12: rtc, bits 13 ? 15: resume bit description 31:14 reserved. 13 sleep enable ( slp_en) ? wo. setting this bit causes the system to sequence into the sleep state defined by the slp_typ field. 12:10 sleep type (slp_typ) ? r/w. this 3-bit field defines the type of sleep the system should enter when the slp_en bit is set to 1. these bits are only reset by rtcrst#. 9:3 reserved. 2 global release (gbl_rls) ? wo. 0 = this bit always reads as 0. 1 = acpi software writes a 1 to this bit to raise an event to the bios. bios software has a corresponding enable and status bits to control its ability to receive acpi events. 1 (desktop only) reserved 1 (mobile only) bus master relo ad (bm_rld) ? r/w. this bit is treated as a scratchpad bit. this bit is reset to 0 by pltrst# 0 = bus master requests will no t cause a break from the c3 state. 1 = enable bus master requests (internal, external or bmbusy#) to cause a break from the c3 state. if software fails to set this bit before going to c3 state, ich8 will still return to a snoopable state from c3 or c4 stat es due to bus master activity. 0 sci enable ( sci_en) ? r/w. selects the sci interrupt or the smi# interrupt for various events including the bits in the pm1_ sts register (bit 10, 8, 0), and bits in gpe0_sts. 0 = these events will generate an smi#. 1 = these events will generate an sci. code master interrupt 000b on: typically maps to s0 state. 001b asserts stpclk#. puts processor in stop-grant state. optional to assert cpuslp# to put processor in sleep state: typically maps to s1 state. 010b reserved 011b reserved 100b reserved 101b suspend-to-ram. assert slp_s3 #: typically maps to s3 state. 110b suspend-to-disk. assert slp_s3#, an d slp_s4#: typically maps to s4 state. 111b soft off. assert slp_s3#, slp_s4#, and slp_s5#: typically maps to s5 state. lpc interface bridge registers (d31:f0) 398 intel ? ich8 family datasheet 9.8.3.4 pm1_tmr?power management 1 timer register i/o address: pmbase + 08h ( acpi pmtmr_blk ) attribute: ro default value: xx000000h size: 32-bit lockable: no usage: acpi power well: core 9.8.3.5 proc_cnt?processor control register i/o address: pmbase + 10h ( acpi p_blk ) attribute: r/w, ro, wo default value: 00000000h size: 32-bit lockable: no (bits 7:5 are write once)usage: acpi or legacy power well: core bit description 31:24 reserved 23:0 timer value (tmr_val) ? ro. returns the running count of the pm timer. this counter runs off a 3.579545 mhz clock (14.31818 mhz divided by 4). it is reset to 0 during a pci reset, and then continues counti ng as long as the system is in the s0 state. after an s1 state, the counter will not be reset (it wi ll continue counting from the last value in s0 state. anytime bit 22 of the timer goes high to low (bits referenced from 0 to 23), the tmrof_sts bit (pmbase + 00h, bit 0) is set. the high-to-low transition will occur every 2.3435 seconds. if the tmrof_en bit (pmbase + 02h, bit 0) is set, an sci interrupt is also generated. bit description 31:18 reserved 17 throttle status (thtl_sts) ? ro. 0 = no clock throttling is occurring (maximum processor performance). 1 = indicates that the clock state machine is throttling the processor performance. this could be due to the tht_en bit or the force_thtl bit being set. 16:9 reserved 8 force thermal throttling (force_thtl) ? r/w. software can set this bit to force the thermal throttling function. 0 = no forced throttling. 1 = throttling at the duty cycle specified in thrm_dty starts immediately, and no smi# is generated. intel ? ich8 family datasheet 399 lpc interface bridge registers (d31:f0) 7:5 thrm_dty ? wo. this write-once field determines the duty cycle of the throttling when the force_thtl bit is set. the duty cycle indicates the a pproximate percentage of time the stpclk# signal is asserted while in the throttle mode. the stpclk# throttle period is 1024 pciclks. note that the throttling only occurs if the system is in the c0 state. for mobile components, if in the c2, c3, or c4 state, no throttling occurs. once the thrm_dty field is written, any subs equent writes will have no effect until pltrst# goes active. 4 thtl_en ? r/w. when set and the system is in a c0 state, it enables a processor- controlled stpclk# throttling. the duty cy cle is selected in the thtl_dty field. 0 = disable 1 = enable 3:1 thtl_dty ? r/w. this field determ ines the duty cycle of the throttling when the thtl_en bit is set. the duty cycle indicate s the approximate perc entage of time the stpclk# signal is asserted (low) while in the throttle mode. the stpclk# throttle period is 1024 pciclks. 0 reserved bit description thrm_dty t h rott l e mo d e p c i cl oc k s 000b 50% (default) 512 001b 87.5% 896 010b 75.0% 768 011b 62.5% 640 100b 50% 512 101b 37.5% 384 110b 25% 256 111b 12.5% 128 thtl_dty t h rott l e mo d e p c i cl oc k s 000b 50% (default) 512 001b 87.5% 896 010b 75.0% 768 011b 62.5% 640 100b 50% 512 101b 37.5% 384 110b 25% 256 111b 12.5% 128 lpc interface bridge registers (d31:f0) 400 intel ? ich8 family datasheet 9.8.3.6 lv2 ? level 2 register (mobile only) i/o address: pmbase + 14h ( acpi p_blk+4 ) attribute: ro default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: core note: this register should not be used by intel ? ia64 processors or sy stems with more than 1 logical processor, unles s appropriate semaphoring software has been put in place to ensure that all threads/processo rs are ready for the c2 state when the read to this register occurs 9.8.3.7 lv3?level 3 register (mobile only) i/o address: pmbase + 15h ( acpi p_blk + 5 ) attribute: ro default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: core note: if the c4onc3_en bit is set, reads this register will initiate a lvl4 transition rather than a lvl3 transition. in the event th at software attempts to simultaneously read the lvl2 and lvl3 registers (which is invalid), the ich8 will ignore the lvl3 read, and only perform a c2 transition. note: this register should not be used by ia64 proc essors or systems with more than 1 logical processor, unless appropriate semaphoring soft ware has been put in place to ensure that all threads/processors are read y for the c3 state when the re ad to this register occurs. 9.8.3.8 lv4?level 4 register (mobile only) i/o address: pmbase + 16h ( acpi p_blk + 6 ) attribute: ro default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: core note: this register should not be used by ia64 proc essors or systems with more than 1 logical processor, unless appropriate semaphoring soft ware has been put in place to ensure that all threads/processors are read y for the c4 state when the re ad to this register occurs. bit description 7:0 reads to this register return al l 0s, writes to this register have no effect. reads to this register generate a ?enter a level 2 power state? (c2) to the clock control logic. this will cause the stpclk# signal to go active, an d stay active until a break event occurs. throttling (due either to thtl_en or force_thtl) will be ignored. bit description 7:0 reads to this register return all 0s, writes to this register have no effect. reads to this register generate a ?enter a c3 power state? to the clock control logic. the c3 state persists until a break event occurs. bit description 7:0 reads to this register return all 0s, writes to this register have no effect. reads to this register generate a ?enter a c4 power state? to the clock control logic. the c4 state persists until a break event occurs. intel ? ich8 family datasheet 401 lpc interface bridge registers (d31:f0) 9.8.3.9 lv5?level 5 register (mobile only) i/o address: pmbase + 17h ( acpi p_blk + 7 ) attribute: ro default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: core note: this register should not be used by ia-64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the c5 state when the read to this register occurs. 9.8.3.10 lv6?level 6 register (mobile only) i/o address: pmbase + 18h ( acpi p_blk + 8 ) attribute: ro default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: core note: this register should not be used by ia-64 pr ocessors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are read y for the c6 state when the re ad to this register occurs. 9.8.3.11 pm2_cnt?power manageme nt 2 control (mobile only) i/o address: pmbase + 20h ( acpi pm2_blk ) attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi power well: core bit description 7:0 reads to this register return al l 0?s, writes to this register have no effect. reads to this register generate a ?enter a c5 power state? to the clock control logic. the c5 state persists until a break event occurs. bit description 7:0 reads to this register return al l 0?s, writes to this register have no effect. reads to this register generate a ?enter a c6 power state? to the clock control logic. the c6 state persists until a break event occurs. bit description 7:1 reserved 0 arbiter disabl e (arb_dis) ? r/w this bit is essentiall y just a scratchpad bit for legacy software compatibility. software typicall y sets this bit to 1 prior to entering a c3 or c4 state. when a transition to a c3 or c4 state occurs, ich8 will automatically prevent any internal or external non-isoch bus masters from initiating any cycles up to the (g)mch. this blocking starts immediately upon the ich8 sending the go-c3 message to the (g)mch. the blocking stops when the ack-c2 message is received. note that this is not really blocking, in that messages (such as from pci express*) are just queued and held pending. lpc interface bridge registers (d31:f0) 402 intel ? ich8 family datasheet 9.8.3.12 gpe0_sts?general purpose event 0 status register i/o address: pmbase + 28h ( acpi gpe0_blk ) attribute: r/wc default value: 00000000h size: 32-bit lockable: no usage: acpi power well: resume this register is symmetrical to the gene ral purpose event 0 enable register. unless indicated otherwise below, if the corresponding _en bit is set, then when the _sts bit get set, the ich8 will generate a wake event. once back in an s0 state (or if already in an s0 state when the event occurs), the ich8 will also generate an sci if the sci_en bit is set, or an smi# if th e sci_en bit (pmbase + 04h, bit 0) is not set. bits 31:16 are reset by a cf9h write; bits 15:0 are not. all are reset by rsmrst#. bit description 31:16 gpion_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = these bits are set any time the corres ponding gpio is set up as an input and the corresponding gpio signal is high (or low if the corresponding gp_inv bit is set). if the corresponding enable bi t is set in the gpe0_en register, then when the gpio[n]_sts bit is set: ? if the system is in an s1?s5 state, the event will also wake the system. ? if the system is in an s0 state (or upon waki ng back to an s0 state), a sci will be caused depending on the gpio_rout bits (d31:f0:b 8h, bits 31:30) for the corresponding gpi. note: mapping is as follows: bit 31 corre sponds to gpio[15]... and bit 16 corresponds to gpio[0]. 15 reserved 14 usb4_sts ? r/wc. 0 = disable. 1 = set by hardware and can be reset by writing a one to this bit position or a resume well reset. this bit is set when usb uhci controller #4 needs to cause a wake. additionally if the usb4_en bit is set, the setting of the usb4_sts bit will generate a wake event. 13 pme_b0_sts ? r/wc. this bit will be set to 1 by the ich8 when any internal device with pci power manage ment capabilities on bus 0 asserts the equivalent of the pme# signal. additionally, if the pme_b0_en bit is set, and the system is in an s0 state, then the setting of the pme_b0_s ts bit will generate an sci (or smi# if sci_en is not set). if the pme_b0_sts bit is set, and the system is in an s1?s4 state (or s5 state due to slp_typ and slp_en), then the setting of the pme_b0_sts bit will generate a wake event, and an sci (or smi# if sci_en is not set) will be generated. if the system is in an s5 state due to power button override, then the pme_b0_sts bit will not cause a wake event or sci. the default for this bit is 0. writing a 1 to this bit position clears this bit. note : on ich8, hd audio wake events are changed to be repo rted in this bit. me ?maskable? wake events ar e also reported in this bit. 12 usb3_sts ? r/wc. 0 = disable. 1 = set by hardware and can be reset by writing a one to this bit position or a resume well reset. this bit is set when usb uhci controller #3 needs to cause a wake. additionally if the usb3_en bit is set, the setting of the usb3_sts bit will generate a wake event. intel ? ich8 family datasheet 403 lpc interface bridge registers (d31:f0) 11 pme_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = set by hardware when the pme# sign al goes active. additionally, if the pme_en bit is set, and the system is in an s0 state, then the setting of the pme_sts bit will generate an sci or smi# (if sci_en is not set). if the pme_en bit is set, and the system is in an s1?s4 state (or s5 state due to setting slp_typ and slp_en), then th e setting of the pme_sts bit will generate a wake event, and an sci will be generated. if the system is in an s5 state due to power button override or a power failure, then pme_sts will not cause a wake event or sci. 10 (ich8 base, ich8r, ich8do only) reserved 10 (ich8dh only) qrt_sci_sts ? r/wc: in desktop mode, when quick resume technology feature is enabled, this bit will be se t by hardware when the sci_now_cnt or qrt_pb_sci_sts bit goes high. software cl ears the bit by writing a 1 to the bit position. in desktop mode, when qrt feature is disabled, this bit will be treated as reserved. 10 (mobile only) batlow_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = batlow# not asserted 1 = set by hardware when the batlow# signal is asserted. 9 pci_exp_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = set by hardware to indicate that: ? the pme event message was received on one or more of the pci express* ports ? an assert pmegpe message received from the (g)mch via dmi notes: 1. the pci wake# pin has no impact on this bit. 2. if the pci_exp_sts bit went active due to an assert pmegpe message, then a deassert pmegpe message must be received prior to the software write in order for the bit to be cleared. 3. if the bit is not cleare d and the corresponding pci_exp_en bit is set, the level-triggered sci will remain active. 4. a race condition exists where the pci express device sends another pme message because the pci express device was not serviced within the time when it must re send the message. this may re sult in a spurious interrupt, and this is comprehended and approved by the pci express* specification, revision 1.0a . the window for this race cond ition is approximately 95-105 milliseconds. 8 ri_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = set by hardware when the ri# input signal goes active. bit description lpc interface bridge registers (d31:f0) 404 intel ? ich8 family datasheet 7 smbus wake status (smb_wak_sts) ? r/wc. the smbus controller can independently cause an smi# or sci, so this bit does not need to do so (unlike the other bits in this register ). software clears this bit by writing a 1 to it. 0 = wake event not caused by the ich8?s smbus logic. 1 = set by hardware to indicate that the wake event was caused by the ich8?s smbus logic.this bit will be set by the wake/smi# co mmand type, even if the system is already awake. the smi ha ndler should then clear this bit. notes: 1. this bit is set by the smbus slave command 01h (wake/smi#) even when the system is in the s0 state. therefore, to avoid an instant wake on subsequent transitions to sleep states , software must clear this bit after each reception of the wake/smi# comma nd or just prior to entering the sleep state. 2. if smb_wak_sts is set due to smbus sl ave receiving a message, it will be cleared by internal logic when a thrmtrip# event happens or a power button override event. however, th rmtrip# or power button override event will not clear smb_wak_sts if it is set due to smbalert# signal going active. 3. the smbalert_sts bit (d31:f3:i/o offs et 00h:bit 5) should be cleared by software before the smb_wak_sts bit is cleared. 6 tcosci_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = toc logic or thermal sensor logic did not cause sci. 1 = set by hardware when the tco logic or thermal sensor logic causes an sci. 5 usb5_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = usb uhci controller 5 does not need to cause a wake. 1 = set by hardware when usb uhci controller 5 needs to cause a wake. wake event will be generate d if the corresponding usb2_en bit is set. 4 usb2_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = usb uhci controller 2 does not need to cause a wake. 1 = set by hardware when usb uhci controller 2 needs to cause a wake. wake event will be generated if the corresponding usb 2_en bit is set. 3 usb1_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = usb uhci controller 1 does not need to cause a wake. 1 = set by hardware when usb uhci controller 1 needs to cause a wake. wake event will be generated if the corresponding usb 1_en bit is set. 2 swgpe_sts ? r/wc. the swgpe_ctrl bit (bit 1 of gpe_ctrl re g) acts as a level input to this bit. 1 hot_plug_sts ? r/wc. 0 = this bit is cleared by writ ing a 1 to this bit position. 1 = when a pci express* hot-plug event oc curs. this will cause an sci if the hot_plug_en bit is set in the gep0_en register. 0 thermal interrupt status (thrm_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = thrm# signal not driven active as defined by the thrm_pol bit 1 = set by hardware anytime the thrm# sign al is driven active as defined by the thrm_pol bit. additionally, if the thrm_en bit is set, then the setting of the thrm_sts bit will also generate a po wer management even t (sci or smi#). bit description intel ? ich8 family datasheet 405 lpc interface bridge registers (d31:f0) 9.8.3.13 gpe0_en?general purp ose event 0 enables register i/o address: pmbase + 2ch ( acpi gpe0_blk + 4 ) attribute: r/w default value: 00000000h size: 32-bit lockable: no usage: acpi power well: bits 0?7, 9, 12, 14?31 resume, bits 8, 10?11, 13 rtc this register is symmetrical to the general purpose event 0 status register. all the bits in this register should be cleared to 0 based on a power button override or processor thermal trip event. the resume well bits ar e all cleared by rsmrst#. the rtc sell bits are cleared by rtcrst#. bit description 31:16 gpin_en ? r/w. these bits enable the corresp onding gpi[n]_sts bits being set to cause a sci, and/or wake event. these bits are cleared by rsmrst#. note: mapping is as follows: bit 31 co rresponds to gpio15... and bit 16 corresponds to gpio0. 15 reserved 14 usb4_en ? r/w. 0 = disable. 1 = enable the setting of the usb4_sts bit to generate a wake event. the usb4_sts bit is set anytime usb uhci controller #4 signals a wake event. break events are handled via the usb interrupt. 13 pme_b0_en ? r/w. 0 = disable 1 = enables the setting of the pme_b0_sts bit to generate a wake event and/or an sci or smi#. pme_b0_sts can be a wake event from the s1?s4 states, or from s5 (if entered via slp_typ and slp_en) or power failure, but not power button override. this bit defaults to 0. note: it is only cleared by software or rtcr st#. it is not cleared by cf9h writes. 12 usb3_en ? r/w. 0 = disable. 1 = enable the setting of the usb3_sts bit to generate a wake event. the usb3_sts bit is set anytime usb uhci controller #3 signals a wake event. break events are handled via the usb interrupt. 11 pme_en ? r/w. 0 = disable. 1 = enables the setting of the pme_sts to generate a wake event and/or an sci. pme# can be a wake event from the s1 ? s4 state or from s5 (if entered via slp_en, but not power button override). 10 (desktop only) qrt_sci_en ? r/w . in desktop mode this bit enables the qrt_sci_sts signal to cause an sci (depending on the sci_en bit) when it is asserted 10 (mobile only) batlow_en ? r/w. 0 = disable. 1 = enables the batlow# signal to caus e an smi# or sci (depending on the sci_en bit) when it goes low. this bit does not prevent the batlow# signal from inhibiting the wake event. lpc interface bridge registers (d31:f0) 406 intel ? ich8 family datasheet 9 pci_exp_en ? r/w. 0 = disable sci generation up on pci_exp_sts bit being set. 1 = enables ich8 to cause an sci when pc i_exp_sts bit is set. this is used to allow the pci express* ports, including the link to the (g)mch, to cause an sci due to wake/pme events. 8 ri_en ? r/w. the value of this bit will be maintained through a g3 state and is not affected by a hard reset caused by a cf9h write. 0 = disable. 1 = enables the setting of the ri_sts to generate a wake event. 7 reserved 6 tcosci_en ? r/w. 0 = disable. 1 = enables the setting of the tcosci_sts to generate an sci. 5 usb5_en ? r/w. 0 = disable. 1 = enables the setting of the usb5_sts to generate a wake event. 4 usb2_en ? r/w. 0 = disable. 1 = enables the setting of the usb2_sts to generate a wake event. 3 usb1_en ? r/w. 0 = disable. 1 = enables the setting of the usb1_sts to generate a wake event. 2 swgpe_en ? r/w. this bit allows software to control the assertion of swgpe_sts bit. this bit this bit, when set to 1, enables the sw gpe function. if swgpe_ctrl is written to a 1, hardware will se t swgpe_sts (acts as a level input) if swgpe_sts, swgpe_en, and sci_en ar e all 1's, an sci will be generated if swgpe_sts = 1, swgpe_en = 1, sci_ en = 0, and gbl_smi_en = 1 then an smi# will be generated 1 hot_plug_en ? r/w. 0 = disables sci generation upon the hot_plug_sts bit being set. 1 = enables the ich8 to cause an sci when the hot_plug_sts bit is set. this is used to allow the pci express ports to cause an sci due to hot-plug events. 0 thrm_en ? r/w. 0 = disable. 1 = active assertion of the thrm# signal (a s defined by the thrm_pol bit) will set the thrm_sts bit and generate a power management event (sci or smi). bit description intel ? ich8 family datasheet 407 lpc interface bridge registers (d31:f0) 9.8.3.14 smi_en?smi control and enable register i/o address: pmbase + 30h attribute: r/w, r/w (special), wo default value: 00000000h size: 32 bit lockable: no usage: acpi or legacy power well: core note: this register is symmetrical to the smi status register. bit description 31:26 reserved 25 el_smi_en ? r/w. 0 = disable 1 = software sets this bit to enab le energy lake logic to cause smi# 24:19 reserved 18 intel_usb2_en ? r/w. 0 = disable 1 = enables intel-specific usb2 smi logic to cause smi#. 17 legacy_usb2_en ? r/w. 0 = disable 1 = enables legacy usb2 logic to cause smi#. 16:15 reserved 14 periodic_en ? r/w. 0 = disable. 1 = enables the ich8 to generate an smi# when the periodic_sts bit (pmbase + 34h, bit 14) is set in the smi_sts register (pmbase + 34h). 13 tco_en ? r/w. 0 = disables tco logic generating an smi#. note that if the nmi2smi_en bit is set, smis that are caused by re-routed nmis wi ll not be gated by th e tco_en bit. even if the tco_en bit is 0, nmis will still be routed to cause smis. 1 = enables the tco logic to generate smi#. note: this bit cannot be written on ce the tco_lock bit is set. 12 reserved 11 mcsmi_enmicrocontroller smi enable (mcsmi_en) ? r/w. 0 = disable. 1 = enables ich8 to trap accesses to the microcontroller range (62h or 66h) and generate an smi#. note that ?trapped? cycl es will be claimed by the ich8 on pci, but not forwarded to lpc. 10:8 reserved 7 bios release (bios_rls) ? wo. 0 = this bit will always return 0 on reads. writes of 0 to this bit have no effect. 1 = enables the generation of an sci interrup t for acpi software when a one is written to this bit position by bios software. note: gbl_sts being set will caus e an sci, even if the sci_en bit is not set. software must take great care not to set the bios_rls bit (which causes gbl_sts to be set) if the sci handler is not in place. lpc interface bridge registers (d31:f0) 408 intel ? ich8 family datasheet 6 software smi# timer enable (swsmi_tmr_en) ? r/w. 0 = disable. clearing the swsmi_tmr_en bit before the timer expires will reset the timer and the smi# will not be generated. 1 = starts software smi# timer. when the swsmi timer expires (t he timeout period depends upon the swsmi_rate_sel bit se tting), swsmi_tmr_sts is set and an smi# is generated. swsm i_tmr_en stays set until cleared by software. 5 apmc_en ? r/w. 0 = disable. writes to the apm_cnt register will not cause an smi#. 1 = enables writes to the apm_cn t register to cause an smi#. 4 slp_smi_en ? r/w. 0 = disables the generation of smi# on slp_ en. note that this bi t must be 0 before the software attempts to transition the sy stem into a sleep state by writing a 1 to the slp_en bit. 1 = a write of 1 to the slp_en bit (bit 13 in pm1_cnt register) will generate an smi#, and the system will not transition to the sleep state based on that write to the slp_en bit. 3 legacy_usb_en ? r/w. 0 = disable. 1 = enables legacy usb circuit to cause smi#. 2 bios_en ? r/w. 0 = disable. 1 = enables the generation of smi# when acpi software writes a 1 to the gbl_rls bit (d31:f0:pmbase + 04h:bit 2). note that if the bios_sts bit (d31:f0:pmbase + 34h:bit 2), which gets set when software writes 1 to gbl_rls bit, is already a 1 at the time that bios_en becomes 1, an smi# will be generated when bios_en gets set. 1 end of smi (eos) ? r/w (special). this bi t controls the arbitration of the smi signal to the processor. this bit must be set for the ich8 to assert smi# low to the processor after smi# has been asserted previously. 0 = once the ich8 asserts smi# low, the eos bit is automatically cleared. 1 = when this bit is set to 1, smi# signal wi ll be deasserted for 4 pci clocks before its assertion. in th e smi handler, the processor should clear all pending smis (by servicing them and then clearing their resp ective status bits), set the eos bit, and exit smm. this will allow the smi arbiter to re-assert smi upon detection of an smi event and the setting of a smi status bit. note: ich8 is able to generate 1st smi after reset even though eos bit is not set. subsequent smi require eos bit is set. 0 gbl_smi_en ? r/w. 0 = no smi# will be generated by ich8. this bit is reset by a pci reset event. 1 = enables the generation of smi# in the system upon any enabled smi event. note: when the smi_lock bit is set, this bit cannot be changed. bit description intel ? ich8 family datasheet 409 lpc interface bridge registers (d31:f0) 9.8.3.15 smi_sts?smi status register i/o address: pmbase + 34h attribute: ro, r/wc default value: 00000000h size: 32-bit lockable: no usage: acpi or legacy power well: core note: if the corresponding _en bit is set when th e _sts bit is set, the ich8 will cause an smi# (except bits 8?10 and 12, which do not need enable bits since they are logic ors of other registers that have enable bits). the ich8 uses the same gpe0_en register (i/o address: pmbase+2ch) to enable/disab le both smi and acpi sci general purpose input events. acpi os assumes that it owns the entire gpe0_en register per acpi spec. problems arise when some of the general-pu rpose inputs are enabled as smi by bios, and some of the general purpose inputs are en abled for sci. in this case acpi os turns off the enabled bit for any gpix input sign als that are not indicated as sci general- purpose events at boot, and exit from slee ping states. bios should define a dummy control method which prevents the acpi os from clearing the smi gpe0_en bits. bit description 31:27 reserved 26 spi_sts ? ro. this bit will be set if the spi logic is generating an smi#. this bit is read only because the sticky st atus and enable bits associat ed with this function are located in the spi registers. 25 el_smi_sts ? ro. this bit will be set if the energy lake logic is generating an smi#. writing a 1 to this bit clears this bit to ?0?. 24:22 reserved 21 monitor_sts ? ro. this bit will be set if the trap/smi logic has caused the smi. this will occur when the processor or a bus master accesses an assigned register (or a sequence of accesses). see section 7.1.44 through section 7.1.47 for details on the specific cause of the smi. 20 pci_exp_smi_sts ? ro. pci express* smi event occurre d. this could be due to a pci express pme event or hot-plug event. 19 reserved 18 intel_usb2_sts ? ro. this non-sticky read-only bit is a logical or of each of the smi status bits in the intel-specific us b2 smi status register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. all integrated usb2 host controll ers are represented with this bit. 17 legacy_usb2_sts ? ro. this non-sticky read-only bit is a logical or of each of the smi status bits in the usb2 legacy suppo rt register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. all integrated usb2 host controll ers are represented with this bit. lpc interface bridge registers (d31:f0) 410 intel ? ich8 family datasheet 16 smbus smi status (smbus_smi_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = this bit is set from the 64 khz clock do main used by the sm bus. software must wait at least 15.63 us after the initial as sertion of this bit before clearing it. 1 = indicates that the smi# was caused by: 1. the smbus slave receiving a message that an smi# should be caused, or 2. the smbalert# signal goes active and the smb_smi_en bit is set and the smbalert_dis bit is cleared, or 3. the smbus slave receiving a host notify message and the host_notify_intren and the sm b_smi_en bits are set, or 4. the ich8 detecting the smlink_slave _smi command while in the s0 state. 15 serirq_smi_sts ? ro. 0 = smi# was not caused by the serirq decoder. 1 = indicates that the smi# was caused by the serirq decoder. note: this is not a sticky bit 14 periodic_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set at the rate determined by the per_smi_sel bits. if the periodic_en bit (pmbase + 30h, bit 14) is also set, the ich8 generates an smi#. 13 tco_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = smi# not caused by tco logic. 1 = indicates the smi# was caused by the tco logic. note that this is not a wake event. 12 device monitor status (devmon_sts) ? ro. 0 = smi# not caused by device monitor. 1 = set if bit 0 of the devact_sts register (pmbase + 44h) is set. the bit is not sticky, so writes to this bit will have no effect. 11 microcontroller smi# status ( mcsmi_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = set if there has been an access to the power management microcontroller range (62h or 66h) and the microcontroller deco de enable #1 bit in the lpc bridge i/o enables configuration register is 1 (d31 :f0:offset 82h:bit 11). note that this implementation assumes that the microcontroller is on lpc. if this bit is set, and the mcsmi_en bit is also set, the ich8 will generate an smi#. 10 gpe0_sts ? ro. this bit is a logical or of the bi ts in the alt_gp_smi_sts register that are also set up to cause an smi# (a s indicated by the gpi_rout registers) and have the corresponding bit set in the alt_gp_smi_en register. bits that are not routed to cause an smi# will have no effect on this bit. 0 = smi# was not generated by a gpi assertion. 1 = smi# was generated by a gpi assertion. 9 gpe0_sts ? ro. this bit is a logical or of the bits 14:10, 8:2, and 0 in the gpe0_sts register (pmbase + 28h) that also have the corresponding bit set in the gpe0_en register (pmbase + 2ch). 0 = smi# was not generated by a gpe0 event. 1 = smi# was generated by a gpe0 event. 8 pm1_sts_reg ? ro. this is an ors of the bits in the acpi pm1 status register (offset pmbase+00h) that can cause an smi#. 0 = smi# was not generated by a pm1_sts event. 1 = smi# was generated by a pm1_sts event. bit description intel ? ich8 family datasheet 411 lpc interface bridge registers (d31:f0) 9.8.3.16 alt_gp_smi_en?alternate gpi smi enable register i/o address: pmbase +38h attribute: r/w default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: resume 7 reserved 6 swsmi_tmr_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = software smi# timer has not expired. 1 = set by the hardware when th e software smi# timer expires. 5 apm_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = no smi# generated by writ e access to apm control register with apmch_en bit set. 1 = smi# was generated by a write access to the apm control register with the apmc_en bit set. 4 slp_smi_sts ? r/wc. software clears this bit by writing a 1 to the bit location. 0 = no smi# caused by write of 1 to slp_ en bit when slp_smi_en bit is also set. 1 = indicates an smi# was caused by a write of 1 to slp_en bit when slp_smi_en bit is also set. 3 legacy_usb_sts ? ro. this bit is a logical or of each of the smi status bits in the usb legacy keyboard/mouse control regist ers anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. 0 = smi# was not generated by usb legacy event. 1 = smi# was generated by usb legacy event. 2 bios_sts ? r/wc. 0 = no smi# generated due to acpi software requesti ng attention. 1 = this bit gets set by hardware when a 1 is written by software to the gbl_rls bit (d31:f0:pmbase + 04h:bit 2). when bo th the bios_en bit (d31:f0:pmbase + 30h:bit 2) and the bios_sts bit are se t, an smi# will be generated. the bios_sts bit is cleared when softwa re writes a 1 to its bit position. 1:0 reserved bit description bit description 15:0 alternate gpi smi enable ? r/w. these bits are used to enable the corresponding gpio to cause an smi#. for th ese bits to have any effect, the following must be true. ? the corresponding bit in the alt_gp_smi_en register is set. ? the corresponding gpi must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. note: mapping is as follows: bit 15 correspon ds to gpio15... bit 0 corresponds to gpio0. lpc interface bridge registers (d31:f0) 412 intel ? ich8 family datasheet 9.8.3.17 alt_gp_smi_sts?alternate gpi smi status register i/o address: pmbase +3ah attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: resume 9.8.3.18 gpe_cntl? general purpose control register i/o address: pmbase +42h attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: resume bit description 15:0 alternate gpi smi status ? r/wc. these bits report th e status of the corresponding gpios. 0 = inactive. software clears th is bit by writing a 1 to it. 1 = active these bits are sticky. if the following conditions are true, then an smi# will be generated and the gpe0_sts bit set: ? the corresponding bit in the alt_gpi_ smi_en register (pmbase + 38h) is set ? the corresponding gpio must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. all bits are in the resume well. default for these bits is dependent on the state of the gpio pins. bit description 8:2 reserved 1 swgpe_ctrl ? r/w. this bit allows software to control the assert ion of swgpe_sts bit. this bit is used by hardware as the le vel input signal for the swgpe_sts bit in the gpe0_sts register. when swgpe_ ctrl is 1, swgpe_sts will be set to 1, and writes to swgpe_sts with a value of 1 to clear swgpe_sts will result in swgpe_sts being set back to 1 by hardware. when swgpe_ctrl is 0, writes to swgpe_sts with a value of 1 will clear swgpe_sts to 0. 0 thrm#_pol ? r/w. this bit controls the polarity of the thrm# pin needed to set the thrm_sts bit. 0 = low value on the thrm# signal will set the thrm_sts bit. 1 = high value on the thrm# signal will set the thrm_sts bit. intel ? ich8 family datasheet 413 lpc interface bridge registers (d31:f0) 9.8.3.19 devact_sts ? device activity status register i/o address: pmbase +44h attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: legacy only power well: core each bit indicates if an access has occurred to the corresponding device?s trap range, or for bits 6:9 if the corresponding pci interru pt is active. this register is used in conjunction with the periodic smi# timer to detect any system activity for legacy power management. the periodic smi# timer indicates if it is the right time to read the devact_sts register (pmbase + 44h). note: software clears bits that are set in this register by writing a 1 to the bit position. bit description 15:13 reserved 12 kbc_act_sts ? r/wc. kbc (60/64h). 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed . clear this bit by writing a 1 to the bit location. 11:10 reserved 9 pirqdh_act_sts ? r/wc. pirq[d or h]. 0 = the corresponding pci inte rrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 8 pirqcg_act_sts ? r/wc. pirq[c or g]. 0 = the corresponding pci inte rrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 7 pirqbf_act_sts ? r/wc. pirq[b or f]. 0 = the corresponding pci inte rrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 6 pirqae_act_sts ? r/wc. pirq[a or e]. 0 = the corresponding pci inte rrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 5:1 reserved 0 desktop only) reserved 0 (mobile only) ide_act_sts ? r/wc. ide primary drive 0 and drive 1. 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed . the enable bit is in the atc register (d31:f1:offset c0h). clear this bit by writing a 1 to the bit location. lpc interface bridge registers (d31:f0) 414 intel ? ich8 family datasheet 9.8.3.20 ss_cnt? intel speedstep ? technology control register (mobile only) i/o address: pmbase +50h attribute: r/w (special) default value 01h size: 8-bit lockable: no usage: acpi/legacy power well: core note: writes to this register will initiate an intel speedstep technology transition that involves a temporary transition to a c3-like state in which the stpclk# signal will go active. an intel speedstep technology transition always occur on writes to the ss_cnt register, even if the value written to ss_state is the same as the previous value (after this ?transition? the system would still be in the same intel speedstep technology state). if the ss_en bit is 0, then writes to this register will have no effect and reads will return 0. 9.8.3.21 c3_res? c3 residenc y register (mobile only) i/o address: pmbase +54h attribute: r/w/ro default value 00000000h size: 32-bit lockable: no usage: acpi/legacy power well: core software may only write this register during system initialization to set the state of the c3_residency_mode bit. it must not be written while the timer is in use. bit description 7:1 reserved 0 ss_state (intel speedstep ? technology state) ? r/w (special). when this bit is read, it returns the last value written to this register. by convention, this will be the current intel speedstep technology state. writes to this register causes a change to the intel speedstep technology state indicated by the value written to this bit. if the new value for ss_state is the same as the previo us value, then transition will still occur. 0 = high power state. 1 = low power state note: this is only a convention because the tr ansition is the same regardless of the value written to this bit. bit description 31:24 reserved 23:0 c3_residency ? ro. the value in this field increments at the same rate as the power management timer. if the c3_resedency_mod e bit is clear, this field automatically resets to 0 at the point when the lvl3 or lvl4 read occurs. if the c3_residency_mode bit is set, the register does not reset when the lvl3 or lvl4 read occurs. in either mode, it increments while stp_cpu# is active (i.e., the processor is in a c3 or c4 state). this field will roll over in the same way as the pm timer, however the most significant bit is not sticky. software is responsible for reading this fi eld before performing th e lvl3/4 transition. software must also check for rollover if the maximum time in c3/c4 could be exceeded. note: hardware reset is the only reset of this counter field. intel ? ich8 family datasheet 415 lpc interface bridge registers (d31:f0) 9.8.3.22 c5_res? c5 residenc y register (mobile only) i/o address: pmbase + 58h attribute: r/w/ro default value 00000000h size: 32-bit lockable: no usage: acpi/legacy power well: core software may only write this register during system initialization to set the state of the c5_residency_mode bit. it must not be written while the timer is in use. bit description 31:24 reserved 23:0 c5_residency ? ro. the value in this field increments at the same rate as the power management timer. if the c5_res edency_mode bit is clear, this field automatically resets to 0 at the point when the lvl5 or lvl6 read occurs. if the c5_residency_mode bit is set, the register does not reset when the lvl5 or lvl6 read occurs. in either mode, it increments while stp_cpu# is active (i.e., the processor is in c3/c4/c5/c6 state). this field will roll over in the same way as the pm timer, however the most significant bit is not sticky. software is responsible for reading this fi eld before performing th e lvl5/6 transition. software must also check for rollover if the maximum time in c5/c6 could be exceeded. note: hardware reset is the only reset of this counter field. lpc interface bridge registers (d31:f0) 416 intel ? ich8 family datasheet 9.9 system management tco registers (d31:f0) the tco logic is accessed via registers mapped to the pci configuration space (device 31:function 0) and the system i/o space. for tco pci configuration registers, see lpc device 31:function 0 pci configuration registers. tco register i/o map the tco i/o registers reside in a 32-byte range pointed to by a tcobase value, which is, pmbase + 60h in the pci config space. the following table shows the mapping of the registers within that 32-byte range. each register is described in the following sections. 9.9.1 tco_rld?tco timer reload and current value register i/o address: tcobase +00h attribute: r/w default value: 0000h size: 16-bit lockable: no power well: core table 116. tco i/o register address map tcobase + offset mnemonic register name default type 00h?01h tco_rld tco timer reload and current value 0000h r/w 02h tco_dat_in tco data in 00h r/w 03h tco_dat_out tco data out 00h r/w 04h?05h tco1_sts tco1 status 0000h r/wc, ro 06h?07h tco2_sts tco2 status 0000h r/w, r/wc 08h?09h tco1_cnt tco1 control 0000h r/w, r/w (special), r/ wc 0ah?0bh tco2_cnt tco2 control 0008h r/w 0ch?0dh tco_message1, tco_message2 tco message 1 and 2 00h r/w 0eh tco_wdcnt watchdog control 00h r/w 0fh ? reserved ? ? 10h sw_irq_gen software irq generation 03h r/w 11h ? reserved ? ? 12h?13h tco_tmr tco timer initial value 0004h r/w 14h?1fh ? reserved ? ? bit description 15:10 reserved 9:0 tco timer value ? r/w. reading this register will return the current count of the tco timer. writing any value to this register wi ll reload the timer to prevent the timeout. intel ? ich8 family datasheet 417 lpc interface bridge registers (d31:f0) 9.9.2 tco_dat_in?tco data in register i/o address: tcobase +02h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 9.9.3 tco_dat_out?tco data out register i/o address: tcobase +03h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 9.9.4 tco1_sts?tco1 status register i/o address: tcobase +04h attribute: r/wc, ro default value: 0000h size: 16-bit lockable: no power well: core (except bit 7, in rtc) bit description 7:0 tco data in value ? r/w. this data register field is used for passing commands from the os to the smi handler. writes to this register will cause an smi and set the sw_tco_smi bit in the tco1_sts register (d31:f0:04h). bit description 7:0 tco data out value ? r/w. this data register fi eld is used for passing commands from the smi handler to the os. writes to this register will set the tco_int_sts bit in the tco_sts register. it will also cause an interrupt, as selected by the tco_int_sel bits. bit description 15:13 reserved 12 dmiserr_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = ich8 received a dmi special cycle message via dmi indicating that it wants to cause an serr#. the software must read the (g)mch to determine the reason for the serr#. 11 reserved 10 dmismi_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = ich8 received a dmi special cycle message via dmi indicating that it wants to cause an smi. the software must read th e (g)mch to determine the reason for the smi. 9 dmisci_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = ich8 received a dmi special cycle message via dmi indicating that it wants to cause an sci. the software must read th e (g)mch to determine the reason for the sci. lpc interface bridge registers (d31:f0) 418 intel ? ich8 family datasheet 8 bioswr_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich8 sets this bit and gene rates and smi# to indicate an invalid attempt to write to the bios. this occurs when either: a) the bioswp bit is changed from 0 to 1 and the bld bit is also set, or b) any write is attempted to the bios and the bioswp bit is also set. note: on write cycles attempted to the 4 mb lower alias to the bios space, the bioswr_sts will not be set. 7 newcentury_sts ? r/wc. this bit is in the rtc well. 0 = cleared by writing a 1 to the bit position or by rtcrst# going active. 1 = this bit is set when the year byte (rtc i/o space, index offset 09h) rolls over from 99 to 00. setting this bit will cause an smi# (but not a wake event). note: the newcentury_sts bit is not valid when the rtc battery is first installed (or when rtc power has not been maintain ed). software can determine if rtc power has not been maintained by checking the rtc_pwr_sts bit (d31:f0:a4h, bit 2), or by other means (such as a checksum on rtc ram). if rtc power is determined to have not been maintained, bios should set the time to a valid value and then clear the newcentury_sts bit. the newcentury_sts bit may take up to 3 rtc clocks for the bit to be cleared after a 1 is written to the bit to clear it. after writing a 1 to this bit, software should not exit the smi handler until verifying that the bit has ac tually been cleared. this will ensure that the smi is not re-entered. 6:4 reserved 3 timeout ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by ich8 to indicate that the sm i was caused by the tco timer reaching 0. 2 tco_int_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = smi handler caused the interrupt by writing to the tco_dat_out register (tcobase + 03h). 1 sw_tco_smi ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = software caused an smi# by writing to the tco_dat_in register (tcobase + 02h). 0 nmi2smi_sts ? ro. 0 = cleared by clearing the associated nmi status bit. 1 = set by the ich8 when an smi# occu rs because an event occurred that would otherwise have caused an nmi (because nmi2smi_en is set). bit description intel ? ich8 family datasheet 419 lpc interface bridge registers (d31:f0) 9.9.5 tco2_sts?tco2 status register i/o address: tcobase +06h attribute: r/w, r/wc default value: 0000h size: 16-bit lockable: no power well: resume (except bit 0, in rtc) bit description 15:6 reserved 5 me_wake_sts ? r/wc. this bit is set when the me generates a non-maskable wake event, and is not affected by any other enable bit. when this bit is set, the host power management logic wakes to s0. this bit is only set by hardware and can on ly be reset by writin g a one to this bit position. this bit is not affected by hard re sets caused by a cf9 wr ite, but is reset by rsmrst. 4 smlink slave smi status (smlink_slv_smi_sts) ? r/wc. allow the software to go directly into pre-determined sleep state. this avoids race conditions. software clears this bit by writing a 1 to it. 0 = the bit is reset by rsmrst#, but not du e to the pci reset associated with exit from s3?s5 states. 1 = ich8 sets this bit to 1 when it receiv es the smi message on the smlink's slave interface. 3 reserved 2 boot_sts ? r/wc. 0 = cleared by ich8 based on rsmrst# or by software writing a 1 to this bit. note that software should first clear the seco nd_to_sts bit before writing a 1 to clear the boot_sts bit. 1 = set to 1 when the second_to_sts bit go es from 0 to 1 and the processor has not fetched the firs t instruction. if rebooting due to a second tco timer timeout, and if the boot_sts bit is set, the ich8 will reboot using the ?safe? multiplier (1111). this allows the system to recover from a processor frequency multiplier that is too high, and allows the bios to check the boot_sts bit at boot. if the bit is set and the frequency multiplier is 1111, then the bios knows that the processor has been programmed to an invalid multiplier. 1 second_to_sts ? r/wc. 0 = software clears this bit by wr iting a 1 to it, or by a rsmrst#. 1 = ich8 sets this bit to 1 to indicate that the timeout bit had be en (or is currently) set and a second timeout occurred before th e tco_rld register was written. if this bit is set and the no_reboot config bit is 0, then the ich8 will reboot the system after the second timeout. the reboot is done by asserting pltrst#. lpc interface bridge registers (d31:f0) 420 intel ? ich8 family datasheet 9.9.6 tco1_cnt?tco1 control register i/o address: tcobase +08h attribute: r/w, r/w (special), r/ wc default value: 0000h size: 16-bit lockable: no power well: core 0 intruder detect (intrd_det) ? r/wc. 0 = software clears this bit by writin g a 1 to it, or by rtcrst# assertion. 1 = set by ich8 to indicate that an intrusio n was detected. this bit is set even if the system is in g3 state. note: this bit has a recovery time. after writing a 1 to this bit position (to clear it), the bit may be read back as a 1 for up 65 mi croseconds before it is read as a 0. software must be aware of this recove ry time when reading this bit after clearing it. note: if the intruder# signal is active when the software attempts to clear the intrd_det bit, the bit will remain as a 1, and the smi# will be generated again immediately. the smi handler can clear the intrd_sel bits (tcobase + 0ah, bits 2:1), to avoid further smis. howe ver, if the intruder# signals goes inactive and then active again, there will not be further smi?s (because the intrd_sel bits would select that no sm i# be generated). note: if the intruder# signal goes inactive some point after the intrd_det bit is written as a 1, then the intrd_det signal will go to a 0 when intruder# input signal goes inactive. note that this is sl ightly different than a classic sticky bit, since most sticky bits woul d remain active indefinite ly when the signal goes active and would immediat ely go inactive when a 1 is written to the bit bit description bit description 15:13 reserved 12 tco_lock ? r/w (special). when set to 1, this bit prevents writes from changing the tco_en bit (in offset 30h of power management i/o space). once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. a core-well reset is required to change this bit from 1 to 0. this bit defaults to 0. 11 tco timer halt (tco_tmr_hlt) ? r/w. 0 = the tco timer is enabled to count. 1 = the tco timer will halt. it will not count, and thus cannot reach a value that will cause an smi# or set the second_to_sts bit. when set, this bit will prevent rebooting and prevent alert on lan even t messages from being transmitted on the smlink (but not alert on lan* heartbeat messages). 10 reserved 9 nmi2smi_en ? r/w. 0 = normal nmi functionality. 1 = forces all nmis to instead cause smis. th e functionality of this bit is dependent upon the settings of the nmi_en bit and the gbl_smi_en bit as detailed in the following table: nmi_en gbl_smi_en description 0b 0b no smi# at all be cause gbl_smi_en = 0 0b 1b smi# will be caused due to nmi events 1b 0b no smi# at all be cause gbl_smi_en = 0 1b 1b no smi# due to nmi because nmi_en = 1 intel ? ich8 family datasheet 421 lpc interface bridge registers (d31:f0) 9.9.7 tco2_cnt?tco2 control register i/o address: tcobase +0ah attribute: r/w default value: 0008h size: 16-bit lockable: no power well: resume 9.9.8 tco_message1 and tco_message2 registers i/o address: tcobase +0ch (message 1)attribute: r/w tcobase +0dh (message 2) default value: 00h size: 8-bit lockable: no power well: resume 8 nmi_now ? r/wc. 0 = software clears this bit by writing a 1 to it. the nmi handler is expected to clear this bit. another nmi will not be generated until the bit is cleared. 1 = writing a 1 to this bit causes an nmi. this allows the bios or smi handler to force an entry to the nmi handler. 7:0 reserved bit description bit description 15:6 reserved 5:4 os_policy ? r/w. os-based software writes to these bits to select the policy that the bios will use after the pl atform resets due the wdt. the following convention is recommended for the bios and os: 00 = boot normally 01 = shut down 10 = don?t load os. hold in pre-boot state and use lan to determine next step 11 = reserved note: these are just scratchpad bits. they should not be reset when the tco logic resets the platform due to watchdog timer. 3 gpio11_alert_disable ? r/w. at reset (via rsmrst# asserted) this bit is set and gpio[11] alerts are disabled. 0 = enable. 1 = disable gpio11/smbalert# as an alert source for the heartbeats and the smbus slave. 2:1 intrd_sel ? r/w. this field selects the action to take if the intruder# signal goes active. 00 = no interrupt or smi# 01 = interrupt (as sele cted by tco_int_sel). 10 = smi 11 = reserved 0 reserved bit description 7:0 tco_message[ n ] ? r/w. bios can write into these registers to indicate its boot progress. the external microc ontroller can read these registers to monitor the boot progress. lpc interface bridge registers (d31:f0) 422 intel ? ich8 family datasheet 9.9.9 tco_wdcnt?tco watchdog control register offset address: tcobase + 0eh attribute: r/w default value: 00h size: 8 bits power well: resume 9.9.10 sw_irq_gen?software irq generation register offset address: tcobase + 10h attribute: r/w default value: 03h size: 8 bits power well: core 9.9.11 tco_tmr?tco timer initial value register i/o address: tcobase +12h attribute: r/w default value: 0004h size: 16-bit lockable: no power well: core bit description 7:0 the bios or system management software can write into this register to indicate more details on the boot progress. the register will reset to 00h based on a rsmrst# (but not pltrst#). the external microcontroller can read this register to monitor boot progress. bit description 7:2 reserved 1 irq12_cause ? r/w. the state of this bit is logi cally anded with the irq12 signal as received by the ich8?s serirq logic. this bit must be a 1 (default) if the ich8 is expected to receive irq12 asse rtions from a serirq device. 0 irq1_cause ? r/w. the state of this bit is logically anded with the irq1 signal as received by the ich8?s serirq logic. this bit must be a 1 (default) if the ich8 is expected to receive irq1 asse rtions from a serirq device. bit description 15:10 reserved 9:0 tco timer initial value ? r/w. value that is loaded into the timer each time the tco_rld register is written. values of 0000h or 0001h will be ignored and should not be attempted. the timer is clocked at a pproximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to 613.8 seconds. note: the timer has an error of 1 tick (0.6s). the tco timer will only count down in the s0 state. intel ? ich8 family datasheet 423 lpc interface bridge registers (d31:f0) 9.10 general purpose i/o registers (d31:f0) the control for the general purpose i/o sign als is handled through a separate 64-byte i/o space. the base offset for this spac e is selected by the gpiobase register. table 117. registers to co ntrol gpio address map gpiobase + offset mnemonic register name default access 00h?03h gpio_use_sel gpio use select 197f75ffh (desktop) / 197e55ffh (mobile) r/w 04h?07h gp_io_sel gpio input/output select e0ea7fffh r/w 08h?0bh ? reserved ? ? 0ch?0fh gp_lvl gpio level for input or output 02fe8000h r/w 10h?13h gpio_use_sel override (low) gpio use select override low 00000000h r/w 14h?17h ? reserved ? ? 18h?1bh gpo_blink gpio blink enable 00040000h r/w 1ch?1fh gp_ser_blink[31:0] gp serial blink [31:0] 00000000h r/w 20?23h gp_sb_cmdsts[31:0] gp serial blink command status [31:0] 00000800h r/w 24?27h gp_sb_data[31:0] gp serial blink data [31:0] 00000000h r/w 28?2bh ? reserved ? ? 2c?2fh gpi_inv gpio signal invert 00000000h r/w 30h?33h gpio_use_sel2 gpio use select 2 [63:32] 000100ffh (desktop) / 000100feh (mobile) r/w 34h?37h gp_io_sel2 gpio input/output select 2 [63:32] 00550ff0h r/w 38h?3bh gp_lvl2 gpio level for input or output 2 [63:32] 00aa0003h r/w 3ch?3fh gpio_use_sel override (high) gpio use select override high 00000000h r/w lpc interface bridge registers (d31:f0) 424 intel ? ich8 family datasheet 9.10.1 gpio_use_sel?gpio use select register offset address: gpiobase + 00h attribute: r/w default value: 197f75ffh (desktop) size: 32-bit 197e55ffh (mobile) lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 9.10.2 gp_io_sel?gpio input/output select register offset address: gpiobase +04h attribute: r/w default value: e0ea 7fffh size: 32-bit lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:0 gpio_use_sel[31:0] ? r/w. each bit in this regi ster enables the corresponding gpio (if it exists) to be used as a gp io, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. notes: 1. the following bits are always 1 because they are unmultiplexed: 8, 18, 20. the following bits are also unmultiplexed in desktop configuration: 12, 13, 16 2. if gpio[n] does not exist, then the bit in this register will always read as 0 and writes will have no effect. 3. when rsmrst# is asserted, all multip lexed signals in the resume and core wells are configured as their default function. when just pltrst# is asserted, the gpio in the core well are conf igured as their default function. 4. when configured to gpio mode, the mult iplexing logic will present the inactive state to native logic that uses the pin as an input. 5. all gpios are reset to the default state by cf9h reset except gpio24 6. if the gpio use is configured by a so ft strap, the corresp onding bit in this register is ignored. this applies to the following ich8m bits: [13:12]. bit description 31:0 gp_io_sel[31:0] ? r/w. when configured in na tive mode (gpio_use_sel[n] is 0), writes to these bits have no effect. the value reported in this register is undefined when programmed as native mode. 0 = output. the corresponding gpio signal is an output. 1 = input. the corresponding gpio signal is an input. intel ? ich8 family datasheet 425 lpc interface bridge registers (d31:f0) 9.10.3 gp_lvl?gpio level for input or output register offset address: gpiobase +0ch attribute: r/w default value: 02fe8000h size: 32-bit lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 9.10.4 gpio_use_sel override re gister (low)?gpio use select override register low offset address: gpiobase +10h attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:0 gp_lvl[31:0] ? r/w: if gpio[n] is programmed to be an outp ut (via the corresponding bit in the gp_io_sel register), then the corresponding gp_lvl[n ] bit can be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. if gpio[n] is programmed as an input, then the corresponding gp_lvl bit reflects the state of the input signal (1 = high, 0 = low.) and writes will have no effect. when configured in native mode (gpio_use_ sel[n] is 0), writes to these bits have no effect. the value reported in this register is unde fined when programmed as native mode. bit description 31:0 gpio_use_sel override [31:0] ? r/w. each bit in th is register enables the corresponding gpio (if it exists) to be us ed as a gpio, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. once a bit is set to 1b, it can only be clea red a reset. bits 31:2 4 and 15:8 are cleared by rsmrst# and cf9h events. bits 23:16 and 7:0 are cleared by pltrst# events. if the corresponding gpio is not multip lexed with native functionality or not implemented at all, th is bit has no effect. this register corresponds to gpio[31:0]. lpc interface bridge registers (d31:f0) 426 intel ? ich8 family datasheet 9.10.5 gpo_blink?gpo blink enable register offset address: gpiobase +18h attribute: r/w default value: 00040000h size: 32-bit lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 note: gpio18 will blink by default immediately after reset. this signal could be connected to an led to indicate a failed boot (by programmin g bios to clear gp_blink18 after successful post). 9.10.6 gp_ser_blink[31: 0]?gp serial blink offset address: gpiobase +1ch attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:0 gp_blink[31:0] ? r/w. the setting of this bit has no effect if the corresponding gpio signal is programmed as an input. 0 = the corresponding gpio will function normally. 1 = if the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times have approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. the value of the corresponding gp_lvl bit remains unchange d during the blink process, and does not effect the blink in any way. the gp_lvl bit is not altered when programmed to blink. it will remain at its previous value. these bits correspond to gpio in the resume well. thes e bits revert to the default value based on rsmrst# or a write to the cf9h register (but not just on pltrst#). bit description 31:0 gp_ser_blink[31:0] : the setting of this bit has no effect if th e corresponding gpio is programmed as an input or if the corresponding gpio has the gpo_blink bit set. when set to a 0, the corresponding gpio will function normally. when using serial blink, this bit should be set to a 1 while the corresponding gp_io_sel bit is set to 1. setting the gp_io_sel bit to 0 after the gp_ser_blink bit ensures ich8 will not drive a 1 on the pin as an output. when this corresponding bit is set to a 1 and the pin is configured to output mode, the serial blink capability is enabled. the ich8 will serialize messages through an open-drain buffer configuration. the value of the corresponding gp_lvl bi t remains unchanged and does not impact the serial blink capability in any way. writes to this register have no effect wh en the corresponding pin is configured in native mode and the read va lue returned is undefined. intel ? ich8 family datasheet 427 lpc interface bridge registers (d31:f0) 9.10.7 gp_sb_cmdsts[31:0]?gp serial blink command status offset address: gpiobase +20h attribute: r/w default value: 00080000h size: 32-bit lockable: no power well: core 9.10.8 gp_sb_data[31:0]?gp serial blink data offset address: gpiobase +24h attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: core bit description 31:24 reserved 23:22 data length select (dls) : this read/write field dete rmines the number of bytes to serialize on gpio. 00 = serialize bits 7:0 of gp_sb_data (1 byte) 01 = serialize bits 15:0 of gp_sb_data (2 bytes) 10 = undefined - software must not write this value 11 = serialize bits 31:0 of gp_sb_data (4 bytes) software should not modify the value in this register unless the busy bit is clear. writes to this register have no effect when the corresponding pin is configured in native mode and the read va lue returned is undefined. 21:16 data rate select (drs): this read/write field selects the nu mber of 128ns time intervals to count between manchester data transitions. the default of 8h results in a 1024ns minimum time between transition s. a value of 0h in this register produces undefined behavior. software should not modify the value in th is register unless th e busy bit is clear. 15:9 reserved 8 busy : this read-only status bit is the hardware indication that a serialization is in progress. hardware sets this bit to 1 ba sed on the go bit being set. hardware clears this bit when the go bi t is cleared by the hardware. 7:1 reserved 0 go : this bit is set to 1 by software to start the serializatio n process. hardware clears the bit after the serialized data is se nt. writes of 0 to th is register have no effect. software should not write this bit to 1 unless the busy status bit is cleared. bit description 31:0 gp_sb_data[31:0] : this read-write register cont ains the data se rialized out. the number of bits shifted out are se lected through the dls field in the gp_sb_cmdsts register. this register should not be mo dified by software when the busy bit is set. lpc interface bridge registers (d31:f0) 428 intel ? ich8 family datasheet 9.10.9 gpi_inv?gpio sign al invert register offset address: gpiobase +2ch attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: cpu i/o for 17, core for 16, 7:0 9.10.10 gpio_use_sel2?gpio us e select 2 register[63:32] offset address: gpiobase +30h attribute: r/w default value: 000100ffh (desktop) size: 32-bit 000100feh (mobile) lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:0 gp_inv[n] ? r/w. input inversion: this bit only has effect if the corresponding gpio is used as an input and used by the gpe logic, where the polarity matters. when set to ?1?, then the gpi is inverted as it is sent to the gpe logic that is using it. this bit has no effect on the value that is reported in the gp_lvl register. these bits are used to allow both active-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, the input signal must be active for at least two pci clocks to ensure detection by the ich8. in the s3, s4 or s5 states the input signal must be active for at least 2 rtc clocks to ensure detection. the setting of these bits has no effect if the corresponding gpio is programm ed as an output. these bits correspond to gpi that are in the resume well, and will be reset to their default values by rsmrst# or by a write to the cf9h register. 0 = the corresponding gpi_sts bit is set when the ich8 detects the state of the input pin to be high. 1 = the corresponding gpi_sts bit is set when the ich8 detects the state of the input pin to be low. bit description 31:0 gpio_use_sel2[31:0] ? r/w. each bit in this register enables the corresponding gpio (if it exists) to be used as a gpio, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. notes: 1. the following bit is always 1 because it is always unmultiplexed: 0. 2. if gpio[n] does not exist, then the (n-32) bit in this register will always read as 0 and writes will have no effect. the following bits are always 0: [15:12], [31:24]. 3. when rsmrst# is asserted, all multip lexed signals in the resume and core wells are configured as their default fu nction. when just pl trst# is asserted, the gpios in the core well are conf igured as their default function. 4. when configured to gpio mode, the multiplexing logic will present the inactive state to native logic that uses the pin as an input. 5. all gpios are reset to the default state by cf9h reset (except gpio24) intel ? ich8 family datasheet 429 lpc interface bridge registers (d31:f0) 9.10.11 gp_io_sel2?gpio input/output select 2 register[63:32] offset address: gpiobase +34h attribute: r/w default value: 00550ff0h size: 32-bit lockable: no power well: cpu i/o for 17, core for 16, 7:0 9.10.12 gp_lvl2?gpio level for input or output 2 register[63:32] offset address: gpiobase +38h attribute: r/w default value: 00aa0003h size: 32-bit lockable: no power well: cpu i/o for 17, core for 16, 7:0 bit description 31:24, 15:12 always 0. no corresponding gpio. 23:16, 11:0 gp_io_sel2[49:48, 39:32] ? r/w. 0 = gpio signal is programmed as an output. 1 = corresponding gpio signal (if enab led in the gpio_use_sel2 register) is programmed as an input. this register corresponds to gpio[55:48 , 43:32]. bit 0 corresponds to gpio32. bit description 31:24, 15:12 reserved. read-only 0 23:16, 11:0 gp_lvl[49:48, 39:32] ? r/w. if gpio[n] is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the correspondi ng gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. if gpio[n] is programmed as an input, then the corresponding gp_l vl bit reflects the state of the input signal (1 = high, 0 = low.) and writes will have no effect. when configured in native mode (gpio_use_sel[n] is 0), writes to these bits have no effect. the value reported in this register is undefined when programmed as native mode. this register corresponds to gpio[55:48, 43:32]. bit 0 corresponds to gpio32. lpc interface bridge registers (d31:f0) 430 intel ? ich8 family datasheet 9.10.13 gpio_use_sel override register (high)?gpio use select override register high offset address: gpiobase +3ch attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:0 gpio_use_sel override [63:32] ? r/w. each bit in this field corresponds to one of the host gpio indexed signals. a 1b in this field forces the corresponding host signal used as native function mode, rega rdless of the host gpio_use_sel register bit. a 0b in this field leaves the determin ation of the pin usage to the gpio_use_sel register. once a bit is set to 1b, it can only be clea red a reset. bits 31:24 and 15:8 are cleared by rsmrst# and cf9h events . bits 23:16 and 7:0 are cleared by pltrst# events. if the corresponding gpio is not multiplexed with native functionality or not implemented at all, th is bit has no effect. this register corresponds to gpio[55:48, 43:32]. bit 0 corresponds to gpio32. intel ? ich8 family datasheet 431 pci-to-pci bridge registers (d30:f0) 10 pci-to-pci bridge registers (d30:f0) the ich8 pci bridge resides in pci device 30, function 0 on bus #0. this implements the buffering and control logic between pci and the backbone. the arbitration for the pci bus is handled by this pci device. 10.1 pci configuration registers (d30:f0) note: address locations that are not shown should be treated as reserved (see section 6.2 for details). . table 118. pci bridge regi ster address map (pci-pci ?d30:f0) (sheet 1 of 2) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h psts pci status 0010h r/wc, ro 08h rid revision identification see register description ro 09h?0bh cc class code 00060401h ro 0dh pmlt primary master latency timer 00h ro 0eh headtyp header type 81h ro 18h?1ah bnum bus number 000000h r/w, ro 1bh smlt secondary master latency timer 00h r/w, ro 1ch?1dh iobase_limit i/o base and limit 0000h r/w, ro 1eh?1fh secsts secondary status 0280h r/wc, ro 20h?23h membase_limit memory base and limit 00000000h r/w, ro 24h?27h pref_mem_base _limit prefetchable memory base and limit 00010001h r/w, ro 28h?2bh pmbu32 prefetchable memory upper 32 bits 00000000h r/w 2ch?2fh pmlu32 prefetchable memory limit upper 32 bits 00000000h r/w 34h capp capability list pointer 50h ro 3ch-3dh intr interrupt information 0000h r/w, ro 3eh?3fh bctrl bridge control 0000h r/wc, ro 40h?41h spdh secondary pci device hiding 00h r/w, ro 44h?47h dtc delayed transaction control 00000000h r/w, ro 48h?4bh bps bridge proprietary status 00000000h r/wc, ro pci-to-pci bridge registers (d30:f0) 432 intel ? ich8 family datasheet 10.1.1 vid? vendor identificati on register (pci-pci?d30:f0) offset address: 00h?01h attribute: ro default value: 8086h size: 16 bits 10.1.2 did? device identificati on register (pci-pci?d30:f0) offset address: 02h?03h attribute: ro default value: see bit description size: 16 bits 10.1.3 pcicmd?pci command (pci-pci?d30:f0) offset address: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits 4ch?4fh bpc bridge policy configuration 00001200h r/w ro 50?51h svcap subsystem vendor capability pointer 000dh ro 54h?57h svid subsystem vendor ids 00000000 r/wo table 118. pci bridge regi ster address map (pci-pci?d30:f0) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit valu e assigned to intel. intel vid = 8086h. bit description 15:0 device id ? ro.this is a 16-bit value assigned to the pci bridge. refer to the intel ? ich8 family specification update for the value of the device id register. bit description 15:11 reserved 10 interrupt disable (id) ? ro. hardwired to 0. the pci bridge has no interrupts to disable. 9 fast back to back enable (fbe) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a . 8 serr# enable (serr_en) ? r/w. 0 = disable. 1 = enable the ich8 to generate an nmi (or smi# if nmi routed to smi#) when the d30:f0 sse bit (offset 06h, bit 14) is set. 7 wait cycle control (wcc) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a . 6 parity error response (per) ? r/w. 0 = the ich8 ignores parity errors on the pci bridge. 1 = the ich8 will set the sse bit (d30:f0, o ffset 06h, bit 14) when parity errors are detected on the pci bridge. 5 vga palette snoop (vps) ? ro . hardwired to 0, per the pci express* base specification, revision 1.0a . intel ? ich8 family datasheet 433 pci-to-pci bridge registers (d30:f0) 10.1.4 psts?pci status register (pci-pci?d30:f0) offset address: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 4 memory write and invalidate enable (mwe) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a 3 special cycle enable (sce) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a and the pci- to-pci bridge specification. 2 bus master enable (bme) ? r/w. 0 = disable 1 = enable. allows the pci-to-pci br idge to accept cycles from pci. 1 memory space enable (mse) ? r/w. controls the respon se as a target for memory cycles targeting pci. 0 = disable 1 = enable 0 i/o space enable (iose) ? r/w. controls the response as a target for i/o cycles targeting pci. 0 = disable 1 = enable bit description bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = indicates that the ich8 de tected a parity error on the internal backbone. this bit gets set even if the parity error resp onse bit (d30:f0:04 bit 6) is not set. pci-to-pci bridge registers (d30:f0) 434 intel ? ich8 family datasheet 14 signaled system error (sse) ? r/wc. several internal an d external sources of the bridge can cause serr#. the first class of errors is parity e rrors related to the backbone. the pci bridge captures generic da ta parity errors (errors it finds on the backbone) as well as errors returned on backbone cycles wher e the bridge was the master. if either of these two conditions is met, and the primary side of the bridge is enabled for parity error response, serr# will be captured as shown below. as with the backbone, the pci bus captures the same sets of e rrors. the pci bridge captures generic data parity erro rs (errors it finds on pci) as well as errors returned on pci cycles where the bridge was the master. if either of these two conditions is met, and the secondary side of the bridge is enab led for parity error response, serr# will be captured as shown below. the final class of errors is system bus errors. there are three status bits associated with system bus errors, each with a corresponding enable. the diagram capturing this is shown below. after checking for the three above classes of errors, an serr# is generated, and psts.sse logs the generation of serr#, if cmd.see (d30:f0:04, bit 8) is set, as shown below. 13 received master abort (rma) ? r/wc. 0 = no master abort received. 1 = set when the bridge receives a ma ster abort status from the backbone. 12 received target abort (rta) ? r/wc. 0 = no target abort received. 1 = set when the bridge receives a ta rget abort status from the backbone. bit description intel ? ich8 family datasheet 435 pci-to-pci bridge registers (d30:f0) 10.1.5 rid?revision identificati on register (pci-pci?d30:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 10.1.6 cc?class code register (pci-pci?d30:f0) offset address: 09h-0bh attribute: ro default value: 060401h size: 24 bits 11 signaled target abort (sta) ? r/wc. 0 = no signaled target abort 1 = set when the bridge generates a completion packet with target abort status on the backbone. 10:9 reserved. 8 data parity error detected (dpd) ? r/wc. 0 = data parity error not detected. 1 = set when the bridge receives a comp letion packet from the backbone from a previous request, an d detects a parity error, and cmd.pere is set (d30:f0:04, bit 6). 7:5 reserved. 4 capabilities list (clist) ? ro. hardwired to 1. capability list exist on the pci bridge. 3 interrupt status (is) ? ro. hardwired to 0. the pci bridge does not generate interrupts. 2:0 reserved bit description bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hu b 8 (ich8) family specification update for the value of the revision id register bit description 23:16 base class code (bcc) ? ro. hardwired to 06h. indicates this is a bridge device. 15:8 sub class code (scc) ? ro. hardwired to 04h. indicates th is device is a pci-to-pci bridge. 7:0 programming interface (pi) ? ro. hardwired to 01h. indi cates the bridge is subtractive decode pci-to-pci bridge registers (d30:f0) 436 intel ? ich8 family datasheet 10.1.7 pmlt?primary master latency timer register (pci-pci?d30:f0) offset address: 0dh attribute: ro default value: 00h size: 8 bits 10.1.8 headtyp?header type register (pci-pci?d30:f0) offset address: 0eh attribute: ro default value: 01h size: 8 bits 10.1.9 bnum?bus number re gister (pci-pci?d30:f0) offset address: 18h?1ah attribute: r/w, ro default value: 000000h size: 24 bits bit description 7:3 master latency timer count (mltc) ? ro. reserved per the pci express* base specification, revision 1.0a . 2:0 reserved bit description 7 multi-function device (mfd) ? ro. a 0 indicates a single function device 6:0 header type (htype) ? ro. this 7-bit field identifi es the header layout of the configuration space, which is a pci-to-pci bridge in this case. bit description 23:16 subordinate bus number (sbbn) ? r/w. this field indicates the highest pci bus number below the bridge. 15:8 secondary bus number (scbn) ? r/w. this field indicates the bus number of pci. 7:0 primary bus number (pbn) ? r/w. this field is defaul t to 00h. in a multiple-ich8 system, programmable pbn allows an ich8 to be located on any bus. system configuration software is responsible for in itializing these registers to appropriate values. pbn is not used by hardwa re in determinin g its bus number. intel ? ich8 family datasheet 437 pci-to-pci bridge registers (d30:f0) 10.1.10 smlt?secondary master latency timer register (pci-pci?d30:f0) offset address: 1bh attribute: r/w, ro default value: 00h size: 8 bits this timer controls the amount of time the ic h8 pci-to-pci bridge will burst data on its secondary interface. the counter starts co unting down from the assertion of frame#. if the grant is removed, then the expirati on of this counter will result in the de- assertion of frame#. if the grant has not been removed, then the ich8 pci-to-pci bridge may continue ownership of the bus. 10.1.11 iobase_limit?i/o ba se and limit register (pci-pci?d30:f0) offset address: 1ch-1dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 7:3 master latency timer count (mltc) ? r/w. this 5-bit field indi cates the number of pci clocks, in 8-clock increments, that the ich8 remains as master of the bus. 2:0 reserved bit description 15:12 i/o limit address limit bits [15:12] ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11: 0 are assumed to be padded to fffh. 11:8 ii/o limit address capability (iolc) ? ro. in dicates that the bridge does not support 32-bit i/o addressing. 7:4 i/o base address (ioba) ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bi ts 11:0 are assumed to be padded to 000h. 3:0 i/o base address capability (iobc) ? ro. indicates that the bridge does not support 32-bit i/o addressing. pci-to-pci bridge registers (d30:f0) 438 intel ? ich8 family datasheet 10.1.12 secsts?secondary status register (pci-pci?d30:f0) offset address: 1eh ? 1fh attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = intel ? ich8 pci bridge detected an address or data parity error on the pci bus 14 received system error ( rse) ? r/wc. 0 = serr# assertion not received 1 = serr# assertion is received on pci. 13 received master abort (rma) ? r/wc. 0 = no master abort. 1 = this bit is set whenever th e bridge is acting as an in itiator on the pci bus and the cycle is master-aborted. for (g)mch/ich8 interface packets that have completion required, this must also ca use a target abort to be re turned and sets psts.sta. (d30:f0:06 bit 11) 12 received target abort (rta) ? r/wc. 0 = no target abort. 1 = this bit is set whenever the bridge is acting as an initiator on pci and a cycle is target-aborted on pci. for (g)mch/ich8 interface packets that have completion required, this event must also cause a target abort to be returned, and sets psts.sta. (d30:f0:06 bit 11). 11 signaled target abort (sta) ? r/wc. 0 = no target abort. 1 = this bit is set when the br idge is acting as a target on the pci bus and signals a target abort. 10:9 devsel# timing (devt) ? ro. 01h = medium decode timing. 8 data parity error detected (dpd) ? r/wc. 0 = conditions de scribed below not met. 1 = the ich8 sets this bit when all of the following three conditions are met: ? the bridge is the initiator on pci. ? perr# is detected asserted or a parity error is detected internally ? bctrl.pere (d30:f0:3e bit 0) is set. 7 fast back to back capable (fbc) ? ro. hardwi red to 1 to indicate that the pci to pci target logic is capable of rece iving fast back-to-back cycles. 6 reserved 5 66 mhz capable (66mhz_cap) ? ro. hardwire d to 0. this bridge is 33 mhz capable only. 4:0 reserved intel ? ich8 family datasheet 439 pci-to-pci bridge registers (d30:f0) 10.1.13 membase_limit?memory base and limit register (pci-pci?d30:f0) offset address: 20h?23h attribute: r/w, ro default value: 00000000h size: 32 bits this register defines the base and limit, aligned to a 1-mb boundary, of the non- prefetchable memory area of the bridge. a ccesses that are within the ranges specified in this register will be sent to pci if cmd. mse is set. accesses from pci that are outside the ranges specified will be accepted by the bridge if cmd.bme is set. 10.1.14 pref_mem_base_limit?prefetchable memory base and limit register (pci-pci?d30:f0) offset address: 24h?27h attribute: r/w, ro default value: 00010001h size: 32-bit defines the base and limit, aligned to a 1- mb boundary, of the prefetchable memory area of the bridge. accesses that are within th e ranges specified in this register will be sent to pci if cmd.mse is set. accesses from pci that are outside the ranges specified will be accepted by the bridge if cmd.bme is set. bit description 31-20 memory limit (ml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the upper 1-mb alig ned value (exclusive) of the range. the incoming address must be less than this value. 19-16 reserved 15:4 memory base (mb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1-mb alig ned value (inclusive) of the range. the incoming address must be greate r than or equal to this value. 3:0 reserved bit description 31-20 prefetchable memory limit (pml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the u pper 1-mb aligned value (exclusive) of the range. the incoming address mu st be less than this value. 19-16 64-bit indicator (i64l) ? ro. indicates support for 64-bit addressing. 15:4 prefetchable memory base (pmb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lo wer 1-mb aligned value (inclusive) of the range. the incoming address must be greater than or equal to this value. 3:0 64-bit indicator (i64b) ? ro. indicates support fo r 64-bit addressing. pci-to-pci bridge registers (d30:f0) 440 intel ? ich8 family datasheet 10.1.15 pmbu32?prefetchable memory base upper 32 bits register (pci-pci?d30:f0) offset address: 28h?2bh attribute: r/w default value: 00000000h size: 32 bits 10.1.16 pmlu32?prefetchable memory limit upper 32 bits register (pci-pci?d30:f0) offset address: 2c?2fh attribute: r/w default value: 00000000h size: 32 bits 10.1.17 capp?capability list poin ter register (pci-pci?d30:f0) offset address: 34h attribute: ro default value: 50h size: 8 bits 10.1.18 intr?interrupt informat ion register (pci-pci?d30:f0) offset address: 3ch ? 3dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 31:0 prefetchable memory base upper portion (pmbu) ? r/w. upper 32-bits of the prefetchable address base. bit description 31:0 prefetchable memory limit upper portion (pmlu) ? r/w. upper 32-bits of the prefetchable address limit. bit description 7:0 capabilities pointer (ptr) ? ro. indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. bit description 15:8 interrupt pin (ipin) ? ro. the pci bridge does not as sert an interrupt. 7:0 interrupt line (iline) ? r/w. software written value to indicate which interrupt line (vector) the interrupt is conn ected to. no hardware action is taken on this register. since the bridge does not gene rate an interrupt, bios should program this value to ffh as per the pci bri dge specification. intel ? ich8 family datasheet 441 pci-to-pci bridge registers (d30:f0) 10.1.19 bctrl?bridge control register (pci-pci?d30:f0) offset address: 3eh ? 3fh attribute: r/wc, ro default value: 0000h size: 16 bits bit description 15:12 reserved 11 discard timer serr# enable (dte ) ? r/w. controls the generation of serr# on the primary interface in respon se to the dts bit being set: 0 = do not generate serr# on a secondary timer discard 1 = generate serr# in response to a secondary timer discard 10 discard timer status (dts) ? r/wc. this bit is set to 1 when the secondary discard timer (see the sdt bit below) expires for a delayed transaction in the hard state. 9 secondary discard timer (sdt) ? r/w. this bit sets the maximum number of pci clock cycles that the intel? ich8 waits fo r an initiator on pci to repeat a delayed transaction request. the counter starts once the delayed transaction data is has been returned by the system and is in a buffer in the ich8 pci bridge. if the master has not repeated the transaction at least once before the counter expires, the ich8 pci bridge discards the transaction from its queue. 0 = the pci master timeout value is between 2 15 and 2 16 pci clocks 1 = the pci master timeout value is between 2 10 and 2 11 pci clocks 8 primary discard timer (pdt ) ? r/w. this bit is r/w for software compatibility only. 7 fast back to back enable (fbe) ? ro. hardwi red to 0. the pci logi c will not generate fast back-to-back cycles on the pci bus. 6 secondary bus reset (sbr) ? r/w. controls pcirst# assertion on pci. 0 = bridge de-asserts pcirst# 1 = bridge asserts pcirst#. when pcirst # is asserted, the delayed transaction buffers, posting buffers, and the pci bus ar e initialized back to reset conditions. the rest of the part and the config uration registers are not affected. 5 master abort mode (mam ) ? r/w. controls the ich8 pci bridge?s behavior when a master abort occurs: master abort on (g)mch/ich8 interconnect (dmi): 0 = bridge asserts trdy# on pc i. it drives all 1?s for reads, and discards data on writes. 1 = bridge returns a target abort on pci. master abort pci (non-locked cycles): 0 = normal completion status will be re turned on the (g)mch/ich8 interconnect. 1 = target abort completion st atus will be returned on th e (g)mch/ich8 interconnect. note: all locked reads will return a completer abort completion status on the (g)mch/ ich8 interconnect. 4 vga 16-bit decode (v16d) ? r/w. enables the ich8 pci bridge to provide 16-bits decoding of vga i/o address precluding the decode of vga alias addresses every 1 kb. this bit requires the vgae bi t in this register be set. pci-to-pci bridge registers (d30:f0) 442 intel ? ich8 family datasheet 10.1.20 spdh?secondary pci device hiding register (pci-pci?d30:f0) offset address: 40h?41h attribute: r/w, ro default value: 00h size: 16 bits this register allows software to hide the pci devices, either plugged into slots or on the motherboard. 3 vga enable (vgae) ? r/w. when set to a 1, the ich8 pci bridge forwards the following transactions to pci regardless of th e value of the i/o base and limit registers. the transactions are qualified by cm d.mse (d30:f0:04 bit 1) and cmd.iose (d30:f0:04 bit 0) being set. ? memory addresses: 000a0000h-000bffffh ? i/o addresses: 3b0h-3bbh and 3c0h-3dfh. for the i/o addresses, bits [63:16] of the address must be 0, and bits [15:10] of the address are ignored (i.e., aliased). the same holds true from secondary accesses to the primary interface in reverse. that is, when the bit is 0, memory and i/o a ddresses on the second ary interface between the above ranges will be claimed. 2 isa enable (ie) ? r/w. this bit only applies to i/ o addresses that are enabled by the i/o base and i/o limit registers and are in the fi rst 64 kb of pci i/o space. if this bit is set, the ich8 pci bridge will block any fo rwarding from primary to secondary of i/o transactions addressing the last 768 bytes in each 1-kb block (o ffsets 100h to 3ffh). 1 serr# enable (see) ? r/w. controls the forwarding of secondary interface serr# assertions on the primary interface. when se t, the pci bridge will forward serr# pin. ? serr# is asserted on the secondary interface. ? this bit is set. ? cmd.see (d30:f0:04 bit 8) is set. 0 parity error response enable (pere) ? r/w. 0 = disable 1 = the ich8 pci bridge is enabled for parity error reporting based on parity errors on the pci bus. bit description bit description 15:4 reserved 3 hide device 3 (hd3) ? r/w, ro. same as bit 0 of th is register, except for device 3 (ad[19]) 2 hide device 2 (hd2) ? r/w, ro. same as bit 0 of this register, except for device 2 (ad[18]) 1 hide device 1 (hd1) ? r/w, ro. same as bit 0 of this regi ster, except for device 1 (ad[17]) 0 hide device 0 (hd0) ? r/w, ro. 0 = the pci configuration cycles for this slot are not affected. 1 = intel ? ich8 hides device 0 on the pci bus. this is done by masking the idsel (keeping it low) for configuration cycles to that device. since the device will not see its idsel go active, it will not respond to pci configuration cycles and the processor will think the device is not presen t. ad[16] is used as idsel for device 0. intel ? ich8 family datasheet 443 pci-to-pci bridge registers (d30:f0) 10.1.21 dtc?delayed transa ction control register (pci-pci?d30:f0) offset address: 44h ? 47h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 31 discard delayed transactions (ddt) ? r/w. 0 = logged delayed transactions are kept. 1 = the ich8 pci bridge will discard any delayed transactions it has logged. this includes transactions in th e pending queue, and any transactions in the active queue, whether in the hard or soft dt st ate. the prefetchers will be disabled and return to an idle state. note: if a transaction is running on pci at the time this bit is set, that transaction will continue until either the pci master di sconnects (by de-asserting frame#) or the pci bridge disconnects (by asserting stop#). this bit is cleared by the pci bridge when the delayed transaction queu es are empty and have returned to an idle state. software sets this bit and polls for its completion 30 block delayed transactions (bdt) ? r/w. 0 = delayed transactions accepted 1 = the ich8 pci bridge will not accept incoming transactions which will result in delayed transactions. it will blindly retr y these cycles by asserting stop#. all postable cycles (memory writes) will still be accepted. 29: 8 reserved 7: 6 maximum delayed transactions (mdt) ? r/w. controls the maximum number of delayed transactions that the ich8 pci bridge will run. encodings are: 00 =) 2 active, 5 pending 01 =) 2 active, no pending 10 =) 1 active, no pending 11 =) reserved 5 reserved 4 auto flush after disco nnect enable (afade) ? r/w. 0 = the pci bridge will retain any fetched da ta until required to discard by producer/ consumer rules. 1 = the pci bridge will flush any prefetched data after either the pci master (by de- asserting frame#) or the pci bridge (b y asserting stop#) disconnects the pci transfer. 3 never prefetch (np) ? r/w. 0 = prefetch enabled 1 = the ich8 will only fetch a single dw an d will not enable prefetching, regardless of the command being an memory read (mr), memory read line (mrl), or memory read multiple (mrm). pci-to-pci bridge registers (d30:f0) 444 intel ? ich8 family datasheet 10.1.22 bps?bridge proprietary status register (pci-pci?d30:f0) offset address: 48h ? 4bh attribute: r/wc, ro default value: 00000000h size: 32 bits 2 memory read multiple prefetch disable (mrmpd) ? r/w. 0 = mrm commands will fetch multiple ca che lines as defined by the prefetch algorithm. 1 = memory read multiple (mrm) commands wi ll fetch only up to a single, 64-byte aligned cache line. 1 memory read line prefetch disable (mrlpd) ? r/w. 0 = mrl commands will fetch multiple cache lines as defined by the prefetch algorithm. 1 = memory read line (mrl) commands will fe tch only up to a single, 64-byte aligned cache line. 0 memory read prefetch disable (mrpd) ? r/w. 0 = mr commands will fetch up to a 64-byte aligned cache line. 1 = memory read (mr) commands will fetch only a single dw. bit description bit description 31:17 reserved 16 perr# assertion detected (pad) ? r/wc. this bit is set by hardware whenever the perr# pin is asserted on the ri sing edge of pci clock. this includes cases in which the chipset is the agent driving perr#. it re mains asserted until cleared by software writing a 1 to this location. when enabled by the perr#-to-serr# enable bit (in the bridge policy configuration regi ster), a 1 in this bit can generate an internal serr# and be a source for the nmi logic. this bit can be used by software to de termine the source of a system problem. 15:7 reserved 6:4 number of pending transactions (npt) ? ro. this read-only indicator tells debug software how many transactions are in the pending queue. possible values are: 000 = no pending transaction 001 = 1 pending transaction 010 = 2 pending transactions 011 = 3 pending transactions 100 = 4 pending transactions 101 = 5 pending transactions 110 - 111 = reserved note: this field is not valid if dtc.mdt (offset 44h:bits 7:6) is any value other than ?00?. 3:2 reserved 1:0 number of active transactions (nat) ? ro. this read-only indicator tells debug software how many transactions are in the active queue. possible values are: 00 = no active transactions 01 = 1 active transaction 10 = 2 active transactions 11 = reserved intel ? ich8 family datasheet 445 pci-to-pci bridge registers (d30:f0) 10.1.23 bpc?bridge policy configuration register (pci-pci?d30:f0) offset address: 4ch ? 4fh attribute: r/w, ro default value: 00001200h size: 32 bits bit description 31:14 reserved 13:8 upstream read latency threshold (urlt) ? r/w: this field specifies the number of pci clocks after internally enqueuing an upstream memory read request at which point the pci target logic should insert wait states in order to optimize lead-off latency. when the master returns after this thre shold has been reached and data has not arrived in the delayed transaction completion queue, then the pci target logic will insert wait states instead of immediately re trying the cycle. the pci target logic will insert up to 16 clocks of target initial latency (from frame# assertion to trdy# or stop# assertion) before retrying the pci re ad cycle (if the read data has not arrived yet). note that the starting event for this read latency timer is not explicitly visible externally. a value of 0h disables this policy completely such that wait states will never be inserted on the read lead-off data phase. the default value (12h) specifies 18 pci clocks (540 ns) and is a pproximately 4 clocks less than the typical idle lead-off latency expected for desktop ich8 systems. this value may need to be changed by bi os, depending on the platform. 7 subtractive decode policy (sdp) ? r/w. 0 = the pci bridge always forwards memory and i/o cycles that are not claimed by any other device on the backbone (primary interface) to the pci bus (secondary interface). 1 = the pci bridge will not claim and forwar d memory or i/o cycles at all unless the corresponding space enable bit is set in the command register. note: the boot bios destination selection strap can force the bios accesses to pci. 6 perr#-to-serr# enable (pse) ? r/w. when this bit is set, a 1 in the perr# assertion status bit (in the bri dge proprietary status register) will result in an internal serr# assertion on the primary side of th e bridge (if also enabled by the serr# enable bit in the primary command re gister). serr# is a source of nmi. 5 secondary discard timer testmode (sdtt) ? r/w. 0 = the secondary discard timer expiration will be defined in bctrl.sdt (d30:f0:3e, bit 9) 1 = the secondary discard timer wi ll expire after 128 pci clocks. 4:3 reserved cmd.mse bpc.sdp range forwarding policy 0 0 don?t care forward unclaimed cycles 0 1 don?t care forwarding prohibited 1 x within range positive decode and forward 1 x outside subtractive decode & forward pci-to-pci bridge registers (d30:f0) 446 intel ? ich8 family datasheet 10.1.24 svcap?subsystem vend or capability register (pci-pci?d30:f0) offset address: 50h ? 51h attribute: ro default value: 000dh size: 16 bits 10.1.25 svid?subsystem vendor ids register (pci-pci?d30:f0) offset address: 54h ? 57h attribute: r/wo default value: 00000000h size: 32 bits 2 peer decode enable (pde) ? r/w. 0 = the pci bridge assumes th at all memory cycles target main memory, and all i/o cycles are not claimed. 1 = the pci bridge will perform peer decode on any memory or i/o cycle from pci that falls outside of the memory and i/o window registers 1 reserved 0 received target abort serr# enable (rtae) ? r/w. when set, the pci bridge will report serr# when psts.rta (d30:f0:06 bit 12) or ssts.rta (d30:f0:1e bit 12) are set, and cmd.see (d30:f0:04 bit 8) is set. bit description bit description 15:8 next capability (next) ? ro. value of 00h indicates this is the last item in the list. 7:0 capability identifier (cid) ? ro. value of 0dh indicates th is is a pci bridge subsystem vendor capability. bit description 31:16 subsystem identifier (sid) ? r/wo. indicates the subsys tem as identified by the vendor. this field is write once and is locked down until a bridge reset occurs (not the pci bus reset). 15:0 subsystem vendor identifier (svid) ? r/wo. indicates the manufacturer of the subsystem. this field is write once and is locked down until a bridge reset occurs (not the pci bus reset). intel ? ich8 family datasheet 447 ide controller registers (d31:f1) (mobile only) 11 ide controller registers (d31:f1) (mobile only) 11.1 pci configuration registers (ide?d31:f1) note: address locations that are not shown should be treated as reserved (see section 6.2 for details). all of the ide registers are in the core we ll. none of the registers can be locked. note: the ich8m ide controller is not arbitrated as a pci device; th erefore, it does not need a master latency timer. table 119. ide controller pci regi ster address map (ide-d31:f1) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 00h r/w, ro 06h?07h pcists pci status 0280h r/w, ro 08h rid revision identification see register description ro 09h pi programming interface 8ah r/w, ro 0ah scc sub class code 01h ro 0bh bcc base class code 01h ro 0ch cls cache line size 00h ro 0dh pmlt primary master latency timer 00h ro 10h?13h pcmd_bar primary command block base address 00000001h r/w, ro 14h?17h pcnl_bar primary control block base address 00000001h r/w, ro 18h?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1ch?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20h?23h bm_base bus master base address 00000001h r/w, ro 2ch?2dh ide_svid subsystem vendor id 00h r/wo 2eh?2fh ide_sid subsystem id 0000h r/wo 3c intr_ln interrupt line 00h r/w 3d intr_pn interrupt pin see register description ro 40h?41h ide_timp primary ide timing 0000h r/w 42h?43h ide_tims secondary ide timing 0000h r/w 44h slv_idetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control 00h r/w 4ah?4bh sdma_tim synchronous dma timing 0000h r/w 54h ide_config ide i/o configuration 00000000h r/w c0h atc apm trapping control 00h r/w c4h ats apm trapping status 00h r/wc ide controller registers (d31:f1) (mobile only) 448 intel ? ich8 family datasheet 11.1.1 vid?vendor id entification register (ide?d31:f1) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16-bit lockable: no power well: core 11.1.2 did?device identificati on register (ide?d31:f1) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16-bit lockable: no power well: core bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich8m ide controller. refer to the intel ich8 ich8m family eds specification update for the value of the device id register. intel ? ich8 family datasheet 449 ide controller registers (d31:f1) (mobile only) 11.1.3 pcicmd?pci command register (ide?d31:f1) address offset: 04h ? 05h attribute: ro, r/w default value: 00h size: 16 bits bit description 15:11 reserved 10 interrupt disable (id) ? r/w. 0 = enables the ide controller to assert in ta# (native mode) or irq14/15 (legacy mode). 1 = disable. the interrup t will be deasserted. 9 fast back to back enable (fbe) ? ro. reserved as 0. 8 serr# enable (serr_en) ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. reserved as 0. 6 parity error response (per) ? ro. reserved as 0. 5 vga palette snoop (vps) ? ro. reserved as 0. 4 postable memory write enable (pmwe) ? ro. reserved as 0. 3 special cycle enable (sce) ? ro. reserved as 0. 2 bus master enable (bme) ? r/w. controls the ich8m?s abilit y to act as a pci master for ide bus master transfers. 1 memory space enable (mse) ? r/w. 0 = disables access. 1 = enables access to the ide expansion memory range. the exbar register (offset 24h) must be programmed before this bit is set. note: bios should set this bit to a 1. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus master io registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set. notes: 1.separate bits are provided (ide decode enable, in the ide timing register) to independently disable the prim ary or secondary i/o spaces. 2.when this bit is 0 and the ide controll er is in native mode, the interrupt pin register (see section 11.1.19 ) will be masked (the interrupt will not be asserted). if an interrupt occurs while the masking is in place and the interrupt is still active when the masking ends, the interru pt will be allowe d to be asserted. ide controller registers (d31:f1) (mobile only) 450 intel ? ich8 family datasheet 11.1.4 pcists ? pci status register (ide?d31:f1) address offset: 06h ? 07h attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? ro. reserved as 0. 14 signaled system error (sse) ? ro. reserved as 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated by bus master ide interface function. 1 = bus master ide interface function, as a master, generated a master abort. 12 reserved as 0 ? ro. 11 reserved as 0 ? ro. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; however, the ich8m does not have a real devsel# signal associated with the ide unit, so these bits have no effect. 8 data parity error detected (dped) ? ro. reserved as 0. 7 fast back to back capable (fb2bc) ? ro. reserved as 1. 6 user definable features (udf) ? ro. reserved as 0. 5 66mhz capable (66mhz_cap) ? ro. reserved as 0. 4 reserved 3 interrupt status (ints) ? ro . this bit is independent of the state of the interrupt disable bit in the command register. 0 = interrupt is cleared. 1 = interrupt/msi is asserted. 2:0 reserved intel ? ich8 family datasheet 451 ide controller registers (d31:f1) (mobile only) 11.1.5 rid?revision identifica tion register (ide?d31:f1) offset address: 08h attribute: ro default value: see bit description size: 8 bits 11.1.6 pi?programming interf ace register (ide?d31:f1) address offset: 09h attribute: ro, r/w default value: 8ah size: 8 bits 11.1.7 scc?sub class code register (ide?d31:f1) address offset: 0ah attribute: ro default value: 01h size: 8 bits bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 8 (ich8) family specification update for the value of the revision id register bit description 7 this read-only bit is a 1 to indicate that the ich8m supports bus master operation 6:4 reserved. hardwired to 000b. 3 sop_mode_cap ? ro. this read-only bit is a 1 to indicate that the secondary controller supports both legacy and native modes. 2 sop_mode_sel ? r/w. this read/write bit determines the mode that the secondary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode 1 pop_mode_cap ? ro. this read-only bit is a 1 to indicate that the primary controller supports both legacy and native modes. 0 pop_mode_sel ? r/w. this read/write bits dete rmines the mode that the primary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode bit description 7:0 sub class code (scc) ? ro. 01h = ide device, in the context of a mass storage device. ide controller registers (d31:f1) (mobile only) 452 intel ? ich8 family datasheet 11.1.8 bcc?base class code register (ide?d31:f1) address offset: 0bh attribute: ro default value: 01h size: 8 bits 11.1.9 cls?cache line size register (ide?d31:f1) address offset: 0ch attribute: ro default value: 00h size: 8 bits 11.1.10 pmlt?primary master latency timer register (ide?d31:f1) address offset: 0dh attribute: ro default value: 00h size: 8 bits 11.1.11 pcmd_bar?primary co mmand block base address register (ide?d31:f1) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 8-byte i/o space is used in native mo de for the primary cont roller?s command block. bit description 7:0 base class code (bcc) ? ro. 01 = mass storage device bit description 7:0 cache line size (cls) ? ro. 00h = hardwired. the ide contro ller is implemented internally so this register has no meaning. bit description 7:0 master latency timer count (mltc) ? ro. 00h = hardwired. the ide controller is implem ented internally, and is not arbitrated as a pci device, so it does not need a master latency timer. bit description 31:16 reserved 15:3 base address ? r/w. base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. intel ? ich8 family datasheet 453 ide controller registers (d31:f1) (mobile only) 11.1.12 pcnl_bar?primary co ntrol block base address register (ide?d31:f1) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 4-byte i/o space is used in native mo de for the primary controller?s command block. 11.1.13 scmd_bar?secondary co mmand block base address register (ide d31:f1) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. 11.1.14 scnl_bar?secondary co ntrol block base address register (ide d31:f1) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. bit description 31:16 reserved 15:2 base address ? r/w. base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. bit description 31:16 reserved 15:3 base address ? r/w. base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. ide controller registers (d31:f1) (mobile only) 454 intel ? ich8 family datasheet 11.1.15 bm_base ? bus master base address register (ide?d31:f1) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface function uses base address register 5 to request a 16- byte i/o space to provide a software interf ace to the bus master functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. 11.1.16 ide_svid ? subsystem vendor identification (ide?d31:f1) address offset: 2ch ? 2dh attribute: r/wo default value: 00h size: 16 bits lockable: no power well: core 11.1.17 ide_sid ? subsystem identification register (ide?d31:f1) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core bit description 31:16 reserved 15:4 base address ? r/w. this field provides the ba se address of the i/o space (16 consecutive i/o locations). 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. bit description 15:0 subsystem vendor id (svid) ? r/wo. the svid register, in combination with the subsystem id (sid) register, enables the operating system (o s) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value can be read, but subsequent writes to this register have no effect. the value written to this register will also be readable via the corresponding svid registers for the usb#1, usb#2, and smbus functions. bit description 15:0 subsystem id (sid) ? r/wo. the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this regi ster. after that, the value can be read, but subsequent writes to this register have no ef fect. the value written to this register will also be readable via the corresponding sid registers for the usb#1, usb#2, and smbus functions. intel ? ich8 family datasheet 455 ide controller registers (d31:f1) (mobile only) 11.1.18 intr_ln?interrupt li ne register (ide?d31:f1) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 11.1.19 intr_pn?interrupt pi n register (ide?d31:f1) address offset: 3dh attribute: ro default value: see register description size: 8 bits 11.1.20 ide_timp ? ide primary timing register (ide?d31:f1) address offset: 40 ? 41h attribute: r/w default value: 0000h size: 16 bits this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. bit description 7:0 interrupt line (int_ln) ? r/w. this field is used to co mmunicate to software the interrupt line that the inte rrupt pin is connected to. bit description 7:0 interrupt pin ? ro. this reflects the value of d31ip.pip (chipset config registers:offset 3100h:bits 7:4). bit description 15 ide decode enable (ide) ? r/w. the ide i/o space enable bit (d31:f1:04h, bit 0) in the command register must be set in order for this bit to have any effect. 0 = disable. 1 = enables the ich8m to decode the command (1f0?1f7h) and control (3f6h) blocks. this bit also effects the memory decode range for ide expansion. 14 drive 1 timing register enable (sitre) ? r/w. 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and use the slave ide timing register for drive 1 13:12 iordy sample point (isp) ? r/w. the setting of these bits determine the number of pci clocks between ide ior#/iow# asse rtion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 11:10 reserved 9:8 recovery time (rct) ? r/w. the setting of these bits determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock ide controller registers (d31:f1) (mobile only) 456 intel ? ich8 family datasheet 7 drive 1 dma timing enable (dte1) ? r/w. 0 = disable. 1 = enable the fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 6 drive 1 prefetch/posting enable (ppe1) ? r/w. 0 = disable. 1 = enable prefetch and posting to the ide data port for this drive. 5 drive 1 iordy sample point enable (ie1) ? r/w. 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive. 4 drive 1 fast timing bank (time1) ? r/w. 0 = accesses to the data port will us e compatible timings for this drive. 1 = when this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time . when this bit = 1 and bit 14 = 1, accesses to the data port will use the iordy sample point and recover time specified in the slave ide timing register. 3 drive 0 dma timing enable (dte0) ? r/w. 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 2 drive 0 prefetch/posting enable (ppe0) ? r/w. 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. 1 drive 0 iordy sample point enable (ie0) ? r/w. 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. 0 drive 0 fast timing bank (time0) ? r/w. 0 = accesses to the data port will us e compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample poin t, and bits 9:8 for the recovery time bit description intel ? ich8 family datasheet 457 ide controller registers (d31:f1) (mobile only) 11.1.21 ide_tims ? ide secondary timing register (ide?d31:f1) address offset: 42h ? 43h attribute: r/w default value: 0000h size: 16 bits 11.1.22 slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) address offset: 44h attribute: r/w default value: 00h size: 8 bits bit description 15 ide decode enable (ide) ? r/w. this bit enables/di sables the secondary decode. the ide i/o space enable bit (d31:f1:04h, bi t 0) in the command register must be set in order for this bit to ha ve any effect. additionally, se parate configuration bits are provided (in the ide i/o configuration regist er) to individually disable the secondary ide interface signals, even if th e ide decode enable bit is set. 0 = disable. 1 = enables the ich8m to decode the associated command blocks (170?177h) and control block (376h). accesses to these ranges return 00h, as the secondary channel is not implemented. 14:12 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich8m since a secondary channel does not exist. 11 reserved 10:0 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich8m since a secondary channel does not exist. bit description 7:4 no operation (nop) ? r/w. these bits are read/write for le gacy software compatibility, but have no functionality in the ich8m. 3:2 primary drive 1 iordy sample point (pisp1) ? r/w. this field determines the number of pci clocks between ior#/iow# assertion and the first iordy sample point, if the access is to drive 1 da ta port and bit 14 of the ide timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 1:0 primary drive 1 recovery time (prct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/ iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks ide controller registers (d31:f1) (mobile only) 458 intel ? ich8 family datasheet 11.1.23 sdma_cnt?synchronous dma control register (ide?d31:f1) address offset: 48h attribute: r/w default value: 00h size: 8 bits bit description 7:4 reserved 3:2 no operation (nop) ? r/w. thes e bits are read/write for lega cy software compatibility, but have no functionality in the ich8m. 1 primary drive 1 synchronous dma mode enable (psde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 1. 0 primary drive 0 synchronous dma mode enable (psde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 0. intel ? ich8 family datasheet 459 ide controller registers (d31:f1) (mobile only) 11.1.24 sdma_tim?synchronous dma timing register (ide?d31:f1) address offset: 4ah ? 4bh attribute: r/w default value: 0000h size: 16 bits note: for fast_pcb1 = 1 (133 mhz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to section 5.15.4 for details. bit description 15:14 reserved 13:12 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich8m. 11:10 reserved 9:8 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich8m. 7:6 reserved 5:4 primary drive 1 cycle time (pct1) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. 3:2 reserved 1:0 primary drive 0 cycle time (pct0) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved ide controller registers (d31:f1) (mobile only) 460 intel ? ich8 family datasheet 11.1.25 ide_config?ide i/o configuration register (ide?d31:f1) address offset: 54h attribute: r/w default value: 00000000h size: 32 bits bit description 31:24 reserved 23:20 miscellaneous scratchpad (ms) ? r/w. previously defined as a scratchpad bit to indicate to a driver that ata- 100 is supported. this is not us ed by software as all they needed to know was located in bits 7: 4. see the definition of those bits. 19:18 no operation (nop) ? r/w. these bits are read/write for le gacy software compatibility, but have no functionality in the ich8m. 17:16 sig_mode ? r/w. these bits are used to control mode of the ide signal pins for swap bay support. if the prs bit (chipset config registers:offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 15:14 no operation (nop) ? r/w. these bits are read/write for le gacy software compatibility, but have no functionality in the ich8m. 13 fast primary drive 1 base clock (fast_pcb1) ? r/w. this bit is used in conjunction with the pct1 bits to enable/disable ultra ata/100 timings for the primary slave drive. 0 = disable ultra ata/100 timing for the primary slave drive. 1 = enable ultra ata/100 timing for the primary slave drive (overrides bit 1 in this register). 12 fast primary drive 0 base clock (fast_pcb0) ? r/w. this bit is used in conjunction with the pct0 bits to enable/disable ultra ata/100 timings for the primary master drive. 0 = disable ultra ata/100 timing for the primary master drive. 1 = enable ultra ata/100 timing for the primary ma ster drive (overrides bit 0 in this register). 11:8 reserved 7 no operation (nop) ? r/w. these bits are read/write for le gacy software compatibility, but have no functionality in the ich8m. 6 no operation (nop) ? r/w. these bits are read/write for le gacy software compatibility, but have no functionality in the ich8m. 5 primary slave channel cable reporting ? r/w. bios should program this bit to tell the ide driver which cable is plugged into the channel. 0 = 40 conductor cable is present. 1 = 80 conductor cable is present. 4 primary master channel cable reporting ? r/w. same description as bit 5 3:2 no operation (nop) ? r/w. these bits are read/w rite for legacy software compatibility, but have no functionality in the ich8m. 1 primary drive 1 base clock (pcb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 0 primary drive 0 base clock (pcb0) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings intel ? ich8 family datasheet 461 ide controller registers (d31:f1) (mobile only) 11.1.26 atc?apm trapping cont rol register (ide?d31:f1) address offset: c0h attribute: r/w default value: 00h size: 8 bits 11.1.27 ats?apm trapping stat us register (ide?d31:f1) address offset: c4h attribute: r/wc default value: 00h size: 8 bits bit description 7:2 reserved 1 slave trap (pst) ? r/w. enables trapping and smi# assertion on legacy i/o accesses to 1f0h-1f7h and 3f6h. the active device must be the slave device for the trap and/or smi# to occur. 0 master trap (pmt) ? r/w. enables trapping and sm i# assertion on legacy i/o accesses to 1f0h-1f7h and 3f6h. the active device must be master device for the trap and/or smi# to occur. bit description 7:2 reserved 1 slave trap status (psts) ? r/wc. indicates that a trap occurred to the slave device 0 master trap status (pmts) ? r/wc. indicates that a trap occurred to the master device ide controller registers (d31:f1) (mobile only) 462 intel ? ich8 family datasheet 11.2 bus master ide i/o registers (ide?d31:f1) the bus master ide function uses 16 bytes of i/o space, allocated via the bmiba register, located in device 31:function 1 configuration space, offset 20h. all bus master ide i/o space registers can be acce ssed as byte, word, or dword quantities. reading reserved bits returns an indetermin ate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). the description of the i/o registers is shown in table 120 . 11.2.1 bmicp?bus master ide command register (ide?d31:f1) address offset: bmibase + 00h attribute: r/w default value: 00h size: 8 bits table 120. bus master ide i/o registers bmibase + offset mnemonic register name default type 00 bmicp bus master ide command primary 00h r/w 01 ? reserved 00h ro 02 bmisp bus master ide status primary 00h r/w, r/wc 03 ? reserved 00h ro 04?07 bmidp bus master ide descriptor table pointer primary xxxxxxxxh r/w bit description 7:4 reserved. returns 0. 3 read / write control (r/wc) ? r/w. this bit sets the di rection of the bus master transfer: this bit must not be changed when the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved. returns 0. 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus master operatio n is still active (i.e., the bus master ide active bit (bmibase + 02h, bit 0) of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bit (bmibase + 02h, bit 2) in the bus master ide status regi ster for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controller. bus master operation does not actually start unless the bus master enable bit (d31:f1:04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detect ed changing from 0 to 1. the controller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bu s master ide active bit being cleared or the interrupt bit of the bus master ide status register for that ide channel being set, or both. hardware does not clear this bit automatically. intel ? ich8 family datasheet 463 ide controller registers (d31:f1) (mobile only) 11.2.2 bmisp?bus master ide st atus register (ide?d31:f1) address offset: bmibase + 02h attribute: r/w, r/wc default value: 00h size: 8 bits 11.2.3 bmidp?bus master ide desc riptor table pointer register (ide?d31:f1) address offset: bmibase + 04h attribute: r/w default value: all bits undefined size: 32 bits bit description 7 prd interrupt status (prdis) ? r/wc. 0 = when this bit is cleared by software, the interrupt is cleared. 1 = set when the host controller completes execution of a prd that has its interrupt bit (bit 2 of this register) set. 6 drive 1 dma capable ? r/w. 0 = not capable. 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 1 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the ich8m does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 5 drive 0 dma capable ? r/w. 0 = not capable 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 0 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the ich8m does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 4:3 reserved. returns 0. 2 interrupt ? r/wc. software can use this bit to determine if an ide device has asserted its interru pt line (ideirq). 0 = software clears this bit by writing a 1 to it. if th is bit is cleared while the interrupt is still active, this bit will remain clear until another assert ion edge is detected on the interrupt line. 1 = set by the rising edge of the ide interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal i/o apic. when this bit is read as 1, all data transferred from the drive is visible in system memory. 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encounters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the ich8m when the last transfer for a region is performed, where eot for that region is set in the region descriptor. it is also cleared by the ich8m when the start bit is cleared in the command register. when this bit is read as 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the ich8m when the start bi t is written to the command register. bit description 31:2 address of descriptor table (addr) ? r/w. corresponds to a[31:2]. the descriptor table must be dw ord-aligned. the descriptor table must not cross a 64-k boundary in memory. 1:0 reserved ide controller registers (d31:f1) (mobile only) 464 intel ? ich8 family datasheet intel ? ich8 family datasheet 465 sata controller registers (d31:f2) 12 sata controller registers (d31:f2) 12.1 pci configuration registers (sata?d31:f2) note: address locations that are not shown should be treated as reserved. all of the sata registers are in the core well. none of the registers can be locked. table 121. sata controller pci register address map (sata?d31:f2) (sheet 1 of 2) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 02b0h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface see register description see register description 0ah scc sub class code see register description see register description 0bh bcc base class code 01h ro 0dh pmlt primary master latency timer 00h ro 10h?13h pcmd_bar primary command block base address 00000001h r/w, ro 14h?17h pcnl_bar primary control block base address 00000001h r/w, ro 18h?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1ch?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20h?23h bar legacy bus master base address 00000001h r/w, ro 24h?27h abar / sidpba ahci base address / sata index data pair base address 00000000h see register description 2ch?2dh svid subsystem vendor identification 0000h r/wo 2eh?2fh sid subsystem identification 0000h r/wo 34h cap capabilities pointer 80h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description. ro 40h?41h ide_timp primary ide timing 0000h r/w 42h?43h ide_tims secondary ide timing 0000h r/w 44h sidetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control 00h r/w sata controller registers (d31:f2) 466 intel ? ich8 family datasheet note: the ich8 sata controller is not arbitrated as a pci device, therefore it does not need a master latency timer. 12.1.1 vid?vendor iden tification regist er (sata?d31:f2) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bit lockable: no power well: core 4ah?4bh sdma_tim synchronous dma timing 0000h r/w 54h?57h ide_config ide i/o configuration 00000000h r/w 70h?71h pid pci power management capability id see register description ro 72h?73h pc pci power management capabilities 4002h ro 74h?75h pmcs pci power management control and status 0000h r/w, ro, r/wc 80h?81h msici message signaled in terrupt capability id 7005h ro 82h?83h msimc message signaled interrupt message control 0000h ro, r/w 84h?87h msima message signaled interrupt message address 00000000h ro, r/w 88h?89h msimd message signaled interrupt message data 0000h r/w 90h map address map 00h r/w 92h?93h pcs port control and status 0000h r/w, ro, r/wc 94h?97h sir sata initialization register 00000000h r/w a0h siri sata indexed registers index 00h r/w a4h strd sata indexed register data xxxxxxxxh r/w a8h?abh scap0 sata capability register 0 00100012h ro ach?afh scap1 sata capability register 1 00000048h ro c0h atc apm trapping control 00h r/w c4h ats atm trapping status 00h r/wc d0h?d3h sp scratch pad 00000000h r/w e0h?e3h bfcs bist fis control/status 00000000h r/w, r/wc e4h?e7h bftd1 bist fis transmit data, dw1 00000000h r/w e8h?ebh bftd2 bist fis transmit data, dw2 00000000h r/w table 121. sata controller pci register address map (sata?d31:f2) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit va lue assigned to intel. intel vid = 8086h intel ? ich8 family datasheet 467 sata controller registers (d31:f2) 12.1.2 did?device identificati on register (sata?d31:f2) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16 bit lockable: no power well: core 12.1.3 pcicmd?pci command register (sata?d31:f2) address offset: 04h ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich8 sata controller. note: the value of this field will change dependent upon the value of the map register. refer to the intel ich8 family specification update . bit description 15:11 reserved 10 interrupt disable ? r/w. this disables pin-based intx# interrupts. this bit has no effect on msi operation. 0 = internal intx# messages are generated if there is an interrupt and msi is not enabled. 1 = internal intx# messages will not be generated. 9 fast back to back enable (fbe) ? ro. reserved as 0. 8 serr# enable (serr_en) ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. reserved as 0. 6 parity error response (per) ? r/w. 0 = disabled. sata controller will not gene rate perr# when a data parity error is detected. 1 = enabled. sata controller will generate pe rr# when a data parity error is detected. 5 vga palette snoop (vps) ? ro. reserved as 0. 4 postable memory write enable (pmwe) ? ro. reserved as 0. 3 special cycle en able (sce) ? ro. reserved as 0. 2 bus master enable (bme) ? r/w. this bit controls the ich8?s ability to act as a pci master for ide bus master transfers. this bit does not impact the generation of completions for split transaction commands. 1 memory space enable (mse) ? r/w / ro. controls access to the sata controller?s target memory space (for ahci). note: when map.mv (offset 90:bits 1:0) is not 00h, this register is read only (ro). software is responsible for clearing th is bit before entering combined mode. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus mast er i/o registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set. sata controller registers (d31:f2) 468 intel ? ich8 family datasheet 12.1.4 pcists ? pci status register (sata?d31:f2) address offset: 06h ? 07h attribute: r/wc, ro default value: 02b0h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 12.1.5 rid?revision identificati on register (sata?d31:f2) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected by sata controller. 1 = sata controller detects a parity error on its interface. 14 signaled system error (sse) ? ro. reserved as 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated. 1 = sata controller, as a master , generated a master abort. 12 reserved as 0 ? ro. 11 signaled target abort (sta) ? ro. reserved as 0. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; controls the devi ce select time for the sata controller?s pci interface. 8 data parity error detected (dped) ? ro. for ich8, this bit can only be set on read completions received from sibus where there is a parity error. 1 = sata controller, as a master, either detect s a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. 7 fast back to back capable (fb2bc) ? ro. reserved as 1. 6 user definable features (udf) ? ro. reserved as 0. 5 66mhz capable (66mhz_cap) ? ro. reserved as 1. 4 capabilities list (cap_list) ? ro. this bit indicates the presence of a capabilities list. the minimum requirement for the capabili ties list must be pci power management for the sata controller. 3 interrupt status (ints) ? ro. reflects the state of intx# messages. 0 = interrupt is cleared (ind ependent of the state of in terrupt disabl e bit in the command register [offset 04h]). 1 = interrupt is to be asserted 2:0 reserved bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 8 (ich8) family specification update for the value of the revision id register intel ? ich8 family datasheet 469 sata controller registers (d31:f2) 12.1.6 pi?programmin g interface register (sata?d31:f2) 12.1.6.1 when sub class code register (d31:f2:offset 0ah) = 01h address offset: 09h attribute: r/w, ro default value: see bit description size: 8 bits 12.1.6.2 when sub class code register (d31:f2:offset 0ah) = 04h address offset: 09h attribute: ro default value: 00h size: 8 bits bit description 7 this read-only bit is a 1 to indicate th at the ich8 supports bus master operation 6:4 reserved. will always return 0. 3 secondary mode native capable (snc) ? ro. 0 = secondary controller only supports legacy mode. 1 = secondary controller supports both legacy and native modes. when map.mv (d31:f2:offset 90:bits 1:0) is any value other than 00b, this bit reports as a 0. when map.mv is 00b , this bit reports as a 1. 2 secondary mode nati ve enable (sne) ? r/w / ro. determines the mode th at the secondary channel is operating in. 0 = secondary controller operatin g in legacy (compatibility) mode 1 = secondary controller operating in native pci mode. when map.mv (d31:f2:offset 90:bits 1:0) is any value other than 00b, this bit is read- only (ro). software is responsible for cleari ng this bit before entering combined mode. when map.mv is 00b, this bit is read/write (r/w). if this bit is set by software, then the pne bit (bit 0 of this register ) must also be set by software. while in theory these bits can be programmed separately, such a configuration is not supported by hardware. 1 primary mode native capable (pnc) ? ro. 0 = primary controller only supports legacy mode. 1 = primary controller supports both legacy and native modes. when map.mv (d31:f2:offset 90:bits 1:0) is any value other than 00b, this bit reports as a 0. when map.mv is 00b , this bit reports as a 1 0 primary mode native enable (pne) ? r/w / ro. determines the mode that the primary channel is operating in. 0 = primary controller operating in legacy (compatibility) mode. 1 = primary controller operating in native pci mode. when map.mv (d31:f2:offset 90:bits 1:0) is any value other than 00b, this bit is read- only (ro). software is responsible for cleari ng this bit before entering combined mode. when map.mv is 00b, this bit is read/write (r/w). if this bit is set by software, then the sne bit (bit 2 of this register) must also be set by software. while in theory these bits can be programmed separately, such a configuration is not supported by hardware. bit description 7:0 interface (if) ? ro. when configured as raid, this register becomes read only 0. sata controller registers (d31:f2) 470 intel ? ich8 family datasheet 12.1.6.3 when sub class code regi ster (d31:f2:offset 0ah) = 06h address offset: 09h attribute: ro default value: 01h size: 8 bits 12.1.7 scc?sub class code register (sata?d31:f2) address offset: 0ah attribute: ro default value: see bit description size: 8 bits 12.1.8 bcc?base class code register (sata?d31:f2sata?d31:f2) address offset: 0bh attribute: ro default value: 01h size: 8 bits bit description 7:0 interface (if) ? ro. indicates the sata controll er supports ahci, rev 1.1. bit description 7:0 sub class code (scc) ? ro. this field specifies the sub-class code of the controller, per the table below: intel ? ich8 only: ich8m only: (intel ? ich8r, ich8dh, ich8do, and ich8m-e only): scc reg i ster attr ib ute s cc reg i ster va l ue ro 01h (ide controller) map.sms (d31:f2:offset 90h:bit 7:6) scc register value 00b 01h (ide controller) 01b 06h (ahci controller) map. s m s ( d 3 1:f 2 : off set 90h:bit 7:6) scc de f au l t reg i ster value 00b 01h (ide controller) 01b 06h (ahci controller) 10b 04h (raid controller) bit description 7:0 base class code (bcc) ? ro. 01h = mass storage device intel ? ich8 family datasheet 471 sata controller registers (d31:f2) 12.1.9 pmlt?primary master latency timer register (sata?d31:f2) address offset: 0dh attribute: ro default value: 00h size: 8 bits 12.1.10 pcmd_bar?primary co mmand block base address register (sata?d31:f2) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 8-byte i/o space is used in native mo de for the primary controller?s command block. 12.1.11 pcnl_bar?primary contro l block base address register (sata?d31:f2) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 4-byte i/o space is used in native mo de for the primary controller?s command block. bit description 7:0 master latency timer count (mltc) ? ro. 00h = hardwired. the sata controller is im plemented internally, and is not arbitrated as a pci device, so it does no t need a master latency timer. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwi red to 1 to indicate a request for i/o space. sata controller registers (d31:f2) 472 intel ? ich8 family datasheet 12.1.12 scmd_bar?secondary co mmand block base address register (ide d31:f1) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. 12.1.13 scnl_bar?secondary co ntrol block base address register (ide d31:f1) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwi red to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwi red to 1 to indicate a request for i/o space. intel ? ich8 family datasheet 473 sata controller registers (d31:f2) 12.1.14 bar ? legacy bus mast er base address register (sata?d31:f2) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface function uses base address register 5 to request a 16- byte io space to provide a software interface to the bus master functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. 12.1.15 abar/sidpba1 ? ahci base address register/serial ata index data pair base address (sata?d31:f2) when the programming interface is not ide (i .e., is not 01h), this register is named abar. when the programming interface is ide, this register becomes sidpba. note that hardware does not clear those ba bits when switching from ide sku to non- ide sku or vice versa. bios is responsible for clearing those bits to 0 since the number of writable bits changes after sku switching (as indicated by a change in cc.scc). in the case, this register will then have to be re-programmed to a proper value. 12.1.15.1 when cc.scc is not 01h address offset: 24?27h attribute: r/wo default value: 00000000h size: 32 bits when the programming interface is not ide, the register represents a memory bar allocating space for the ahci memory registers defined in section 12.4 . notes: 1. when the map.mv register is programmed for combined mode (00b), this register is ro. software is responsible for clearing th is bit before entering combined mode. 2. the abar register must be set to a value of 0001_0000h or greater. bit description 31:16 reserved 15:4 base address ? r/w. this field provides the base address of the i/o space (16 consecutive i/o locations). 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:11 base address (ba) ? r/w. base address of register memory space (aligned to 1 kb) 10:4 reserved 3 prefetchable (pf) ? ro. indicates th at this range is not pre-fetchable 2:1 type (tp) ? ro. indicates that this range can be mapped anywhere in 32-bit address space. 0 resource type indicator (rte) ? ro. hardwired to 0 to indicate a request for register memory space. sata controller registers (d31:f2) 474 intel ? ich8 family datasheet 12.1.15.2 when cc.scc is 01h address offset: 24h ? 27h attribute: r/wo default value: 00000001h size: 32 bits when the programming interface is ide, the register becomes an i/o bar allocating 16 bytes of i/o space for the i/o-mapped registers defined in section 12.3 . note that although 16 bytes of locations are allocated, only 8 bytes are used to as sindx and sdata registers; with the remaining 8 bytes preserved for future enhancement. 12.1.16 svid?subsystem vendor identification register (sata?d31:f2) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 12.1.17 sid?subsystem identifica tion register (sata?d31:f2) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 12.1.18 cap?capabilities poin ter register (sata?d31:f2) address offset: 34h attribute: ro default value: 80h size: 8 bits bit description 31:16 reserved 15:4 base address (ba) ? r/w. base address of the i/o space. 3:1 reserved 0 resource type indicator (rte) ? ro. indicates a re quest for i/o space. bit description 15:0 subsystem vendor id (svid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 15:0 subsystem id (sid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 7:0 capabilities pointer (cap_ptr) ? ro. indicates that the first capabili ty pointer offset is 80h. this value changes to 70h if the map. mv register (dev 31:f2:90h, bits 1:0) in configuration space indicates that the sata function and pata functions are combined (values of 10b or 10b) or sub class code (cc. scc) (dev 31:f2:0ah) is configure as ide mode (value of 01). intel ? ich8 family datasheet 475 sata controller registers (d31:f2) 12.1.19 int_ln?interrupt line register (sata?d31:f2) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 12.1.20 int_pn?interrupt pi n register (sata?d31:f2) address offset: 3dh attribute: ro default value: see register description size: 8 bits 12.1.21 ide_tim ? ide timing register (sata?d31:f2) address offset: primary: 40h ? 41h attribute: r/w secondary: 42h ? 43h default value: 0000h size: 16 bits this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation unless otherwise noted. bit description 7:0 interrupt line ? r/w. this field is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:0 interrupt pin ? ro. this reflects the value of d 31ip.sip (chipset configuration registers: offset 3100h:bits 11:8). bit description 15 ide decode enable (ide) ? r/w. individually enable/disable the primary or secondary decode. 0 = disable. 1 = enables the intel ? ich8 to decode the associated command blocks (1f0?1f7h for primary, 170?177h for secondary) and control block (3f6h for primary and 376h for secondary). this bit effects the ide deco de ranges for both legacy and native-mode decoding. note: this bit affects sata operation in both combined and non-combined ata modes. see section 5.16 for more on ata modes of operation. 14 drive 1 timing register enable (sitre) ? r/w. 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and us e the slave ide timing register for drive 1 13:12 iordy sample point (isp) ? r/w. the setting of these bits determines the number of pci clocks between ide ior#/iow# asse rtion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved sata controller registers (d31:f2) 476 intel ? ich8 family datasheet 11:10 reserved 9:8 recovery time (rct) ? r/w. the setting of these bits determines the minimum number of pci clocks between the last io rdy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock 7 drive 1 dma timing enable (dte1) ? r/w. 0 = disable. 1 = enable the fast timing mode for dma transf ers only for this drive. pio transfers to the ide data port will run in compatible timing. 6 drive 1 prefetch/posting enable (ppe1) ? r/w. 0 = disable. 1 = enable prefetch and posting to the ide data port for this drive. 5 drive 1 iordy sample point enable (ie1) ? r/w. 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive. 4 drive 1 fast timing bank (time1) ? r/w. 0 = accesses to the data port will us e compatible timings for this drive. 1 = when this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. when this bit = 1 and bit 14 = 1, accesses to th e data port will use the iordy sample point and recover time specified in the slave ide timing register. 3 drive 0 dma timing enable (dte0) ? r/w. 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 2 drive 0 prefetch/posting enable (ppe0) ? r/w. 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. 1 drive 0 iordy sample point enable (ie0) ? r/w. 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. 0 drive 0 fast timing bank (time0) ? r/w. 0 = accesses to the data port will us e compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time bit description intel ? ich8 family datasheet 477 sata controller registers (d31:f2) 12.1.22 sidetim?slave ide timi ng register (sata?d31:f2) address offset: 44h attribute: r/w default value: 00h size: 8 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation unless otherwise noted. bit description 7:6 secondary drive 1 iordy sample point (sisp1) ? r/w. this field determines the number of pci clocks between ide ior#/iow # assertion and the first iordy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 5:4 secondary drive 1 recovery time (srct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/ iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register fo r secondary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks 3:2 primary drive 1 iordy sample point (pisp1) ? r/w. this field determines the number of pci clocks between ior#/iow# asse rtion and the first iordy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 1:0 primary drive 1 recovery time (prct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/ iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks sata controller registers (d31:f2) 478 intel ? ich8 family datasheet 12.1.23 sdma_cnt?synchronous dma control register (sata?d31:f2) address offset: 48h attribute: r/w default value: 00h size: 8 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation unless otherwise noted. 12.1.24 sdma_tim?synchronous dma timing register (sata?d31:f2) address offset: 4ah ? 4bh attribute: r/w default value: 0000h size: 16 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation, unless otherwise noted. bit description 7:4 reserved 3 secondary drive 1 synchronou s dma mode enable (ssde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for secondary channel drive 1 2 secondary drive 0 synchronou s dma mode enable (ssde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for secondary drive 0. 1 primary drive 1 synchronous dma mode enable (psde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 1 0 primary drive 0 synchronous dma mode enable (psde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 0 bit description 15:14 reserved 13:12 secondary drive 1 cycle time (sct1) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to- stop (rp) time is also determin ed by the settin g of these bits. 11:10 reserved scb1 = 0 (33 mhz clock) scb1 = 1 (66 mhz clock) fast_scb1 = 1 (133 mhz clock) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved intel ? ich8 family datasheet 479 sata controller registers (d31:f2) 9:8 secondary drive 0 cycle time (sct0) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to- stop (rp) time is also determin ed by the setting of these bits. 7:6 reserved 5:4 primary drive 1 cycle time (pct1) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. 3:2 reserved 1:0 primary drive 0 cycle time (pct0) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. bit description scb1 = 0 (33 mhz clock) scb1 = 1 (66 mhz clock) fast_scb1 = 1 (133 mhz clock) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved pcb1 = 0 (33 mhz clock) pcb1 = 1 (66 mhz clock) fast_pcb1 = 1 (133 mhz clock) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved pcb1 = 0 (33 mhz clock) pcb1 = 1 (66 mhz clock) fast_pcb1 = 1 (133 mhz clock) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved sata controller registers (d31:f2) 480 intel ? ich8 family datasheet 12.1.25 ide_config?ide i/o configuration register (sata?d31:f2) address offset: 54h ? 57h attribute: r/w default value: 00000000h size: 32 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation, unless otherwise noted. bit description 31:24 reserved 23:20 scratchpad (sp2). intel ? ich8 does not perform any actions on these bits. 19:18 sec_sig_mode ? r/w. these bits are used to control mode of the secondary ide signal pins for swap bay support. if the srs bit (chipset configuration registers:offset 3414h:bit 1) is 1, the reset states of bits 19:18 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved note: in the non-combined mode, these bits ar e for software compatibility and have no effect on the sata controller. in the combined mode, these bits are controlling the behavior of the pata controller. (mobile only) 17:16 prim_sig_mode ? r/w. these bits are used to control mode of the primary ide signal pins for mobile swap bay support. if the prs bit (chipset confid e registers:offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved note: in the non-combined mode, these bits ar e for software compatibility and have no effect on the sata controller. in the combined mode, these bits are controlling the behavior of the pata controller. (mobile only) 15 fast secondary drive 1 base clock (fast_scb1) ? r/w. this bit is used in conjunction with the sct1 bits (d31:f2:4ah, bits 13:12) to enable/disable ultra ata/ 100 timings for the secondary slave drive. 0 = disable ultra ata/100 timing for the secondary slave drive. 1 = enable ultra ata/100 timing for the seco ndary slave drive (overrides bit 3 in this register). 14 fast secondary drive 0 base clock (fast_scb0) ? r/w. this bit is used in conjunction with the sct0 bits (d31:f2:4ah, bits 9:8) to enable/disable ultra ata/100 timings for the secondary master drive. 0 = disable ultra ata/100 timing for the secondary master drive. 1 = enable ultra ata/100 timing for the secondary master drive (overrides bit 2 in this register). intel ? ich8 family datasheet 481 sata controller registers (d31:f2) 12.1.26 pid?pci power management capability identification register (sata?d31:f2) address offset: 70h ? 71h attribute: ro default value: xx01h size: 16 bits 13 fast primary drive 1 base clock (fast_pcb1) ? r/w. this bit is used in conjunction with the pct1 bits (d31:f2:4ah, bits 5:4) to enable/disable ultra ata/100 timings for the primary slave drive. 0 = disable ultra ata/100 timing for the primary slave drive. 1 = enable ultra ata/100 timing for the primary slave drive (overrides bit 1 in this register). 12 fast primary drive 0 base clock (fast_pcb0) ? r/w. this bit is used in conjunction with the pct0 bits (d31:f2:4ah, bits 1:0) to enable/disable ultra ata/100 timings for the primary master drive. 0 = disable ultra ata/100 timing for the primary master drive. 1 = enable ultra ata/100 timing for the primary master drive (overrides bit 0 in this register). 11:8 reserved 7:4 scratchpad (sp1). ich8 does not perform any action on these bits. 3 secondary drive 1 base clock (scb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 2 secondary drive 0 base clock (scbo) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 1 primary drive 1 base clock (pcb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 0 primary drive 0 base clock (pcb0) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings bit description bits description 15:8 next capability (next) ? ro. 00h ? if scc = 01h (ide mode). a8h ? for all other values of scc to po int to the next capability structure. 7:0 capability id (cid) ? ro. indicates that this pointer is a pci power management. sata controller registers (d31:f2) 482 intel ? ich8 family datasheet 12.1.27 pc?pci power manageme nt capabilities register (sata?d31:f2) address offset: 72h ? 73h attribute: ro default value: 4003h size: 16 bits f 12.1.28 pmcs?pci power mana gement control and status register (sata?d31:f2) address offset: 74h ? 75h attribute: ro, r/w, r/wc default value: 0008h size: 16 bits bits description 15:11 pme support (pme_sup) ? ro. indicate s pme# can be generated from the d3 hot state in the sata host controller. 10 d2 support (d2_sup) ? ro. hardwired to 0. the d2 state is not supported 9 d1 support (d1_sup) ? ro. hardwired to 0. the d1 state is not supported 8:6 auxiliary current (aux_cur) ? ro. pme# from d3cold state is not supported, therefore this field is 000b. 5 device specific initialization (dsi) ? ro. ha rdwired to 0 to indicate that no device- specific initialization is required. 4 reserved 3 pme clock (pme_clk) ? ro. hardwired to 0 to in dicate that pci clock is not required to generate pme#. 2:0 version (ver) ? ro. hardwired to 011 to indi cates support for revision 1.2 of the pci power management specification. bits description 15 pme status (pmes) ? r/wc. bit is set when a pme event is to be requested, and if this bit and pmee is set, a pme# will be generated from the sata controller 14:9 reserved 8 pme enable (pmee) ? r/w. when set, the sata co ntroller generates pme# form d3 hot on a wake event. 7:4 reserved 3 no soft reset (nsfrst) ? ro. these bits are used to indicate whether devices transitioning from d3 hot state to d0 state will perform an internal reset. 0 = device transitioning from d3 hot state to d0 state perfo rm an internal reset. 1 = device transitioning from d3 hot state to d0 state do not perform an internal reset. configuration content is preserve d. upon transition from the d3 hot state to d0 state initialized state, no addition al operating system interventi on is required to preserve configuration context beyond writing to the power state bits. regardless of this bit, the controller transition from d3 hot state to d0 state by a system or bus segment reset will retu rn to the state d0 uninitialized with only pme context preserved if pme is supported and enabled. 2 reserved 1:0 power state (ps) ? r/w. these bits are used both to determine the current power state of the sata controller and to set a new power state. 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller?s configuration space is available, but the i/o and memory spaces are not. additi onally, interrupts are blocked. intel ? ich8 family datasheet 483 sata controller registers (d31:f2) 12.1.29 msici?message signal ed interrupt capability identification (sata?d31:f2) address offset: 80h ? 81h attribute: ro default value: 7005h size: 16 bits note: there is no support for msi when the software is operating in legacy (ide) mode when ahci is not enabled. prior to switch ing from ahci to ide mode, software must make sure that msi is disabled. 12.1.30 msimc?message signaled interrupt message control (sata?d31:f2) address offset: 82h ? 83h attribute: r/w, ro default value: 0000h size: 16 bits note: there is no support for msi when the software is operating in legacy (ide) mode when ahci is not enabled. prior to switch ing from ahci to ide mode, software must make sure that msi is disabled. bits description 15:8 next pointer (next): indicates the next item in the list is the pci power management pointer. 7:0 capability id (cid): capabilities id indicates msi. bits description 15:8 reserved 7 64 bit address capable (c64): capable of generating a 32-bit message only. sata controller registers (d31:f2) 484 intel ? ich8 family datasheet 6:4 multiple message enable (mme) : when this field is cleared to ?000? (and msie is set), only a single msi message will be generated for all sata po rts, and bits [15:0] of the message vector will be driven from md[15:0]. when this field is set to ?001? (and msie is set), two msi messages will be generated. bit [15:1] of the message vectors will be driven from md[15:1] and bit [0] of the message vector will be driven dependen t on which sata port is the so urce of the interrupt: ?0? for port 0, and ?1? for ports 1, 2, 3, 4 and 5. when this field is set to ?010? (and msie is set), four messages will be generated, one for each sata port. bits[15:2] of the message ve ctors will be driven from md[15:2], while bits[1:0] will be driven dependent on which sa ta port is the source of the interrupt: ?00? for port 0, ?01? for port 1, ?10? for po rt 2, and ?11? for ports 3, 4, and 5). when this field is set to ?100? (and msie is set), seven messages wi ll be generated, one for each sata port. bits[15:2] of the mess age vectors will be driven from md[15:3], while bits[2:0] will be driv en dependent on which sata port is the source of the interrupt: ?000? for port 0, ?001? for port 1, ?010? for port 2, ?011? for port 3, ?100? for port 4, ?101 for port 5, and ?110? for port 6 (ccc interrupt). . values ?011b? to ?111b? are reserved. if this field is set to one of these reserved values, the results are undefined. note: note: the ccc interrupt is generated on unimplemented port (ahci pi register bit equal to 0). if ccc interrupt is disabled , no msi shall be generated for the port dedicated to the ccc in terrupt. when ccc interrupt occurs, md[2:0] is dependant on ccc_ctl.int (in addition to mme). 3:1 multiple message capable (mmc): indicates the number of interrupt messages supported by the ich8 sata controller. 000 = 1 msi capable (when cc.scc bit is set to 01h. msi is not supported in ide mode) 010 = 4 msi capable 100 = 8 msi capable 0 msi enable (msie): if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. this bi t is r/w when sc.scc is not 01h and is read-only 0 when cc.scc is 01h. note that cmd.id bit has no effect on msi. note: software must clear this bit to ?0? to di sable msi first before changing the number of messages allocated in the mmc field. software must al so make sure this bit is cleared to ?0? when operating in legacy mode (when ghc.ae = 0). bits description mme value driven on msi memory write bits[15:2] bit[2] bit[1] bit[0] 000 md[15:0] md[1] md[1] md[0] 001 md[15:2] md[1] md[1] ports 0: 0 ports 1,2,3: 1 010 md[15:2] port 0: 0 port 1: 0 port 2: 1 port 3: 1 port 0: 0 port 1: 0 port 2: 1 port 3: 1 port 0: 0 port 1: 1 port 2: 0 port 3: 1 100 md[15:3] port 0: 000 port 1: 001 port 2: 010 port 3: 011 port 4: 100 port 5: 101 port 0: 000 port 1: 001 port 2: 010 port 3: 011 port 4: 100 port 5: 101 port 0: 000 port 1: 001 port 2: 010 port 3: 011 port 4: 100 port 5: 101 intel ? ich8 family datasheet 485 sata controller registers (d31:f2) 12.1.31 msima? message signaled interrupt message address (sata?d31:f2) address offset: 84h ? 87h attribute: ro, r/w default value: 00000000h size: 32 bits note: there is no support for msi when the software is operating in legacy (ide) mode when ahci is not enabled. prior to switch ing from ahci to ide mode, software must make sure that msi is disabled. 12.1.32 msimd?message signaled interrupt message data (sata?d31:f2) address offset: 88h-89h attribute: r/w default value: 0000h size: 16 bits note: there is no support for msi when the software is operating in legacy (ide) mode when ahci is not enabled. prior to switch ing from ahci to ide mode, software must make sure that msi is disabled. bits description 31:2 address (addr): lower 32 bits of the system specified message address, always dword aligned. 1:0 reserved bits description 15:0 data (data) ? r/w : this 16-bit field is programmed by system software if msi is enabled. its content is driven onto the lowe r word of the data bus of the msi memory write transaction. note that when the mme fiel d is set to ?001? or ?010?, bit [0] and bits [1:0] respectively of the msi memory write transaction will be driven based on the source of the interrupt rather than from md [2:0]. see the description of the mme field. sata controller registers (d31:f2) 486 intel ? ich8 family datasheet 12.1.33 map?address map re gister (sata?d31:f2) address offset: 90h attribute: r/w default value: 00h size: 8 bits bits description 7:6 sata mode select (sms) ? r/w: sw programs these bits to control the mode in which the sata hba should operate: 00b = ide mode 01b = ahci mode 10b = raid mode 11b = reserved notes: 1. the sata function device id will chan ge based on the value of this register. 2. when combined mode is used (mv = ?1 0?), only ide mode is allowed. ide mode can be selected when ah ci and/or raid are enabled 3. when switching from ahci or raid mode to ide mode, a 2 port sata controller (device 31, func tion 5) shall be enabled. 4. ahci mode may only be selected when mv = 00 5. raid mode may only be selected when mv = 00 6. programming these bits with values that are invalid (e.g. selecting raid when in combined mode) will result in inde terministic behavior by the hardware. 7. software shall not manipulate sms during runtime operation (i.e., the os will not do this). the bios may choose to sw itch from one mode to another during post. 5:2 reserved. 1:0 (desktop only) map value ? r/w. map value (mv): reserved 1:0 (mobile only) map value ? r/w. map value (mv): the value in the bits below indi cate the address range the sata ports responds to, and whet her or not the pata and sata functions are combined. when in combined mode, the ahci memory space is not available and ahci may not be used. 00 =non-combined. p0 is primary master, p2 is the primary slave. p1 is secondary master, p3 is the secondary slave. 01 =reserved 10 =combined. p0 is primary master. p2 is primary slave. ide is secondary 11 =reserved notes: 1. programming these bits with values that are invalid (e.g., selecting raid when in combined mode) will result in inde terministic behavior by the hardware. 2. sw shall not manipulate mv during runt ime operation; i.e. the os will not do this. the bios may choose to switch fr om one mode to another during post. intel ? ich8 family datasheet 487 sata controller registers (d31:f2) 12.1.34 pcs?port control and st atus register (sata?d31:f2) address offset: 92h ? 93h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits by default, the sata ports are set to the disabled state (bits [5:0] = ?0?). when enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. when disabled, the port is in the ?off? state and cannot detect any devices. if an ahci-aware or raid enabled operating system is being booted then system bios shall ensure that all supported sata ports are enabled prior to passing control to the os. once the ahci aware os is booted it becomes the enabling/disabling policy owner for the individual sata ports. this is acco mplished by manipulating a port?s pxsctl and pxcmd fields. because an ahci or raid awar e os will typically not have knowledge of the pxe bits and because the pxe bits act as master on/off switches for the ports, pre- boot software must ensure that these bits are set to ?1? prior to booting the os, regardless as to whether or not a device is currently on the port. bits description 15 oob retry mode (orm) ? r/w. 0 = the sata controller will not retry after an oob failure 1 = the sata controller will continue to retry after an oob failure until successful (infinite retry) 14 reserved. 13 port 5 present (p5p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabl ed via p5e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 3 has been detected. 12 port 4 present (p4p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabl ed via p4e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 3 has been detected. 11 port 3 present (p3p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabl ed via p3e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 3 has been detected. 10 port 2 present (p2p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabl ed via p2e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 2 has been detected. 9 port 1 present (p1p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabl ed via p1e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 1 has been detected. sata controller registers (d31:f2) 488 intel ? ich8 family datasheet 8 port 0 present (p0p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabled via p0e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 0 has been detected. 7:6 reserved 5 port 5 enabled (p5e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p5cmd.sud (offset abar+298h:bit 1) 4 port 4 enabled (p4e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p4cmd.sud (offset abar+298h:bit 1) 3 port 3 enabled (p3e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p3cmd.sud (offset abar+298h:bit 1) 2 port 2 enabled (p2e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p2cmd.sud (offset abar+218h:bit 1) 1 port 1 enabled (p1e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p1cmd.sud (offset abar+198h:bit 1) 0 port 0 enabled (p0e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p0cmd.sud (offset abar+118h:bit 1) bits description intel ? ich8 family datasheet 489 sata controller registers (d31:f2) 12.1.35 sclkcg?sata clock gating control register address offset: 94h-97h attribute: r/w default value: 00000000h size: 32 bits . bit description 31 reserved 30 sata clock request enabled (scre) ? r/w. 0 = sata clock request protocol is disa bled. sataclkreq# pin when in native function will always output '0' to keep the sata clock running. 1 = sata clock request protoc ol is enabled. sataclkr eq# pin when in native function will behave as the serial ata clock request to the system clock chip. 28 reserved 27:24 (desktop only) reserved 27:24 (mobile only) sata initialization field 3 (sif3) ? r/w. bios shall always program this register to the value 0ah. a ll other values are reserved. 23 sata initialization field 2 (sif2) ? r/w. bios shall always program this register to the value 0b. all other values are reserved. 22:9 reserved 8:0 sata initialization field 1 (sif1) ? r/w. bios shall always program this register to the value 180h. al l other values are reserved. sata controller registers (d31:f2) 490 intel ? ich8 family datasheet 12.1.36 sclkgc?sata clock gene ral configuration register address offset: 9ch attribute: r/w default value: 00h size: 8 bits . 12.1.37 siri?sata indexed registers index register address offset: a0h attribute: r/w default value: 00h size: 8 bits . 12.1.38 strd ? sata indexed regist er data register address offset: a4h attribute: r/w default value: xxxxxxxxh size: 32 bits . bit description 7:2 reserved 1 sata2-port configuratio n indicator (sata2pind) ? ro. 0 = normal configuration. 1 = one ide controller is implemented supporting only two ports for a primary master and a secondary master. note: when set, bios must ensure that bit 2 and bit 3 of the ahci pi registers are zeros. bios must also make sure that port 2 and port 3 are disabled (via pcs configuration register) and the port clocks are gated (via sclkcg configuration register). 0 sata4-port all master configur ation indicator (sata4pmind) ? ro. 0 = normal configuration. 1 = two ide controllers are implemented, each support ing only two ports for a primary master and a secondary master. note: when set, bios must ensure that bit 2 and bit 3 of the ahci pi registers are zeros. bios must also make sure that port 2 and port 3 are disabled (via pcs configuration register) and the port clocks are gated (via sclkcg configuration register). bit description 7:2 index (idx) ? r/w. this field is a 5-bit index po inter into the sata indexed register space. data is written into and read from the sird register (d31:f2:a4h). 1:0 reserved bit description 31:0 data (dta) ? r/w. 32-bit data value that is written to the register pointed to by siri (d31:f2;a0h) or read from the register pointed to by siri. intel ? ich8 family datasheet 491 sata controller registers (d31:f2) table 122. sata indexed registers index name 00h?03h sata tx termination test register 1 (sttt1) 04h?17h reserved 18h?1bh sata initialization register 18 (sir18) 1ch?1fh sata test mode enable register (stme) 20h?27h reserved 28h?2bh sata initialization register 28 (sir28) 40h?43h sata initialization register 40 (sir40) 44h?73h reserved 74h?77h sata tx termination test register 2 (sttt2) 78h?7bh sata initialization register 78 (sir78) 7ch?83h reserved 84h?87h sata initialization register 84 (sir84) 88h?8bh sata initialization register 88 (sir88) 8ch?8fh sata initialization register 8c (sir8c) 90h?93h sata tx termination test register 3 (sttt3) 94h?97h sata initialization register 94 (sir94) 98h?9fh reserved a0h?a3h sata initializatio n register a0 (sira0) a4h?a7h reserved a8h?abh sata initializatio n register a8 (sira8) ach?afh sata initializatio n register ac (siraf) sata controller registers (d31:f2) 492 intel ? ich8 family datasheet 12.1.39 sttt1 ? sata indexed registers index 00h (sata tx terminatio n test register 1) address offset: index 00h - 03h attribute: r/w default value: 00000000h size: 32 bits . 12.1.40 sir18?sata indexed registers index 18h (sata initialization register 18h) address offset: index 18h - 1bh attribute: r/w default value: 0000025bh size: 32 bits . 12.1.41 stme?sata indexe d registers index 1ch (sata test mode enable register) address offset: index 1ch - 1fh attribute: r/w default value: 00000000h size: 32 bits . bit description 31:2 reserved. 1 port 1 tx termination test enable ? r/w: 0 = port 1 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 1 tx termination. note: this bit only to be used for system board testing. 0 port 0 tx termination test enable ? r/w: 0 = port 0 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 0 tx termination. note: this bit only to be used for system board testing. bit description 31:10 reserved. 9:0 bios programs this field to 1000011011b. bit description 31:19 reserved. 18 sata test mode enable bit ? r/w: 0 = entrance to intel ich6 sata test modes are disabled. 1 = this bit allows entrance to intel ich6 sata test modes when set. note: this bit only to be used for system board testing. 17:0 reserved. intel ? ich8 family datasheet 493 sata controller registers (d31:f2) 12.1.42 sir28?sata indexe d registers index 28h (sata initialization register 28h) address offset: index 28h - 2bh attribute: r/w default value: 00cc2080h size: 32 bits . 12.1.43 sir40?sata indexe d registers index 40h (sata initialization register 40h) address offset: index 40h - 43h attribute: r/w default value: 0011006dh size: 32 bits . 12.1.44 sttt2 ? sata indexed regi sters index 74h (sata tx termination test register 2) address offset: index 74h - 77h attribute: r/w default value: 00000000h size: 32 bits . bit description 31:0 bios programs this field to 00cc2080h. bit description 31:24 reserved 23:16 bios programs this field to 22h. 15:0 reserved bit description 31:18 reserved. 17 port 3 tx termination test enable ? r/w: 0 = port 3 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 3 tx termination. note: this bit only to be used for system board testing. 16 port 2 tx termination test enable ? r/w: 0 = port 2 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 2 tx termination. note: this bit only to be used for system board testing. 15:0 reserved. sata controller registers (d31:f2) 494 intel ? ich8 family datasheet 12.1.45 sir78?sata indexed registers index 78h (sata initialization register 78h) address offset: index 78h - 7bh attribute: r/w default value: 00330000h size: 32 bits . 12.1.46 sir84?sata indexed registers index 84h (sata initialization register 84h) address offset: index 84h - 87h attribute: r/w default value: 0000001bh size: 32 bits . 12.1.47 sir88?sata indexed registers index 88h (sata initialization register 88h) address offset: index 88h - 8bh attribute: r/w default value: 2d2d2424h size: 32 bits . 12.1.48 sir8c?sata indexe d registers index 8ch (sata initialization register 8ch) address offset: index 8ch - 8fh attribute: r/w default value: 24240055h size: 32 bits . bit description 31:24 reserved 23:16 bios programs this field to 22h. 15:0 reserved bit description 31:0 bios programs this field to 0000001bh. bit description 31:0 bios programs this field to 24242424h. bit description 31:0 bios programs this field to 090900aah. intel ? ich8 family datasheet 495 sata controller registers (d31:f2) 12.1.49 sttt3 ? sata indexed regi sters index 90h (sata tx termination test register 3) address offset: index 90h - 93h attribute: r/w default value: 00000000h size: 32 bits . 12.1.50 sir94?sata indexe d registers index 94h (sata initialization register 94h) address offset: index 94h - 97h attribute: r/w default value: 00000011h size: 32 bits . 12.1.51 sira0?sata indexe d registers index a0h (sata initialization register a0h) address offset: index a0h - a3h attribute: r/w default value: 0000001bh size: 32 bits . 12.1.52 sira8?sata indexe d registers index a8h (sata initialization register a8h) address offset: index a8h - abh attribute: r/w default value: 002d0024h size: 32 bits . bit description 31:2 reserved. 1 port 5 tx termination test enable ? r/w: 0 = port 1 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 1 tx termination. note: this bit only to be used for system board testing. 0 port 4 tx termination test enable ? r/w: 0 = port 0 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 0 tx termination. note: this bit only to be used for system board testing. bit description 31:0 bios programs this field to 00000022h. bit description 31:0 bios programs this field to 0000001bh. bit description 31:0 bios programs this field to 00240024h. sata controller registers (d31:f2) 496 intel ? ich8 family datasheet 12.1.53 sirac?sata indexe d registers index ach (sata initialization register ach) address offset: index ach - afh attribute: r/w default value: 00240005h size: 32 bits . 12.1.54 satacr0?sata capability register 0 (sata?d31:f2) address offset: a8h?abh attribute: ro default value: 00100012h size: 32 bits note: this register shall be read-only 0 when cc.scc is 01h. bit description 31:0 bios programs this field to 0009000ah. bit description 31:24 reserved 23:20 major revision (majrev) ? ro: major revisi on number of the sata capability pointer implemented. 19:16 minor revision (minrev) ? ro: minor revision number of the sata capability pointer implemented. 15:8 next capability pointer (next) ? ro: points to the next capabi lity structure. 00h indicates this is the last capability pointer. 7:0 capability id (cap)? ro: this value of 12h has been assigned by the pci sig to designate the sata ca pability structure. intel ? ich8 family datasheet 497 sata controller registers (d31:f2) 12.1.55 satacr1?sata capabilit y register 1 (sata?d31:f2) address offset: ach?afh attribute: ro default value: 00000048h size: 32 bits note: this register shall be read-only 0 when cc.scc is 01h. bit description 31:16 reserved 15:4 bar offset (barofst) ? ro : indicates the offset into the bar where the index/data pair are located (in dword granularity). the index and data i/o regi sters are located at offset 10h within the i/o space defined by lbar. a value of 004h indicates offset 10h. 000h = 0h offset 001h = 4h offset 002h = 8h offset 003h = bh offset 004h = 10h offset ... fffh = 3fffh offset (max 16kb) 3:0 bar location (barloc) ? ro : indicates the absolute pci configuration register address of the bar containing the index/da ta pair (in dword granularity). the index and data i/o registers reside within the space defined by lbar in the sata controller. a value of 8h indicates offset 20h, which is lbar. 0000 ? 0011b = reserved 0100b = 10h => bar0 0101b = 14h => bar1 0110b = 18h => bar2 0111b = 1ch => bar3 1000b = 20h => lbar 1001b = 24h => bar5 1010 ? 1110b = reserved 1111b = index/data pair in pci configuration space. this isn?t supported in ich8. sata controller registers (d31:f2) 498 intel ? ich8 family datasheet 12.1.56 atc?apm trapping cont rol register (sata?d31:f2) address offset: c0h attribute: r/w default value: 00h size: 8 bits . 12.1.57 ats?apm trapping stat us register (sata?d31:f2) address offset: c4h attribute: r/wc default value: 00h size: 8 bits . 12.1.58 sp scratch pad register (sata?d31:f2) address offset: d0h attribute: r/w default value: 00000000h size: 32 bits . bit description 7:4 reserved 3 secondary slave trap (sst) ? r/w. enables trapping and smi# assertion on legacy i/o accesses to 170h-177h and 376h. the acti ve device on the secondary interface must be device 1 for the trap and/or smi# to occur. 2 secondary master trap (spt) ? r/w. enables trapping and smi# assertion on legacy i/o accesses to 170h-177h and 376h. the active device on the secondary interface must be device 0 for the trap and/or smi# to occur. 1 primary slave trap (pst) ? r/w. enables trapping and smi# assertion on legacy i/ o accesses to 1f0h-1f7h and 3f6h. the active device on the primar y interface must be device 1 for the trap and/or smi# to occur. 0 primary master trap (pmt) ? r/w. enables trapping and smi# assertion on legacy i/o accesses to 1f0h-1f7h and 3f6h. the acti ve device on the primary interface must be device 0 for the trap and/or smi# to occur. bit description 7:4 reserved 3 secondary slave trap (sst) ? r/wc. indicates that a trap occurred to the secondary slave device. 2 secondary master trap (spt) ? r/wc. indicates that a trap occurred to the secondary master device. 1 primary slave trap (pst) ? r/wc. indicates that a trap occurred to the primary slave device. 0 primary master trap (pmt) ? r/wc. indicates that a trap occurred to the primary master device. bit description 31:0 data (dt) ? r/w. this is a read/write register that is available for software to use. no hardware action is taken on this register. intel ? ich8 family datasheet 499 sata controller registers (d31:f2) 12.1.59 bfcs?bist fis control/st atus register (sata?d31:f2) address offset: e0h ? e3h attribute: r/w, r/wc default value: 00000000h size: 32 bits bits description 31:16 reserved 15 (desktop only) port 5 bist fis initiate (p5bfi) ? r/w. when a rising edge is detected on this bit field, the ich8 initiates a bist fis to th e device on port 5, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 5 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fiss or to return the ich8 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p5bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully 14 (desktop only) port 4 bist fis initiate (p4bfi) ? r/w. when a rising edge is detected on this bit field, the ich8 initiates a bist fis to th e device on port 4, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 4 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fiss or to return the ich8 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p4bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully 13 (desktop only) port 3 bist fis initiate (p3bfi) ? r/w. when a rising edge is detected on this bit field, the ich8 initiates a bist fis to th e device on port 3, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 3 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fiss or to return the ich8 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p3bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully 13 (mobile only) reserved. 12 port 2 bist fis initiate (p2bfi) ? r/w. when a rising edge is detected on this bit field, the ich8 initiates a bist fis to th e device on port 2, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 2 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the ich8 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p2bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully 11 bist fis successful (bfs) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a bist fis transmitted by ich8 receives an r_ok completion status from the device. note: this bit must be cleare d by software prior to initiating a bist fis. sata controller registers (d31:f2) 500 intel ? ich8 family datasheet 10 bist fis failed (bff) ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = this bit is set any time a bist fis transmitted by ich8 receives an r_err completion status from the device. note: this bit must be cleared by softwa re prior to initiating a bist fis. 9 (desktop only) port 1 bist fis initiate (p1bfi) ? r/w. when a rising edge is detected on this bit field, the ich8 initiates a bist fis to th e device on port 1, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 1 is present and read y (not partial/slumber state). after a bist fis is successfully completed, soft ware must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the ich8 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p1bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully 9 (mobile only) reserved. 8 port 0 bist fis initiate (p0bfi) ? r/w. when a rising edge is detected on this bit field, the ich8 initiates a bist fis to th e device on port 0, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 0 is present and read y (not partial/slumber state). after a bist fis is successfully completed, soft ware must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the ich8 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p0bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully 7:2 bist fis parameters . these 6 bits form the contents of the upper 6 bits of the bist fis pattern definition in any bist fis transmitted by the ich8. this field is not port specific ? its contents will be used fo r any bist fis initiated on port 0, port 1, port 2 or port 3. the specific bit definitions are: bit 7: t ? far end transmit mode bit 6: a ? align bypass mode bit 5: s ? bypass scrambling bit 4: l ? far en d retimed loopback bit 3: f ? far end analog loopback bit 2: p ? primitive bit for use with transmit mode 1:0 reserved bits description intel ? ich8 family datasheet 501 sata controller registers (d31:f2) 12.1.60 bftd1?bist fis transmit data1 register (sata?d31:f2) address offset: e4h ? e7h attribute: r/w default value: 00000000h size: 32 bits 12.1.61 bftd2?bist fis transmit data2 register (sata?d31:f2) address offset: e8h ? ebh attribute: r/w default value: 00000000h size: 32 bits bits description 31:0 bist fis transmit data 1 ? r/w. the data programmed into this register will form the contents of the second dword of any bist fis initiated by the ich8. this register is not port specific ? its contents will be used for bist fis initiated on any port. although the 2nd and 3rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 2nd dw regardless of whether or not the ?t? bit is indicated in the bfcs register (d31:f2:e0h). bits description 31:0 bist fis transmit data 2 ? r/w. the data programmed into this register will form the contents of the third dword of any bist fis initiated by the ich8. this register is not port specific ? its contents will be used for bist fis initiated on any port. although the 2nd and 3rd dws of the bist fis are only me aningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 3rd dw regardless of whether or not the ?t? bit is indicated in the bfcs register (d31:f2:e0h). sata controller registers (d31:f2) 502 intel ? ich8 family datasheet 12.2 bus master ide i/ o registers (d31:f2) the bus master ide function uses 16 bytes of i/o space, allocated via the bar register, located in device 31:function 2 configuration space, offset 20h. all bus master ide i/o space registers can be accessed as byte, word, or dword quantities. reading reserved bits returns an indeterminate, inconsistent va lue, and writes to reserved bits have no affect (but should not be attempted). these registers are only used for legacy operation. software must not use these registers when running ahci. the description of the i/o registers is shown in table 123 . table 123. bus master ide i/o register address map bar+ offset mnemonic register default type 00 bmicp command register primary 00h r/w 01 ? reserved ? ro 02 bmisp bus master ide status register primary 00h r/w, r/wc, ro 03 ? reserved ? ro 04?07 bmidp bus master ide descriptor table pointer primary xxxxxxxxh r/w 08 bmics command register secondary 00h r/w 09 ? reserved ? ro 0ah bmiss bus master ide status register secondary 00h r/w, r/wc, ro 0bh ? reserved ? ro 0ch?0fh bmids bus master ide descriptor table pointer secondary xxxxxxxxh r/w 10h air ahci index register 00000000h r/w, ro 14h aidr ahci index data register xxxxxxxxh r/w intel ? ich8 family datasheet 503 sata controller registers (d31:f2) 12.2.1 bmic[p,s]?bus master id e command register (d31:f2) address offset: primary: bar + 00h attribute: r/w secondary: bar + 08h default value: 00h size: 8 bits bit description 7:4 reserved. returns 0. 3 read / write control (r/wc) ? r/w. this bit sets the di rection of the bus master transfer: this bit must not be changed wh en the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved. returns 0. 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus master operation is still active (i.e., the bus master ide active bit (d31:f2:bar + 02h, bit 0) of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bi t in the bus master id e status register for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controller. bus master operation does not actually start unless the bus master enable bit (d31:f1:04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detected changing from 0 to 1. the controller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bu s master ide active bit being cleared or the interrupt bit of the bus master ide status register fo r that ide channel being set, or both. hardware does not clea r this bit automatically. if this bit is cleared to 0 prior to the dma data transfer being initiated by the drive in a sata controller registers (d31:f2) 504 intel ? ich8 family datasheet 12.2.2 bmis[p,s]?bus master id e status register (d31:f2) address offset: primary: bar + 02h attribute: r/w, r/wc, ro secondary: bar + 0ah default value: 00h size: 8 bits bit description 7 prd interrupt status (prdis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the host controller execution of a prd that has its prd_int bit set. 6 drive 1 dma capable ? r/w. 0 = not capable. 1 = capable. set by device dependent code (b ios or device driver ) to indicate that drive 1 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the intel ? ich8 does not use this bit. it is intended for systems that do no t attach bmide to the pci bus. 5 drive 0 dma capable ? r/w. 0 = not capable 1 = capable. set by device dependent code (b ios or device driver ) to indicate that drive 0 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the ich8 does not use this bi t. it is intended for systems that do not at tach bmide to the pci bus. 4:3 reserved. returns 0. 2 interrupt ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set when a device fis is received with the ?i? bit set, provided that software has not disabled interrupts via the ien bit of the device control register (see chapter 5 of the serial ata specification , revision 2.5). 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encoun ters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the ich8 when the last transfer for a region is performed, where eot for that region is set in the regi on descriptor. it is also cleared by the ich8 when the start bus master bit (d31: f2:bar+ 00h, bit 0) is cleared in the command register. when this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the ich8 when the start bit is written to the command register. intel ? ich8 family datasheet 505 sata controller registers (d31:f2) 12.2.3 bmid[p,s]?bus master id e descriptor table pointer register (d31:f5) address offset: primary: bar + 04h?07h attribute: r/w secondary: bar + 0ch ? 0fh default value: all bits undefined size: 32 bits 12.2.3.1 pxssts?serial ata status register (d31:f5) address offset: bar + 00h attribute: ro default value: 00000000h size: 32 bits this is a 32-bit register that conveys the current state of the interface and host. the ich8 updates it continuously and asyn chronously. when the ich8 transmits a comreset to the device, this register is updated to its reset values. bit description 31:2 address of descriptor table (addr) ? r/w. the bits in this field correspond to bits [31:2] of the memory location of the physic al region descriptor (prd). the descriptor table must be dword-aligned. the descriptor tabl e must not cross a 64-kb boundary in memory. 1:0 reserved bit description 31:12 reserved sata controller registers (d31:f2) 506 intel ? ich8 family datasheet 11:8 interface power management (ipm) ? ro . indicates the current interface state: all other values reserved. 7:4 current interface speed (spd) ? ro. indicates the negotiated interface communication speed. all other values reserved. ich8 supports generation 1 communication rates (1.5 gb/sec) and gen 2 rates (3.0 gb/s). 3:0 device detection (det) ? ro . indicates the interface device detection and phy state: all other values reserved. bit description va l ue descr i pt i on 0h device not present or communication not established 1h interface in active state 2h interface in partial power management state 6h interface in slumber power management state v a l ue d escr i p ti on 0h device not present or communication not established 1h generation 1 communication rate negotiated 2h generation 2 communication rate negotiated value description 0h no device de tected and phy communication not established 1h device presence detected but phy communication not established 3h device presence detected and phy communication established 4h phy in offline mode as a result of the interface being disabled or running in a bist loopback mode intel ? ich8 family datasheet 507 sata controller registers (d31:f2) 12.2.3.2 pxsctl ? serial ata control register (d31:f5) address offset: bar + 01h attribute: r/w, ro default value: 00000004h size: 32 bits this is a 32-bit read-write register by which software controls sata capabilities. writes to the scontrol register result in an action being taken by the ich8 or the interface. reads from the register return the last value written to it. bit description 31:20 reserved 19:16 port multiplier port (pmp) ? ro. this field is not used by ahci note: port multiplier not supported by ich8. 15:12 select power management (spm) ? ro. this field is not used by ahci 11:8 interface power management transitions allowed (ipm) ? r/w . indicates which power states the ich8 is allowed to transition to: all other values reserved 7:4 speed allowed (spd) ? r/w. indicates the highest allowable speed of the interface. this speed is limited by the ca p.iss (abar+00h:bit 23:20) field. all other values reserved. ich8 supports generation 1 communication rates (1.5 gb/sec) and gen 2 rates (3.0 gb/s). 3:0 device detection initialization (det) ? r/w . controls the ich8?s device detection and interface initialization. all other values reserved. when this field is written to a 1h, the ich8 initiates comreset and starts the initialization process. when the initialization is complete, this field shall remain 1h until set to another value by software. this field may only be changed to 1h or 4h when pxcmd.st is 0. changing this field while the ich8 is running results in undefined behavior. value description 0h no interface restrictions 1h transitions to the partial state disabled 2h transitions to the slumber state disabled 3h transitions to both partial and slumber states disabled value description 0h no speed negotiation restrictions 1h limit speed negotiation to generation 1 communication rate 2h limit speed negotiation to generation 2 communication rate value description 0h no device detection or initialization action requested 1h perform interface communication initialization sequence to establish communication. this is fu nctionally equivalent to a hard reset and results in the interface being reset and communications re-initialized 4h disable the serial ata interface and put phy in offline mode sata controller registers (d31:f2) 508 intel ? ich8 family datasheet 12.2.3.3 pxserr?serial ata error register (d31:f5) address offset: bar + 02h attribute: r/wc default value: 00000000h size: 32 bits bit description 31:16 diagnostics (diag) ? r/wc . contains diagnostic error information for use by diagnostic software in validating corre ct operation or isolating failure modes: bits description 31:27reserved 26 exchanged (x) : when set to one this bit in dicates a cominit signal was received. this bit is reflected in the interrupt register pxis.pcs. 25 unrecognized fis type (f) : indicates that one or more fiss were received by the transport layer with good crc, but ha d a type field that was not recognized. 24 transport state transition error (t) : indicates that an error has occurred in the transition from one state to another within the transport layer since the last time this bit was cleared. 23 link sequence error (s) : indicates that one or more link state machine error conditions was encountered. the link laye r state machine defines the conditions under which the link layer dete cts an erroneous transition. 22 handshake error (h) : indicates that one or more r_err handshake response was received in response to frame transmis sion. such errors may be the result of a crc error detected by the reci pient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 crc error (c) : indicates that one or more cr c errors occurred with the link layer. 20 disparity error (d) : this field is not used by ahci. 19 10b to 8b decode error (b) : indicates that one or more 10b to 8b decoding errors occurred. 18 comm wake (w) : indicates that a comm wake si gnal was detected by the phy. 17 phy internal error (i) : indicates that the phy dete cted some internal error. 16 phyrdy change (n) : when set to 1, this bit indicates that the internal phyrdy signal changed state since the last time this bit was cleared. in the ich8, this bit will be set when phyrdy changes from a 0 -> 1 or a 1 -> 0. the state of this bit is then reflected in the pxis.prcs interrupt status bit and an interrupt will be generated if enabled. so ftware clears this bit by writing a 1 to it. intel ? ich8 family datasheet 509 sata controller registers (d31:f2) 12.2.4 air?ahci index register (d31:f2) address offset: primary: bar + 10h attribute: r/w, ro default value: 00000000h size: 32 bits this register is available only when cc.scc is not 01h. 15:0 error (err) ? r/wc. the err field contains error inform ation for use by host software in determining the appropriate re sponse to the error condition. if one or more of bits 11:8 of this register are set, the controller will stop the current transfer. bits description 15:12reserved 11 internal error (e) : the sata controller failed due to a master or target abort when attempting to access system memory. 10 protocol error (p) : a violation of the serial ata protocol was detected. note: the ich8 does not set this bit for al l protocol violations that may occur on the sata link. 9 persistent communication or data integrity error (c) : a communication error that was not recovered occurred that is expected to be pe rsistent. pe rsistent communications errors may arise from faul ty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. 8 transient data integrity error (t) : a data integrity erro r occurred that was not recovered by the interface. 7:2 reserved 1 recovered communications error (m) : communications between the device and host was temporarily lost but was re-established. this can arise from a device temporarily being removed, fr om a temporary loss of phy synchronization, or from other causes and may be derived from th e phynrdy signal between the phy and link layers. 0 recovered data integrity error (i) : a data integrity error occurred that was recovered by the inte rface through a retry operation or other recovery action. bit description bit description 31:11 reserved 10:2 index (index) ? r/w. this index register is used to select the dwor d offset of the memory mapped ahci register to be access ed. a dword, word or byte access is specified by the active byte enables of the i/o access to the data register. 1:0 reserved sata controller registers (d31:f2) 510 intel ? ich8 family datasheet 12.2.5 aidr?ahci index da ta register (d31:f2) address offset: primary: bar + 14h attribute: r/w default value: all bits undefined size: 32 bits this register is available on ly when cc.scc is not 01h. 12.3 serial ata index/data pair superset registers all of these i/o registers are in the core we ll. they are exposed only when cc.scc is 01h (i.e., ide programming interface) and the controller is not in combined mode. these are index/data pair registers that are used to access the serialata superset registers (serialata status, serialata control and serialata error). the i/o space for these registers is allocated through sidpba. loca tions with offset from 08h to 0fh are reserved for future expansion. software-write operations to the reserved locations shall have no effect while software-read operations to the reserved locations shall return 0. 12.3.1 sindx?sata index register (d31:f5) address offset: sidpba + 00h attribute: r/w default value: 00000000h size: 32 bits note: these are index/data pair registers that are used to access the ssts, sctl, and serr. the i/o space for these registers is allocated through sidpba. bit description 31:0 data (data) ? r/w . this data register is a ?window? through which data is read or written to the ahci memory mapped registers. a read or write to this data register triggers a corresponding read or write to the memory mapped regi ster pointed to by the index register. the index re gister must be setu p prior to the read or write to this data register. note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. since this is not a physical register, the ?default? value is the same as the default value of the register po inted to by index. bit description 31:16 reserved 15:8 port index (pidx) ? r/w. this index field is used to specify the port of the sata controller at which the po rt-specific ssts, sctl, and serr registers are located. 00h = primary master (port 0) 01h = primary slave (port 2) 02h = secondary master (port 1) 03h = secondary slave (port 3) all other values are reserved. 7:0 register index (ridx) ? r/w. this index field is used to specify one out of three registers currently being indexed into. 00h = ssts 01h = sctl 02h = serr all other values are reserved intel ? ich8 family datasheet 511 sata controller registers (d31:f2) 12.3.2 sdata?sata index data register (d31:f5) address offset: sidpba + 04h attribute: r/w default value: all bits undefined size: 32 bits note: these are index/data pair registers that are used to access the ssts, sctl, and serr. the i/o space for these registers is allocated through sidpba. bit description 31:0 data (data) ? r/w. this data register is a ?window? through which data is read or written to the memory mapped regi sters. a read or write to this data register triggers a corresponding read or write to the memory mapped register poin ted to by the index register. the index register must be setup prior to the read or write to this data register. note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. since this is not a physical register, the ?default? value is the same as the default value of the register pointed to by index. sata controller registers (d31:f2) 512 intel ? ich8 family datasheet 12.4 ahci registers (d31:f2) (intel ? ich8r, ich8dh, ich8do, and ich8m-e only) note: these registers are ahci-specific and availabl e when the ich8 is properly configured. the serial ata status, control, and error re gisters are special exceptions and may be accessed on all ich8 components if properly configured. see section 12.1.31 for details. the memory mapped registers within the sata controller exist in non-cacheable memory space. additionally, locked accesses ar e not supported. if software attempts to perform locked transactions to the registers, indeterminate results may occur. register accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte alignment boundary. the registers are broken into two sections ? generic host control and port control. the port control registers are the same for all ports, and there are as many registers banks as there are ports. table 124. ahci register address map abar + offset mnemonic register 00?1fh ghc generic host control 20h?ffh ? reserved 100h?17fh p0pcr port 0 port control registers 180h?1ffh p1pcr port 1 port control registers 200h?27fh p2pcr port 2 port control registers 280h?2ffh p3pcr port 3 port control re gisters (desktop only) registers are not available and so ftware must not read or write registers. (mobile only) 300h?37fh p4pcr port 4 port control re gisters (desktop only) registers are not available and so ftware must not read or write registers. (mobile only) 380h?3ffh p5pcr port 5 port control re gisters (desktop only) registers are not available and so ftware must not read or write registers. (mobile only) intel ? ich8 family datasheet 513 sata controller registers (d31:f2) 12.4.1 ahci generic host co ntrol registers (d31:f2) 12.4.1.1 cap?host capabilities register (d31:f2) address offset: abar + 00h?03h attribute: r/wo, ro default value: ff22ffc2h (desktop) size: 32 bits de127f03h (mobile) all bits in this register that are r/wo are reset only by pltrst#. table 125. generic host cont roller register address map abar + offset mnemonic register default type 00?03 cap host capabilities de227f03h (desktop) de127f03h (mobile) r/wo, ro 04?07 ghc global ich8 control 00000000h r/w 08?0bh is interrupt status 00000000h r/wc, ro 0ch?0fh pi ports implemented 00000000h r/wo, ro 10h-13h vs ahci version 00010100h ro bit description 31 supports 64-bit addressing (s64a) ? ro. indicates that the sata controller can access 64-bit data structures . the 32-bit upper bits of the port dma descriptor, the prd base, and each prd entry are read/write. 30 supports command queue acceleration (scqa) ? ro. hardwired to 1 to indicate that the sata co ntroller supports sata command queuing via the dma setup fis. the intel? ich8 handles dma setup fises natively, and can handle auto-activate optimization through that fis. 29 supports snotification register (ssntf): ? ro. the ich8 sata controller does not support the snotif ication register. 28 supports interlock switch (sis) ? r/wo. indicates whether the sata controller supports interlock switches on its ports for use in hot-plug operations. this value is loaded by platform bios prior to os initialization. if this bit is set, bios must also map the satagp pins to the sata controller through gpio space. 27 supports staggered spin-up (sss) ? r/wo. indicates whether the sata controller supports staggered spin-up on its ports, for use in balancing power spikes. this value is loaded by platform bios prior to os initialization. 0 = staggered spin-up not supported. 1 = staggered spin-up supported. 26 supports aggressive link power management (salp) ? r/wo. 0 = software shall treat the pxcmd.alpe and pxcmd.asp bits as reserved. 1 = the sata controller supports auto-gener ating link requests to the partial or slumber states when there ar e no commands to process. 25 supports activity led (sal) ? ro. indicates that the sata controller supports a single output pin (sataled#) which indicates activity. sata controller registers (d31:f2) 514 intel ? ich8 family datasheet 24 supports command list override (sclo) ? r/wo. when set to '1', indicates that the hba supports the pxcmd.clo bit and it's associated func tion. when cleared to '0', the hba is not capable of clearing the bsy and drq bits in the status register in order to issue a software reset if these bits are still set from a previous operation. 23:20 interface speed support (iss) ? r/wo. indicates the maximum speed the sata controller can support on its ports. 2h =3.0 gb/s. 19 supports non-zero dma offsets (snzo) ? ro . reserved, as per the ahci revision 1.0 specification 18 supports ahci mode only (sam) ? ro. the sata controller may optionally support ahci access mechanism only. 0 = sata controller supports both ide and ahci modes 1 = sata controller supports ahci mode only 17 supports port multiplier (pms) ? r/wo. ich8 does not support port multiplier. bios/sw shall write this bit to ?0? during ahci initialization. 16 supports port multiplier fis based switch ing (pmfs) ? ro. reserved, as per the ahci revision 1.0 specification. note: port multiplier not supported by ich8. 15 pio multiple drq block (pmd) ? r/wo. the sata controller supports pio multiple drq command block 14 slumber state capable (ssc) ? ro. the sata controller supports the slumber state. 13 partial state capable (psc) ? ro. the sa ta controller supports the partial state. 12:8 number of command slots (ncs) ? ro. hardwi red to 1fh to indicate support for 32 slots. 7 command completion coalescing supported (cccs) ? r/wo. 0 = command completion coalescing not supported 1 = command completion coalescing supported 6 enclosure management supported (ems) ? r/wo. 0 = enclosure management not supported 1 = enclosure management supported 5 (ich8r, ich8do, ich8dh only) supports external sata (sxs) ? r/wo. 0 = external sata is not supported on any ports 1 = external sata is supported on one or more ports when set, software can examine each sa ta port?s command register (pxcmd) to determine which port is routed externally. 5 reserved 5 (ich8 base and ich8 mobile only) reserved 4:0 number of ports (nps) ? ro. hardwired to 5h to indicate support for 6 ports. note that the number of ports indi cated in this fiel d may be more than the number of ports indicated in the pi (abar + 0ch) register. bit description intel ? ich8 family datasheet 515 sata controller registers (d31:f2) 12.4.1.2 ghc?global ich8 control register (d31:f2) address offset: abar + 04h?07h attribute: r/w default value: 00000000h size: 32 bits bit description 31 ahci enable (ae) ? r/w. when set, indicates that an ahci driver is loaded and the controller will be talked to via ahci mech anisms. this can be us ed by an ich8 that supports both legacy mechanisms (such as sff-8038i) and ahci to know when the controller will not be talked to as legacy. 0 = software will only talk to the ich8 using legacy mechanisms. 1 = software will only talk to the ich8 using ahci. the ich8 will not have to allow command processing via both ahci and legacy mechanisms. software shall set this bit to 1 before acce ssing other ahci registers. 30:3 reserved 2 msi revert to single message (mrsm) ? ro: when set to 1 by hardware, indicates that the host controller requ ested more than one msi vector but has reverted to using the first vector only. when this bit is cleare d to '0', the hba has no t reverted to single msi mode (i.e. hardware is already in si ngle msi mode, software has allocated the number of messages requested, or hardware is sharing interrupt vectors if mc.mme < mc.mmc). "mc.msie = '1' (msi is enabled) "mc.mmc > 0 (multiple messages requested) "mc.mme > 0 (more than one message allocated) "mc.mme != mc.mmc (messages alloca ted not equal to number requested) when this bit is set to '1', single msi mode operation is in use and software is responsible for clearing bits in th e is register to clear interrupts. this bit shall be cleared to '0' by hardware when any of the four conditions stated is false. this bit is also cleared to '0' when mc.msie = '1' and mc.mme = 0h. in this case, the hardware has been programmed to use si ngle msi mode, and is not "reverting" to that mode. for ich8, the hba shall always revert to si ngle msi mode when the number of vectors allocated by the host is less than the number requested. 1 interrupt enable (ie) ? r/w. this global bit enab les interrupts from the ich8. 0 = all interrupt sources fr om all ports are disabled. 1 = interrupts are allowed from the ahci controller. 0 hba reset (hr) ? r/w. resets ich8 ahci controller. 0 = no effect 1 = when set by sw, this bit causes an intern al reset of the ich8 ahci controller. all state machines that relate to data transfers and queuing return to an idle condition, and all ports are re-initialized via comreset. note: for further details, cons ult section 12.3.3 of the serial ata advanced host controller interface specification. sata controller registers (d31:f2) 516 intel ? ich8 family datasheet 12.4.1.3 is?interrupt status register (d31:f2) address offset: abar + 08h ? 0bh attribute: r/wc, ro default value: 00000000h size: 32 bits this register indicates which of the ports with in the controller have an interrupt pending and require service. bit description 31:7 reserved. returns 0. 6 (mobile only) reserved. returns 0. 6 (desktop only) interrupt pending status port[6] (ips[6]) ? r/wc . 0 = no interrupt pending. 1 = a command completion coalescing interrupt has been generated. 5 (mobile only) reserved. returns 0. 5 (desktop only) interrupt pending status port[5] (ips[5]) ? r/wc . 0 = no interrupt pending. 1 = port 5 has an interrupt pending. softwa re can use this info rmation to determine which ports require serv ice after an interrupt. 4 (mobile only) reserved. returns 0. 4 (desktop only) interrupt pending status port[4] (ips[4]) ? r/wc . 0 = no interrupt pending. 1 = port 4 has an interrupt pending. softwa re can use this info rmation to determine which ports require serv ice after an interrupt. 3 (mobile only) reserved. returns 0. 3 (desktop only) interrupt pending status port[3] (ips[3]) ? r/wc . 0 = no interrupt pending. 1 = port 3 has an interrupt pending. softwa re can use this info rmation to determine which ports require serv ice after an interrupt. 2 interrupt pending status port[2] (ips[2]) ? r/wc 0 = no interrupt pending. 1 = port 2 has an interrupt pending. softwa re can use this info rmation to determine which ports require serv ice after an interrupt. 1 interrupt pending status port[1] (ips[1]) ? r/wc . 0 = no interrupt pending. 1 = port 1has an interrupt pending. softwa re can use this info rmation to determine which ports require serv ice after an interrupt. 0 interrupt pending status port[0] (ips[0]) ? r/wc . 0 = no interrupt pending. 1 = port 0 has an interrupt pending. softwa re can use this info rmation to determine which ports require serv ice after an interrupt. intel ? ich8 family datasheet 517 sata controller registers (d31:f2) 12.4.1.4 pi?ports implemented register (d31:f2) address offset: abar + 0ch?0fh attribute: r/wo, ro default value: 00000000h size: 32 bits this register indicates which ports are exposed to the ich8. it is loaded by platform bios. it indicates which ports that the device supports are available for software to use. for ports that are not available, software must not read or write to registers within that port. bit description 31:6 reserved. returns 0. 5 (desktop only) ports implemented port 5 (pi5) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 5 (mobile only) ports implemented port 5 (pi5) ? ro. 0 = the port is not implemented. 4 (desktop only) ports implemented port 4 (pi4) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 4 (mobile only) ports implemented port 4 (pi4) ? ro. 0 = the port is not implemented. 3 (desktop only) ports implemented port 3 (pi3) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 3 (mobile only) ports implemented port 3 (pi3) ? ro. 0 = the port is not implemented. 2 ports implemented port 2 (pi2) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 1 ports implemented port 1 (pi1) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 0 ports implemented port 0 (pi0) ? r/wo . 0 = the port is not implemented. 1 = the port is implemented. sata controller registers (d31:f2) 518 intel ? ich8 family datasheet 12.4.1.5 vs?ahci version (d31:f2) address offset: abar + 10h?13h attribute: ro default value: 00010100h size: 32 bits this register indicates the major and minor ve rsion of the ahci specification. it is bcd encoded. the upper two bytes represent th e major version number, and the lower two bytes represent the minor version numbe r. example: version 3.12 would be represented as 00030102h. the current version of the specification is 1.10 (00010100h). 12.4.1.6 ccc_ctl?command completion coalescing control register (d31:f2) address offset: abar + 14h?17h attribute: r/w, ro default value: 00000000h size: 32 bits this register is used to configure the command coalescing feature. this register is reserved if command coalescing is not supported (cap_cccs = ?0?). bit description 31:16 major version number (mjr) ? ro. indicates the major version is 1 15:0 minor version number (mnr) ? ro. indicates the minor version is 10. bit description 31:16 timeout value (tv) ? r/w. the timeout value is specified in 10 microsecond intervals. hbaccc_timer is loaded with th is timeout value. hbaccc_timer is only decremented when commands are outstanding on the selected ports. the hba will signal a ccc interrupt when hbaccc_t imer has decremented to ?0?. the hbaccc_timer is reset to the timeout value on the assertion of each ccc interrupt. a timeout value of?0? is invalid. 15:8 command completions (cc) ? r/w. specifies the number of command completions that are necessary to cause a ccc interru pt. the hba has an internal command completion counte r, hbaccc_commandscomplete. hbaccc_commandscomplete is incremented by one each time a selected port has a command completion. when hbaccc_command scomplete is equal to the command completions value, a ccc interrupt is sign aled. the internal command completion counter is reset to ?0? on the assertion of each ccc interrupt. 7:3 interrupt (int) ? ro. specifies the interrupt used by the ccc feature. this interrupt must be marked as unused in the ahci ports implemented memory register by the corresponding bit being set to ?0?. thus, the ccc_interrupt corresponds to the interrupt for an unimplemente d port on the controller. when a ccc interrupt occurs, the is[int] bit shall be asserted to ?1? rega rdless of whether pirq interrupt or msi is used. for desktop int is always 6. note that in msi, cc interru pt may share an interrupt ve ctor with other ports. for example, if the number of message allocated is 4, then ccc inte rrupt share interrupt vector 3 along with port 3, 4, and 5 but is[6] shall get set. 2:1 reserved 0 enable (en) ? r/w . 0 = the command completion coalescing feat ure is disabled and no ccc interrupts are generated 1 = the command completion coalescing feature is enabled and ccc interrupts may be generated based on timeout or command completion conditions. software shall only change the contents of the tv and cc fields when en is cleared to '0'. on transition of this bit from '0' to '1', any updated values for the tv and cc fields shall take effect. intel ? ich8 family datasheet 519 sata controller registers (d31:f2) 12.4.1.7 ccc_ports?command completion coalescing ports register (d31:f2) address offset: abar + 18h?1ch attribute: r/w default value: 00000000h size: 32 bits this register is used to specify the ports that are coalesced as part of the ccc feature when ccc_ctl.en = ?1?. this register is reserved if command coalescing is not supported (cap_cccs = ?0?). 12.4.1.8 em_loc?enclosure management location register (d31:f2) address offset: abar + 1ch?1fh attribute: ro default value: 01000002h size: 32 bits this register identifies the location and size of the enclosure management message buffer. this register is reserved if en closure management is not supported (i.e. cap.ems = 0). bit description 31:0 ports (prt) ? r/w. 0 = the port is not part of the co mmand completion coalescing feature. 1 = the corresponding port is part of th e command completion coalescing feature. bits set to ?1? in this register must also have the corresponding bit set to ?1? in the ports implemented register. bits set to 1 in this register must also have th e corresponding bit set to 1 in the ports implemented register. an updated value for this field shall take effect within one timer increment (1 millisecond). bit description 31:16 offset (ofst) ? ro. the offset of the message buffer in dwords from the beginning of the abar. 15:0 buffer size (sz) ? ro. specifies the size of the transmit message buffer area in dwords. the ich8 sata controller only supports tr ansmit buffer. a value of 0 is invalid. sata controller registers (d31:f2) 520 intel ? ich8 family datasheet 12.4.1.9 em_ctl?enclosure manage ment control register (d31:f2) address offset: abar + 20h?23h attribute: r/w, r/wo, ro default value: 07010000h size: 32 bits this register is used to control and obtain status for the enclosure management interface. this register includes informatio n on the attributes of the implementation, enclosure management messages supported, the status of the interface, whether any message are pending, and is used to initiate sending messages. this register is reserved if enclosure management is not supported (cap_ems = ?0?). bit description 31:27 reserved 26 activity led hardware driven (attr.alhd) ? r/wo. 1 = the sata controller drives the activity led for the led message type in hardware and does not utilize software for this led. the host controller does not begin transmitting the hardware based activity signal until after software has written ctl.tm=1 after a reset condition. 25 transmit only (attr.xmt) ? ro. 0 = the sata controller supports tr ansmitting and re ceiving messages. 1 = the sata controller only supports transmitting messages and does not support receiving messages. 24 single message buffer (attr.smb) ? ro. 0 = there are separate receiv e and transmit buffers such that unsolicited messages could be supported. 1 = the sata controller has one message bu ffer that is shared for messages to transmit and messages received. unsolici ted receive messages are not supported and it is software?s responsibility to manage access to this buffer. 23:20 reserved 19 sgpio enclosure management messages (supp.sgpio): ? ro. 1 = the sata controller supports the sg pio register interface message type. 18 ses-2 enclosure management messages (supp.ses2): ? ro. 1 = the sata controller suppo rts the ses-2 message type. 17 saf-te enclosure management messages (supp.safte): ? ro. 1 = the sata controller suppo rts the saf-te message type. 16 led message types (supp.led): ? ro. 1 = the sata controller su pports the led message type. 15:10 reserved 9 reset (rst) ? r/wo. 0 = a write of ?0? to this bit by software will have no effect. 1 = when set by software, the sata controll er shall reset all enclosure management message logic and take all appropriate rese t actions to ensure messages can be transmitted / received after the reset. after the sata contro ller completes the reset operation, the sa ta controller shall set the value to ?0?. 8 transmit message (ctl.tm) ? r/wo. 0 = a write of ?0? to this bit by software will have no effect. 1 = when set by software, the sata controll er shall transmit th e message contained in the message buffer. when the message is completely sent, the sata controller shall set the value to 0. software shall not change the contents of the message buffer while ctl.tm is set to 1. 7:1 reserved 0 message received (sts.mr) ? ro. message received is not supported in ich8. intel ? ich8 family datasheet 521 sata controller registers (d31:f2) 12.4.2 port registers (d31:f2) table 126. port [3:0] dma register address map (sheet 1 of 3) abar + offset mnemonic register 100h?103h p0clb port 0 command list base address 104h?107h p0clbu port 0 command list base address upper 32-bits 108h?10bh p0fb port 0 fis base address 10ch?10fh p0fbu port 0 fis base address upper 32-bits 110h?113h p0is port 0 interrupt status 114h?117h p0ie port 0 interrupt enable 118h?11bh p0cmd port 0 command 11ch?11fh ? reserved 120h?123h p0tfd port 0 task file data 124h?127h p0sig port 0 signature 128h?12bh p0ssts port 0 serial ata status 12ch?12fh p0sctl port 0 serial ata control 130h?133h p0serr port 0 serial ata error 134h?137h p0sact port 0 serial ata active 138h?13bh p0ci port 0 command issue 13ch?17fh ? reserved 180h?1ffh (mobile only) ? reserved registers are not available and software must not read from or write to registers. 180h?183h p1clb port 1 command list base address 184h?187h p1clbu port 1 command list base address upper 32-bits 188h?18bh p1fb port 1 fis base address 18ch?18fh p1fbu port 1 fis base address upper 32-bits 190h?193h p1is port 1 interrupt status 194h?197h p1ie port 1 interrupt enable 198h?19bh p1cmd port 1 command 19ch?19fh ? reserved 1a0h?1a3h p1tfd port 1 task file data 1a4h?1a7h p1sig port 1 signature 1a8h?1abh p1ssts port 1 serial ata status 1ach?1afh p1sctl port 1 serial ata control 1b0h?1b3h p1serr port 1 serial ata error 1b4h?1b7h p1sact port 1 serial ata active 1b8h?1bbh p1ci port 1 command issue 1bch?1ffh ? reserved 200h?203h p2clb port 2 command list base address 204h?207h p2clbu port 2 command list base address upper 32-bits 208h?20bh p2fb port 2 fis base address sata controller registers (d31:f2) 522 intel ? ich8 family datasheet 20ch?20fh p2fbu port 2 fis base address upper 32-bits 210h?213h p2is port 2 interrupt status 214h?217h p2ie port 2 interrupt enable 218h?21bh p2cmd port 2 command 21ch?21fh ? reserved 220h?223h p2tfd port 2 task file data 224h?227h p2sig port 2 signature 228h?22bh p2ssts port 2 serial ata status 22ch?22fh p2sctl port 2 serial ata control 230h?233h p2serr port 2 serial ata error 234h?237h p2sact port 2 serial ata active 238h?23bh p2ci port 2 command issue 23ch?27fh ? reserved 280h?2ffh (mobile only) ? reserved registers are not available and software must not read from or write to registers. 280h?283h p3clb port 3 command list base address 284h?287h p3clbu port 3 command list base address upper 32-bits 288h?28bh p3fb port 3 fis base address 28ch?28fh p3fbu port 3 fis base address upper 32-bits 290h?293h p3is port 3 interrupt status 294h?297h p3ie port 3 interrupt enable 298h?29bh p3cmd port 3 command 29ch?29fh ? reserved 2a0h?2a3h p3tfd port 3 task file data 2a4h?2a7h p3sig port 3 signature 2a8h?2abh p3ssts port 3 serial ata status 2ach?2afh p3sctl port 3 serial ata control 2b0h?2b3h p3serr port 3 serial ata error 2b4h?2b7h p3sact port 3 serial ata active 2b8h?2bbh p3ci port 3 command issue 2bch?2ffh ? reserved 300h?303h p2clb port 2 command list base address 304h?307h p2clbu port 2 command list base address upper 32-bits 308h?30bh p2fb port 2 fis base address 30ch?30fh p4fbu port 4 fis base address upper 32-bits 310h?313h p4is port 4 interrupt status 314h?317h p4ie port 4 interrupt enable 318h?31bh p4cmd port 4 command 31ch?31fh ? reserved table 126. port [3:0] dma register address map (sheet 2 of 3) abar + offset mnemonic register intel ? ich8 family datasheet 523 sata controller registers (d31:f2) 320h?323h p4tfd port 4 task file data 324h?327h p4sig port 4 signature 328h?32bh p4ssts port 4 serial ata status 32ch?32fh p4sctl port 4 serial ata control 330h?333h p4serr port 4 serial ata error 334h?337h p4sact port 4 serial ata active 338h?33bh p4ci port 4 command issue 33ch?37fh ? reserved 380h?3ffh (mobile only) ? reserved registers are not available and software must not read from or write to registers. 380h?383h p5clb port 5 command list base address 384h?387h p5clbu port 5 command list base address upper 32-bits 388h?38bh p5fb port 5 fis base address 38ch?38fh p5fbu port 5 fis base address upper 32-bits 390h?393h p5is port 5 interrupt status 394h?397h p5ie port 5 interrupt enable 398h?39bh p5cmd port 5 command 39ch?39fh ? reserved 3a0h?3a3h p5tfd port 5 task file data 3a4h?3a7h p5sig port 5 signature 3a8h?3abh p5ssts port 5 serial ata status 3ach?3afh p5sctl port 5 serial ata control 3b0h?3b3h p5serr port 5 serial ata error 3b4h?3b7h p5sact port 5 serial ata active 3b8h?3bbh p5ci port 5 command issue 3bch?3ffh ? reserved table 126. port [3:0] dma register address map (sheet 3 of 3) abar + offset mnemonic register sata controller registers (d31:f2) 524 intel ? ich8 family datasheet 12.4.2.1 pxclb?port [ 5 :0] command list base address register (d31:f2) address offset: port 0: abar + 100h attribute: r/w, ro port 1: abar + 180h port 2: abar + 200h port 3: abar + 280h (desktop only) port 4: abar + 300h (desktop only) port 5: abar + 380h (desktop only) default value: undefined size: 32 bits 12.4.2.2 pxclbu?port [5:0] comm and list base address upper 32-bits register (d31:f2) address offset: port 0: abar + 104h attribute: r/w port 1: abar + 184h port 2: abar + 204h port 3: abar + 284h (desktop only) port 4: abar + 304h (desktop only) port 5: abar + 384h (desktop only) default value: undefined size: 32 bits bit description 31:10 command list base address (clb) ? r/w . indicates the 32-bit base for the command list for this port. this base is used when fetching commands to execute. the structure pointed to by this address range is 1 kb in length. this address must be 1-kb aligned as indicated by bi ts 31:10 being read/write. note that these bits are not reset on a hba reset. 9:0 reserved ? ro bit description 31:0 command list base address upper (clbu) ? r/w . indicates the upper 32-bits for the command list base address for this po rt. this base is us ed when fetching commands to execute. note that these bits are not reset on a hba reset. intel ? ich8 family datasheet 525 sata controller registers (d31:f2) 12.4.2.3 pxfb?port [ 5 :0] fis base address register (d31:f2) address offset: port 0: abar + 108h attribute: r/w, ro port 1: abar + 188h port 2: abar + 208h port 3: abar + 284h (desktop only) port 4: abar + 304h (desktop only) port 5: abar + 384h (desktop only) default value: undefined size: 32 bits 12.4.2.4 pxfbu?port [5: 0] fis base address upper 32-bits register (d31:f2) address offset: port 0: abar + 10ch attribute: r/w port 1: abar + 18ch port 2: abar + 20ch port 3: abar + 28ch port 4: abar + 30ch port 5: abar + 38ch default value: undefined size: 32 bits bit description 31:8 fis base address (fb) ? r/w . indicates the 32-bit base for received fises. the structure pointed to by this address range is 256 bytes in length. this address must be 256-byte aligned, as indicated by bits 31:3 being read/write. note that these bits are not reset on a hba reset. 7:0 reserved ? ro bit description 31:3 command list base address upper (clbu) ? r/w . indicates the upper 32-bits for the received fis base for this port. note that these bits are not reset on a hba reset. 2:0 reserved sata controller registers (d31:f2) 526 intel ? ich8 family datasheet 12.4.2.5 pxis?port [5 :0] interrupt status register (d31:f2) address offset: port 0: abar + 110h attribute: r/wc, ro port 1: abar + 190h port 2: abar + 210h port 3: abar + 290h (desktop only) port 4: abar + 310h (desktop only) port 5: abar + 390h (desktop only) default value: 00000000h size: 32 bits bit description 31 cold port detect status (cpds) ? ro . cold presence detect is not supported. 30 task file error status (tfes) ? r/wc. this bit is set whenever the status register is updated by the device and the e rror bit (pxtfd.bit 0) is set. 29 host bus fatal error status (hbfs) ? r/wc . indicates that the intel ? ich8 encountered an error that it cannot recover from due to a ba d software pointer. in pci, such an indication would be a target or master abort. 28 host bus data error status (hbds) ? r/wc. indicates that the ich8 encountered a data error (uncorrectable ecc / parity) when reading from or writing to system memory. 27 interface fatal error status (ifs) ? r/wc . indicates that the ich8 encountered an error on the sata interface whic h caused the transfer to stop. 26 interface non-fatal error status (infs) ? r/wc. indicates that the ich8 encountered an error on the sata interfa ce but was able to continue operation. 25 reserved 24 overflow status (ofs) ? r/wc . indicates that the ich8 received more bytes from a device than was specified in the prd table for the command. 23 incorrect port multiplier status (ipms) ? r/wc. indicates that the ich8 received a fis from a device whose port multiplier field did not match what was expected. note: port multiplier not supported by ich8. 22 phyrdy change status (prcs) ? ro. when set to one indicates the internal phyrdy signal changed state. this bi t reflects the state of pxserr .diag.n. unlike most of the other bits in the register, th is bit is ro and is only cl eared when pxserr.diag.n is cleared. note that the internal phyrdy signal also transitions when the port interface enters partial or slumber power management states . partial and slumber must be disabled when surprise removal notification is desi red, otherwise the po wer management state transitions will appear as fals e insertion and removal events. 21:8 reserved 7 device interlock status (dis) ? r/wc. when set, indicates that a platform interlock switch has been opened or closed, which may lead to a change in the connection state of the device. this bit is only valid in systems that support an interlock switch (cap.sis [abar+00:bit 28] set). for systems that do not suppo rt an interlock switch, th is bit will always be 0. 6 port connect change status (pcs) ? ro . this bit reflects the state of pxserr.diag.x. (abar+130h/1d0h/230h/2d0h, bit 26) unlike other bits in this register, this bit is only cleare d when pxserr.diag.x is cleared. 0 = no change in curre nt connect status. 1 = change in current connect status. 5 descriptor processed (dps) ? r/wc . a prd with the i bit set has transferred all its data. intel ? ich8 family datasheet 527 sata controller registers (d31:f2) 12.4.2.6 pxie?port [ 5 :0] interrupt enable register (d31:f2) address offset: port 0: abar + 114h attribute: r/w, ro port 1: abar + 194h port 2: abar + 214h port 3: abar + 294h (desktop only) port 4: abar + 314h (desktop only) port 5: abar + 394h (desktop only) default value: 00000000h size: 32 bits this register enables and disables the re porting of the corresponding interrupt to system software. when a bit is set (?1?) an d the corresponding interrupt condition is active, then an interrupt is generated. inte rrupt sources that are disabled (?0?) are still reflected in the status registers. 4 unknown fis interrupt (ufs) ? ro. when set to ?1? indicates that an unknown fis was received and has been copied into syst em memory. this bit is cleared to ?0? by software clearing the pxserr.diag.f bit to ?0?. note that this bit does not directly reflect the pxserr.diag.f bit. pxserr.diag.f is set immediately when an unknown fis is detected, whereas this bit is set wh en the fis is posted to memory. software should wait to act on an unknown fis until this bit is set to ?1? or the two bits may become out of sync. 3 set device bits interrupt (sdbs) ? r/wc . a set device bits fis has been received with the i bit set and has been copied into system memory. 2 dma setup fis interrupt (dss) ? r/wc . a dma setup fis has been received with the i bit set and has been copied into system memory. 1 pio setup fis interrupt (pss) ? r/wc . a pio setup fis has been received with the i bit set, it has been copied into system memory, and the data related to that fis has been transferred. 0 device to host register fis interrupt (dhrs) ? r/wc . a d2h register fis has been received with the i bit set, and has been copied into system memory. bit description bit description 31 cold presence detect enab le (cpde) ? ro. cold presence detect is not supported. 30 task file error enable (tfee) ? r/w . when set, and ghc.ie and pxtfd.sts.err (due to a reception of the error register from a received fis) are set, the intel ? ich8 will generate an interrupt. 29 host bus fatal error enable (hbfe) ? r/w . when set, and ghc.ie and pxs.hbfs are set, the ich8 will generate an interrupt. 28 host bus data error enable (hbde) ? r/w . when set, and ghc.ie and pxs.hbds are set, the ich8 will generate an interrupt. 27 host bus data error enable (hbde) ? r/w. when set, ghc.ie is set, and pxis.hbds is set, the ich8 will generate an interrupt. 26 interface non-fatal error enable (infe) ? r/w. when set, ghc.ie is set, and pxis.infs is set, the ich8 will generate an interrupt. 25 reserved - should be written as 0 24 overflow error enable (ofe) ? r/w. when set, and ghc. ie and pxs.ofs are set, the ich8 will generate an interrupt. sata controller registers (d31:f2) 528 intel ? ich8 family datasheet 23 incorrect port multiplier enable (ipme) ? r/w. when set, and ghc.ie and pxis.ipms are set, the ich8 will generate an interrupt. note: should be written as 0. port mu ltiplier not supported by ich8. 22 phyrdy change interrupt enable (prce) ? r/w. when set, and ghc.ie is set, and pxis.prcs is set, the ich8 shall generate an interrupt. 21:8 reserved - should be written as 0 7 device interlock enable (die) ? r/w. when set, and pxis.d is is set, the ich8 will generate an interrupt. for systems that do not suppo rt an interlock switch, this bit shall be a read-only 0. 6 port change interrupt enable (pce) ? r/w . when set, and ghc.ie and pxs.pcs are set, the ich8 will generate an interrupt. 5 descriptor processed interrupt enable (dpe) ? r/w. when set, and ghc.ie and pxs.dps are set, the ich8 will generate an interrupt 4 unknown fis interrupt enable (ufie) ? r/w . when set, and ghc. ie is set and an unknown fis is received, the ich8 will generate this interrupt. 3 set device bits fis interrupt enable (sdbe) ? r/w. when set, and ghc.ie and pxs.sdbs are set, the ich8 will generate an interrupt. 2 dma setup fis interrupt enable (dse) ? r/w. when set, and ghc.ie and pxs.dss are set, the ich8 will generate an interrupt. 1 pio setup fis interrupt enable (pse) ? r/w . when set, and ghc.ie and pxs.pss are set, the ich8 will generate an interrupt. 0 device to host re gister fis interrupt enable (dhre) ? r/w. when set, and ghc.ie and pxs.dhrs are set, the ich8 will generate an interrupt. bit description intel ? ich8 family datasheet 529 sata controller registers (d31:f2) 12.4.2.7 pxcmd?port [5:0] command register (d31:f2) address offset: port 0: abar + 118h attribute: r/w, ro, r/wo port 1: abar + 198h port 2: abar + 218h port 3: abar + 298h (desktop only) port 4: abar + 318h (desktop only) port 5: abar + 398h (desktop only) default value: 0000w00wh size: 32 bits where w = 00?0b (for?, see bit description) bit description 31:28 interface communication control (icc) ? r/w. this is a four bit field which can be used to control reset and power states of the inte rface. writes to this field will cause actions on the interface, either as primitives or an oob sequence, and the resulting status of the interface will be reported in the pxssts register (address offset port 0:abar+124h, port 1: abar+1a4h, port 2: abar+224h, port 3: abar+2a4h, port 4: ab ar+224h, port 5: abar+2a4h). when system software writes a non-rese rved value other than no-op (0h), the ich8 will perform the action and upda te this field back to idle (0h). if software writes to this field to change the state to a state the link is already in (e.g. interface is in the ac tive state and a request is made to go to the active state), the ich8 will take no acti on and return this field to idle. note: when the alpe bit (bit 26) is set, then this register should not be set to 02h or 06h. 27 aggressive slumber / partial (asp) ? r/w. when set, and the alpe bit (bit 26) is set, the ich8 shall aggressively enter the slumber state when it clears the pxci register and the pxsact register is cl eared. when cleared, and the alpe bit is set, the ich8 will aggressively enter th e partial state when it clears the pxci register and the pxsact regist er is cleared. if cap.salp is cleared to '0', software shall treat this bit as reserved. 26 aggressive link power ma nagement enable (alpe) ? r/w. when set, the ich8 will aggressively enter a lower link power state (partial or slumber) based upon the setting of the asp bit (bit 27). 25 drive led on atapi enable (dlae) ? r/w. when set, the ich8 will drive the led pin active for atapi commands (pxc lb[chz.a] set) in addition to ata commands. when cleared, th e ich8 will only drive the led pin active for ata commands. see section 5.16.5 for details on the activity led. value definition fh?7h reserved 6h slumber: this will cause the intel ? ich8 to request a transition of the interface to the slumber stat e. the sata device may reject the request and the interface will remain in its current state 5h?3h reserved 2h partial: this will cause the ich8 to request a transition of the interface to the partial state. the sata device may reject the request and the interface will remain in its current state. 1h active: this will cause the ich8 to request a transition of the interface into the active 0h no-op / idle: when software read s this value, it indicates the ich8 is not in the process of changing the interface state or sending a device reset, and a new link command may be issued. sata controller registers (d31:f2) 530 intel ? ich8 family datasheet 24 device is atapi (atapi) ? r/w. when set, the connected device is an atapi device. this bit is used by the ich8 to control whether or not to generate the desktop led when commands are active. see section 5.16.5 for details on the activity led. 23:22 reserved 21 (ich8r, ich8do, ich8dh only) external sata port (esp) ? r/wo. 0 = this port supports inte rnal sata devices only. 1 = this port will be used with an extern al sata device. when set, cap.sxs must also be set. 21 reserved 21 (ich8 base, and ich8 mobile only) reserved 20 reserved 19 interlock switch attached to port (isp) ? r/wo. when interlock switches are supported in the platform (cap.sis [a bar+00h:bit 28] set), this indicates whether this particular port has an interlock switch attached. this bit can be used by system software to enable such feat ures as aggressive power management, as disconnects can always be detected regardless of phy state with an interlock switch. when this bit is set, it is expected that hpcp (bit 18) in this register is also set. the ich8 takes no action on the state of th is bit ? it is for system software only. for example, if this bit is cleared, and an interlock switch toggles, the ich8 still treats it as a proper interlock switch event. note that these bits are not reset on a hba reset. 18 hot plug capable port (hpcp) ? r/wo. 0 = port is not capable of hot-plug. 1 = port is hot-plug capable. this indicates whether the pl atform exposes this port to a device which can be hot-plugged. sata by definition is ho t-pluggable, but not all platforms are constructed to allow the device to be remo ved (it may be screwe d into the chassis, for example). this bit can be used by syst em software to indi cate a feature such as ?eject device? to the end-user. the ich8 takes no action on the state of this bit - it is for system software only. for example, if this bit is cleared, and a hot-plug event occurs, the ich8 still treats it as a proper hot-plug event. note that these bits are not reset on a hba reset. 17 port multiplier attached (pma) ? ro / r/w. when this bit is set, a port multiplier is attached to th e ich8 for this port. when cl eared, a port multiplier is not attached to this port. this bit is ro 0 when cap.pms (offset abar+00h:bit 17) = 0 and r/w when cap.pms = 1. note: port multiplier not supported by ich8. 16 port multiplier fis based switching en able (pmfse) ? ro. the ich8 does not support fis-based switching. note: port multiplier not supported by ich8. 15 controller running (cr) ? ro. when this bit is set, the dma engines for a port are running. see section 5.2.2 of the serial ata ahci specification for details on when this bit is set and cleared by the ich8. 14 fis receive running (fr) ? ro. when set, the fis receive dma engine for the port is running. see section 12.2.2 of the serial ata ahci specification for details on when this bit is set and cleared by the ich8. bit description intel ? ich8 family datasheet 531 sata controller registers (d31:f2) 13 interlock switch state (iss) ? ro. for systems that support interlock switches (via cap.sis [abar+00h:bit 28]), if an interlock switch exists on this port (via isp in this register), this bit indicates the current state of the interlock switch. a 0 indicates the switch is closed, and a 1 indicates the switch is opened. for systems that do not support interlock sw itches, or if an inte rlock switch is not attached to this port , this bit reports 0. 12:8 current command slot (ccs) ? ro . indicates the current command slot the ich8 is processing. this field is valid when the st bit is set in this register, and is constantly updated by the ich8. this fiel d can be updated as soon as the ich8 recognizes an active command slot, or at some point soon af ter when it begins processing the command. this field is used by soft ware to determine the current command issue location of the ich8. in queued mode, software shall no t use this field, as its value does not represent the current command being execut ed. software shall only use pxci and pxsact when running queued commands. 7:5 reserved 4 fis receive enable (fre) ? r/w. when set, the ich8 may post received fises into the fis receive area pointed to by pxfb (abar+108h/188h/208h/288h) and pxfbu (abar+10ch/18ch/20ch/28ch). when cleared, received fises are not accepted by the ich8, except for the firs t d2h (device-to-host) register fis after the initialization sequence. system software must not set this bit unt il pxfb (pxfbu) have been programmed with a valid pointer to the fis receive ar ea, and if software wishes to move the base, this bit must first be cleared, and software must wa it for the fr bit (bit 14) in this register to be cleared. 3 command list override (clo) ? r/w. setting this bit to '1' causes pxtfd.sts.bsy and pxtfd.sts.drq to be cleared to '0'. this allows a software reset to be transmitted to the device regardless of whether the bsy and drq bits are still set in the pxtfd.sts register. the hba sets this bit to '0' when pxtfd.sts.bsy and pxtfd.sts.drq have been cleared to '0'. a write to this register with a value of '0' shall have no effect. this bit shall only be set to '1' immediat ely prior to setting the pxcmd.st bit to 1 from a previous value of 0. setting this bit to 1 at any other time is not supported and will result in indeterminate behavior. software must wait for clo to be cleared to 0 before setting pxcmd.st to 1. 2 power on device (pod) ? ro . cold presence de tect not supported. defaults to 1. 1 spin-up device (sud) ? r/w / ro this bit is r/w and defaults to 0 for sy stems that support st aggered spin-up (r/w when cap.sss (abar+00h:bit 27) is 1). bit is ro 1 for systems that do not support staggered spin-up (when cap.sss is 0). 0 = no action. 1 = on an edge detect from 0 to 1, the ich8 starts a comreset initialization sequence to the device. clearing this bit to 0 does not cause any oob sign al to be sent on the interface. when this bit is cleared to 0 and pxsctl.det=0 h, the hba will enter listen mode. 0 start (st) ? r/w . when set, the ich8 may process the command list. when cleared, the ich8 may not process the command list. whenever this bit is changed from a 0 to a 1, the ich8 starts processing the command list at entry 0. whenever this bit is changed from a 1 to a 0, the pxci register is cleared by the ich8 upon the ich8 putting the controller into an idle state. refer to section 12.2.1 of the serial ata ahci specification for important restrictions on when st can be set to 1. bit description sata controller registers (d31:f2) 532 intel ? ich8 family datasheet 12.4.2.8 pxtfd?port [5:0] task file data register (d31:f2) address offset: port 0: abar + 120h attribute: ro port 1: abar + 1a0h port 2: abar + 220h port 3: abar + 2a0h (desktop only) port 4: abar + 320h (desktop only) port 5: abar + 3a0h (desktop only) default value: 0000007fh size: 32 bits this is a 32-bit register that copies specific fields of the task file when fises are received. the fises that contain this information are: d2h register fis pio setup fis set device bits fis 12.4.2.9 pxsig?port [5:0] signature register (d31:f2) address offset: port 0: abar + 124h attribute: ro port 1: abar + 1a4h port 2: abar + 224h port 3: abar + 2a4h (desktop only) port 4: abar + 324h (desktop only) port 5: abar + 3a4h (desktop only) default value: ffffffffh size: 32 bits this is a 32-bit register which contains the initial signature of an attached device when the first d2h register fis is received from th at device. it is updated once after a reset sequence. bit description 31:16 reserved 15:8 error (err) ? ro . contains the latest copy of the task file error register. 7:0 status (sts) ? ro . contains the latest copy of the task file status register. fields of note in this register that affect ahci. bit field definition 7 bsy indicates the interface is busy 6:4 n/a not applicable 3 drq indicates a data transfer is requested 2:1 n/a not applicable 0 err indicates an error during the transfer bit description 31:0 signature (sig) ? ro . contains the signature received from a device on the first d2h register fis. the bit order is as follows: bit field 31:24 lba high register 23:16 lba mid register 15:8 lba low register 7:0 sector count register intel ? ich8 family datasheet 533 sata controller registers (d31:f2) 12.4.2.10 pxssts?port [5:0] serial ata status register (d31:f2) address offset: port 0: abar + 128h attribute: ro port 1: abar + 1a8h port 2: abar + 228h port 3: abar + 2a8h (desktop only) port 4: abar + 328h (desktop only) port 5: abar + 3a8h (desktop only) default value: 00000000h size: 32 bits this is a 32-bit register that conveys the current state of the interface and host. the ich8 updates it continuously and asyn chronously. when the ich8 transmits a comreset to the device, this register is updated to its reset values. bit description 31:12 reserved 11:8 interface power management (ipm) ? ro. indicates the cu rrent interface state: all other values reserved. 7:4 current interface speed (spd) ? ro. indicates the negotiated interface communication speed. all other values reserved. ich8 supports generation 1 communication rates (1.5 gb/sec) and gen 2 rates (3.0 gb/s). 3:0 device detection (det) ? ro. indicates the interface device detection and phy state: all other values reserved. va l ue descr i pt i on 0h device not present or communication not established 1h interface in active state 2h interface in partial power management state 6h interface in slumber power management state v a l ue d escr i p ti on 0h device not present or communication not established 1h generation 1 communication rate negotiated 2h generation 2 communication rate negotiated value description 0h no device de tected and phy communication not established 1h device presence detected but phy communication not established 3h device presence detected and phy communication established 4h phy in offline mode as a result of the interface being disabled or running in a bist loopback mode sata controller registers (d31:f2) 534 intel ? ich8 family datasheet 12.4.2.11 pxsctl ? port [5:0] serial ata control register (d31:f2) address offset: port 0: abar + 12ch attribute: r/w, ro port 1: abar + 1ach port 2: abar + 22ch port 3: abar + 2ach (desktop only) port 4: abar + 32ch (desktop only) port 5: abar + 3ach (desktop only) default value: 00000004h size: 32 bits this is a 32-bit read-write register by which software controls sata capabilities. writes to the scontrol register result in an action being taken by the ich8 or the interface. reads from the register return the last value written to it. bit description 31:20 reserved 19:16 port multiplier port (pmp) ? ro. this field is not used by ahci note: port multiplier not supported by ich8. 15:12 select power management (spm) ? ro. this field is not used by ahci 11:8 interface power management transitions allowed (ipm) ? r/w . indicates which power states the ich8 is allowed to transition to: all other values reserved 7:4 speed allowed (spd) ? r/w. indicates the highest al lowable speed of the interface. this speed is limited by the ca p.iss (abar+00h:bit 23:20) field. ich8 supports generation 1 communication rates (1.5 gb/sec) and gen 2 rates (3.0 gb/s). 3:0 device detection initialization (det) ? r/w . controls the ich8?s device detection and interface initialization. all other values reserved. when this field is written to a 1h, the ich8 initiates comreset and starts the initialization process. when the initialization is complete, this field shall remain 1h until set to another value by software. this field may only be change d to 1h or 4h when pxcmd.st is 0. changing this field while the ich8 is running re sults in undefined behavior. note: it is permissible to implement any of the serial ata defined behaviors for transmission of comreset when det=1h. value description 0h no interface restrictions 1h transitions to the partial state disabled 2h transitions to the slumber state disabled 3h transitions to both partial and slumber states disabled value description 0h no speed negotiation restrictions 1h limit speed negotiation to generation 1 communication rate 2h limit speed negotiation to generation 2 communication rate value description 0h no device detection or initialization action requested 1h perform interface communication initialization sequence to establish communication. this is functionally equivalent to a hard reset and results in the in terface being reset and comm unications re-initialized 4h disable the serial ata interface and put phy in offline mode intel ? ich8 family datasheet 535 sata controller registers (d31:f2) 12.4.2.12 pxserr?port [5:0] seri al ata error register (d31:f2) address offset: port 0: abar + 130h attribute: r/wc port 1: abar + 1b0h port 2: abar + 230h port 3: abar + 2b0h (desktop only) port 4: abar + 330h (desktop only) port 5: abar + 3b0h (desktop only) default value: 00000000h size: 32 bits bit description 31:16 diagnostics (diag) ? r/wc. this field contains diag nostic error information for use by diagnostic software in validating co rrect operation or isolating failure modes: bits description 31:27 reserved 26 exchanged (x) : when set to one this bit in dicates a cominit signal was received. this bit is reflected in the interrupt re gister pxis.pcs. 25 unrecognized fis type (f) : indicates that one or mo re fiss were received by the transport layer with good crc, but had a type field that was not recognized. 24 transport state transition error (t) : indicates that an error has occurred in the transitionfrom one state to another within the transport layer since the last time this bit was cleared. 23 link sequence error (s) : indicates that one or more link state machine error conditions was encountered. the li nk layer state machine defines the conditions under which the link laye r detects an erro neous transition. 22 handshake error (h) : indicates that one or more r_err handshake response was received in response to frame transm ission. such errors may be the result of a crc error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 crc error (c) : indicates that one or more cr c errors occurred with the link layer. 20 disparity error (d) : this field is no t used by ahci. 19 10b to 8b decode error (b) : indicates that one or more 10b to 8b decoding errors occurred. 18 comm wake (w) : indicates that a comm wake signal was detected by the phy. 17 phy internal error (i) : indicates that the phy detected some internal error. 16 phyrdy change (n) : when set to 1 this bit indicates that the internal phyrdy signal changed state since the last time this bit was cleared. in the ich8, this bit will be set when phyrdy changes from a 0 -> 1 or a 1 -> 0. the state of this bit is then reflected in the pxis.prcs in terrupt status bit an d an interrupt will be generated if enabled. software cl ears this bit by writing a 1 to it. sata controller registers (d31:f2) 536 intel ? ich8 family datasheet 15:0 error (err) ? r/wc. the err field contains e rror information for use by host software in determining the appropri ate response to the error condition. if one or more of bits 11:8 of this register are set, the co ntroller will stop the current transfer. bits description 15:12 reserved 11 internal error (e) : the sata controller failed due to a master or target abort when attempting to access system memory. 10 protocol error (p) : a violation of the serial ata protocol was detected. note: the ich8 does not set this bit for all protocol violations that may occur on the sata link. 9 persistent communication or data integrity error (c) : a communication error that was not recovered occurred th at is expected to be persistent. persistent communications errors may ar ise from faulty inte rconnect with the device, from a device that has been removed or has failed, or a number of other causes. 8 transient data integrity error (t) : a data integrity error occurred that was not recovered by the interface. 7:2 reserved 1 recovered communications error (m) : communications between the device and host was temporarily lost but was re-established. this can arise from a device temporarily being removed, from a temporary loss of phy synchronization, or from other causes and may be derived from the phynrdy signal between the phy and link layers. 0 recovered data integrity error (i) : a data integrity error occurred that was recovered by the interface through a retr y operation or other recovery action. bit description intel ? ich8 family datasheet 537 sata controller registers (d31:f2) 12.4.2.13 pxsact?port [5:0] serial ata active (d31:f2) address offset: port 0: abar + 134h attribute: r/w port 1: abar + 1b4h port 2: abar + 234h port 3: abar + 2b4h (desktop only) port 4: abar + 334h (desktop only) port 5: abar + 3b4h (desktop only) default value: 00000000h size: 32 bits 12.4.2.14 pxci?port [5:0] command issue register (d31:f2) address offset: port 0: abar + 138h attribute: r/w port 1: abar + 1b8h port 2: abar + 238h port 3: abar + 2b8h (desktop only) port 4: abar + 338h (desktop only) port 5: abar + 3b8h (desktop only) default value: 00000000h size: 32 bits bit description 31:0 device status (ds) ? r/w . system software sets this bi t for sata queuing operations prior to setting the pxci.ci bit in the same co mmand slot entry. this field is cleared via the set device bits fis. this field is also cleared when pxcmd. st (abar+118h/198h/218h/298h:bit 0) is cleared by software, and as a re sult of a comreset or srst. bit description 31:0 commands issued (ci) ? r/w . this field is set by software to indicate to the ich8 that a command has been built-in system me mory for a command slot and may be sent to the device. when the ich8 receives a fis which clears the bsy and drq bits for the command, it clears the corresponding bit in th is register for that command slot. bits in this field shall only be set to 1 by software when pxcmd.st is set to 1. this field is also cleared when pxcmd. st (abar+118h/198h/218h/298h:bit 0) is cleared by software. sata controller registers (d31:f2) 538 intel ? ich8 family datasheet intel ? ich8 family datasheet 539 sata controller registers (d31:f5) 13 sata controller registers (d31:f5) 13.1 pci configuration registers (sata?d31:f5) note: address locations that are not shown should be treated as reserved. all of the sata registers are in the core well. none of the registers can be locked. table 127. sata controller pci register address map (sata?d31:f5) (sheet 1 of 2) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 02b0h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface see register description see register description 0ah scc sub class code see register description see register description 0bh bcc base class code 01h ro 0dh pmlt primary master latency timer 00h ro 10h?13h pcmd_bar primary command block base address 00000001h r/w, ro 14h?17h pcnl_bar primary control block base address 00000001h r/w, ro 18h?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1ch?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20h?23h bar legacy bus master base address 00000001h r/w, ro 24h?27h sidpba serial ata index / data pair base address 00000000h see register description 2ch?2dh svid subsystem vendor identification 0000h r/wo 2eh?2fh sid subsystem identification 0000h r/wo 34h cap capabilities pointer 80h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 40h?41h ide_timp primary ide timing 0000h r/w 42h?43h ide_tims secondary ide timing 0000h r/w 44h sidetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control 00h r/w sata controller registers (d31:f5) 540 intel ? ich8 family datasheet note: the ich8 sata controller is not arbitrated as a pci device, therefore it does not need a master latency timer. 13.1.1 vid?vendor iden tification regist er (sata?d31:f5) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bit lockable: no power well: core 4ah?4bh sdma_tim synchronous dma timing 0000h r/w 54h?57h ide_config ide i/o configuration 00000000h r/w 70h?71h pid pci power management capability id see register description ro 72h?73h pc pci power management capabilities 4002h ro 74h?75h pmcs pci power management control and status 0000h r/w, ro, r/wc 80h?81h msici message signaled in terrupt capability id 7005h ro 82h?83h msimc message signaled interrupt message control 0000h ro, r/w 84h?87h msima message signaled interrupt message address 00000000h ro, r/w 88h?89h msimd message signaled interrupt message data 0000h r/w 90h map address map 00h r/w 92h?93h pcs port control and status 0000h r/w, ro, r/wc 94h?97h sir sata initialization register 00000000h r/w a0h siri sata indexed registers index 00h r/w a4h strd sata indexed register data xxxxxxxxh r/w a8h?abh scap0 sata capability register 0 00100012h ro ach?afh scap1 sata capability register 1 00000048h ro c0h atc apm trapping control 00h r/w c4h ats atm trapping status 00h r/wc d0h?d3h sp scratch pad 00000000h r/w e0h?e3h bfcs bist fis control/status 00000000h r/w, r/wc e4h?e7h bftd1 bist fis transmit data, dw1 00000000h r/w e8h?ebh bftd2 bist fis transmit data, dw2 00000000h r/w table 127. sata controller pci register address map (sata?d31:f5) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit va lue assigned to intel. intel vid = 8086h intel ? ich8 family datasheet 541 sata controller registers (d31:f5) 13.1.2 did?device identificati on register (sata?d31:f5) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16 bit lockable: no power well: core 13.1.3 pcicmd?pci command register (sata?d31:f5) address offset: 04h ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich8 sata controller. note: the value of this field will change dependent upon the value of the map register. see the intel ich8 family specification update. bit description 15:11 reserved 10 interrupt disable ? r/w. this disables pin-based intx# interrupts. this bit has no effect on msi operation. 0 = internal intx# messages are generated if there is an interrupt and msi is not enabled. 1 = internal intx# messages will not be generated. 9 fast back to back enable (fbe) ? ro. reserved as 0. 8 serr# enable (serr_en) ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. reserved as 0. 6 parity error response (per) ? r/w. 0 = disabled. sata controller will not gene rate perr# when a data parity error is detected. 1 = enabled. sata controller will generate pe rr# when a data parity error is detected. 5 vga palette snoop (vps) ? ro. reserved as 0. 4 postable memory write enable (pmwe) ? ro. reserved as 0. 3 special cycle en able (sce) ? ro. reserved as 0. 2 bus master enable (bme) ? r/w. this bit controls the ich8?s ability to act as a pci master for ide bus master transfers. this bit does not impact the generation of completions for split transaction commands. 1 memory space enable (mse) ? ro. this controller does not support ahci, therefore no memory space is required. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus mast er i/o registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set. sata controller registers (d31:f5) 542 intel ? ich8 family datasheet 13.1.4 pcists ? pci status register (sata?d31:f5) address offset: 06h ? 07h attribute: r/wc, ro default value: 02b0h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 13.1.5 rid?revision identificati on register (sata?d31:f5) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected by sata controller. 1 = sata controller detects a parity error on its interface. 14 signaled system error (sse) ? ro. reserved as 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated. 1 = sata controller, as a master , generated a master abort. 12 reserved as 0 ? ro. 11 signaled target abort (sta) ? ro. reserved as 0. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; controls the devi ce select time for the sata controller?s pci interface. 8 data parity error detected (dped) ? ro. for ich8, this bit can only be set on read completions received from sibus where there is a parity error. 1 = sata controller, as a master, either detect s a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. 7 fast back to back capable (fb2bc) ? ro. reserved as 1. 6 user definable features (udf) ? ro. reserved as 0. 5 66mhz capable (66mhz_cap) ? ro. reserved as 1. 4 capabilities list (cap_list) ? ro. this bit indicates the presence of a capabilities list. the minimum requirement for the capabili ties list must be pci power management for the sata controller. 3 interrupt status (ints) ? ro. reflects the state of intx# messages. 0 = interrupt is cleared (ind ependent of the state of in terrupt disabl e bit in the command register [offset 04h]). 1 = interrupt is to be asserted 2:0 reserved bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 8 (ich8) family specification update for the value of the revision id register intel ? ich8 family datasheet 543 sata controller registers (d31:f5) 13.1.6 pi?programmin g interface register (sata?d31:f5) address offset: 09h attribute: ro default value: 85h size: 8 bits 13.1.7 scc?sub class code register (sata?d31:f5) address offset: 0ah attribute: ro default value: 01h size: 8 bits 13.1.8 bcc?base clas s code register (sata?d31:f5sata?d31:f5) address offset: 0bh attribute: ro default value: 01h size: 8 bits 13.1.9 pmlt?primary master latency timer register (sata?d31:f5) address offset: 0dh attribute: ro default value: 00h size: 8 bits bit description 7 this read-only bit is a 1 to indicate th at the ich8 supports bus master operation 6:4 reserved. will always return 0. 3 secondary mode native capable (snc) ? ro. 0 = secondary controller only supports legacy mode. this bit will always return ?0? 2 secondary mode nati ve enable (sne) ? r/w / ro. determines the mode th at the secondary channel is operating in. 1 = secondary controller operating in native pci mode. this bit will always return ?1? 1 primary mode native capable (pnc) ? ro. 0 = primary controller only supports legacy mode. this bit will always return ?0? 0 primary mode native enable (pne) ? ro. determines the mode that the primary channel is operating in. 1 = primary controller operating in native pci mode. this bit will always return ?1? bit description 7:0 interface (if) ? ro. this controller only supports ide programming interface and is only 01h. bit description 7:0 base class code (bcc) ? ro. 01h = mass storage device bit description 7:0 master latency timer count (mltc) ? ro. 00h = hardwired. the sata controller is im plemented internally, and is not arbitrated as a pci device, so it does no t need a master latency timer. sata controller registers (d31:f5) 544 intel ? ich8 family datasheet 13.1.10 pcmd_bar?primary co mmand block base address register (sata?d31:f5) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 8-byte i/o space is used in native mo de for the primary cont roller?s command block. 13.1.11 pcnl_bar?primary contro l block base address register (sata?d31:f5) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 4-byte i/o space is used in native mo de for the primary cont roller?s command block. 13.1.12 scmd_bar?secondary co mmand block base address register (ide d31:f1) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 8-byte i/o space is used in native mode for the secondary controller?s command block. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwi red to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the ba se address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwi red to 1 to indicate a request for i/o space. intel ? ich8 family datasheet 545 sata controller registers (d31:f5) 13.1.13 scnl_bar?secondary co ntrol block base address register (ide d31:f1) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. 13.1.14 bar ? legacy bus mast er base address register (sata?d31:f5) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface function uses base address register 5 to request a 16-byte i/o space to provide a software inte rface to the bus master functions. only 12 bytes are actually used (6 bytes for prim ary, 6 bytes for secondary). only bits [15:4] are used to decode the address. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwi red to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:4 base address ? r/w. this field provides the base address of the i/o space (16 consecutive i/o locations). 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. sata controller registers (d31:f5) 546 intel ? ich8 family datasheet 13.1.15 sidpba ? sata index/data pair base a ddress register (sata?d31:f5) address offset: 24h ? 27h attribute: r/w, ro default value: 00000001h size: 32 bits this register is an i/o bar allocating 16 bytes of i/o space for the i/o-mapped registers defined in section 13.3 . note that although 16 bytes of locations are allocated, some locations are reserved. 13.1.16 svid?subsystem vendor identification register (sata?d31:f5) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 13.1.17 sid?subsystem identifica tion register (sata?d31:f5) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 13.1.18 cap?capabilities poin ter register (sata?d31:f5) address offset: 34h attribute: ro default value: 80h size: 8 bits bit description 31:16 reserved 15:4 base address (ba) ? r/w. base address of register i/o space 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 15:0 subsystem vendor id (svid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 15:0 subsystem id (sid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 7:0 capabilities pointer (cap_ptr) ? ro. indicates that the first capabili ty pointer offset is 80h. this value changes to 70h if the map. mv register (dev 31:f2:90h, bits 1:0) in configuration space indicates that the sata function and pata functions are combined (values of 10b or 10b) or sub class code (cc. scc) (dev 31:f2:0ah) is configure as ide mode (value of 01). intel ? ich8 family datasheet 547 sata controller registers (d31:f5) 13.1.19 int_ln?interrupt line register (sata?d31:f5) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 13.1.20 int_pn?interrupt pi n register (sata?d31:f5) address offset: 3dh attribute: ro default value: see register description size: 8 bits 13.1.21 ide_tim ? ide timing register (sata?d31:f5) address offset: primary: 40h ? 41h attribute: r/w secondary: 42h ? 43h default value: 0000h size: 16 bits this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation unless otherwise noted. bit description 7:0 interrupt line ? r/w. this field is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:0 interrupt pin ? ro. this reflects the value of d31i p.sip1 (chipset configuration registers:offset 3100h:bits 11:8). bit description 15 ide decode enable (ide) ? r/w. individually enable/disable the primary or secondary decode. 0 = disable. 1 = enables the intel? ich8 to decode th e associated command blocks (1f0?1f7h for primary, 170?177h for secondary) and control block (3f6h for primary and 376h for secondary). this bit effects the ide deco de ranges for both legacy and native-mode decoding. note: this bit affects sata operation in both combined and non-combined ata modes. see section 5.16 for more on ata modes of operation. 14 drive 1 timing register enable (sitre) ? r/w. 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and us e the slave ide timing register for drive 1 13:12 iordy sample point (isp) ? r/w. the setting of these bits determines the number of pci clocks between ide ior#/iow# asse rtion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved sata controller registers (d31:f5) 548 intel ? ich8 family datasheet 11:10 reserved 9:8 recovery time (rct) ? r/w. the setting of these bits determines the minimum number of pci clocks between the last io rdy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock 7 drive 1 dma timing enable (dte1) ? r/w. 0 = disable. 1 = enable the fast timing mode for dma transf ers only for this drive. pio transfers to the ide data port will run in compatible timing. 6 drive 1 prefetch/posting enable (ppe1) ? r/w. 0 = disable. 1 = enable prefetch and posting to the ide data port for this drive. 5 drive 1 iordy sample point enable (ie1) ? r/w. 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive. 4 drive 1 fast timing bank (time1) ? r/w. 0 = accesses to the data port will us e compatible timings for this drive. 1 = when this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. when this bit = 1 and bit 14 = 1, accesses to th e data port will use the iordy sample point and recover time specified in the slave ide timing register. 3 drive 0 dma timing enable (dte0) ? r/w. 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 2 drive 0 prefetch/posting enable (ppe0) ? r/w. 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. 1 drive 0 iordy sample point enable (ie0) ? r/w. 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. 0 drive 0 fast timing bank (time0) ? r/w. 0 = accesses to the data port will us e compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time bit description intel ? ich8 family datasheet 549 sata controller registers (d31:f5) 13.1.22 d1tim?device 1 ide timi ng register (sata?d31:f5) address offset: 44h attribute: r/w default value: 00h size: 8 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are co mbined. device 1 is not allowed on this controller. 13.1.23 sdma_cnt?synchronous dma control register (sata?d31:f5) address offset: 48h attribute: r/w default value: 00h size: 8 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation unless otherwise noted. bit description 7:0 reserved bit description 7:3 reserved 2 secondary drive 0 ataxx enable (sdae0) ? r/w. 0 = disable (default) 1 = enable dma timing modes for the secondary master device. 1 reserved 0 primary drive ataxx enable (pdae0) ? r/w. 0 = disable (default) 1 = enable dma timing modes fo r the primary master device sata controller registers (d31:f5) 550 intel ? ich8 family datasheet 13.1.24 sdma_tim?synchronous dma timing register (sata?d31:f5) address offset: 4ah ? 4bh attribute: r/w default value: 0000h size: 16 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation, unless otherwise noted. bit description 15:10 reserved 9:8 secondary drive 0 cycle time (sct0) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to- stop (rp) time is also determin ed by the settin g of these bits. 7:2 reserved 1:0 primary drive 0 cycle time (pct0) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33 mhz clock) scb1 = 1 (66 mhz clock) fast_scb1 = 1 (133 mhz clock) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved pcb1 = 0 (33 mhz clock) pcb1 = 1 (66 mhz clock) fast_pcb1 = 1 (133 mhz clock) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved intel ? ich8 family datasheet 551 sata controller registers (d31:f5) 13.1.25 ide_config?ide i/o configuration register (sata?d31:f5) address offset: 54h ? 57h attribute: r/w default value: 00000000h size: 32 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are comb ined. these bits have no effect on sata operation, unless otherwise noted. bit description 31:24 reserved 23:20 scratchpad (sp2). intel ? ich8 does not perform an y actions on these bits. 19:18 sec_sig_mode ? r/w. these bits are used to co ntrol mode of the secondary ide signal pins for swap bay support. if the srs bit (chipset configuration registers:offset 3414h:bit 1) is 1, the reset states of bits 19:18 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 17:16 prim_sig_mode ? r/w. these bits are used to control mode of the primary ide signal pins for mobi le swap bay support. if the prs bit (chipset configuration registers:offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 15 fast secondary drive 1 base clock (fast_scb1) ? r/w. this bit is used in conjunction with the sct1 bits (d31:f5:4ah, bits 13:12) to enable/disable ultra ata/ 100 timings for the secondary slave drive. 0 = disable ultra ata/100 timing for the secondary slave drive. 1 = enable ultra ata/100 timing for the secondary slave drive (overrides bit 3 in this register). 14 fast secondary drive 0 base clock (fast_scb0) ? r/w. this bit is used in conjunction with the sct0 bits (d31:f5:4ah, bits 9:8) to enable/disable ultra ata/100 timings for the secondary master drive. 0 = disable ultra ata/100 timing for the secondary master drive. 1 = enable ultra ata/100 timing for the secondary master drive (overrides bit 2 in this register). 13 fast primary drive 1 base clock (fast_pcb1) ? r/w. this bit is used in conjunction with the pct1 bits (d31:f5:4ah, bits 5:4) to enable/disable ultra ata/100 timings for the primary slave drive. 0 = disable ultra ata/100 timing for the primary slave drive. 1 = enable ultra ata/100 timing for the primary slave drive (overrides bit 1 in this register). 12 fast primary drive 0 base clock (fast_pcb0) ? r/w. this bit is used in conjunction with the pct0 bits (d31:f5:4ah, bits 1:0) to enable/disable ultra ata/100 timings for the primary master drive. 0 = disable ultra ata/100 timing for the primary master drive. 1 = enable ultra ata/100 timing for the primary master drive (overrides bit 0 in this register). sata controller registers (d31:f5) 552 intel ? ich8 family datasheet 13.1.26 pid?pci power management capability identification register (sata?d31:f5) address offset: 70h?71h attribute: ro default value: 0001h size: 16 bits 13.1.27 pc?pci power manageme nt capabilities register (sata?d31:f5) address offset: 72h ? 73h attribute: ro default value: 4003h size: 16 bits f 11:8 reserved 7:4 scratchpad (sp1). ich8 does not perform any action on these bits. 3 secondary drive 1 base clock (scb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 2 secondary drive 0 base clock (scbo) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 1 primary drive 1 base clock (pcb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 0 primary drive 0 base clock (pcb0) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings bit description bits description 15:8 next capability (next) ? ro. 00h ? this is the last item in the list. 7:0 capability id (cid) ? ro. indicates that this pointer is a pci power management. bits description 15:11 pme support (pme_sup) ? ro. indicate s pme# can be generated from the d3 hot state in the sata host controller. 10 d2 support (d2_sup) ? ro. hardwired to 0. the d2 state is not supported 9 d1 support (d1_sup) ? ro. hardwired to 0. the d1 state is not supported 8:6 auxiliary current (aux_cur) ? ro. pme# from d3cold state is not supported, therefore this field is 000b. 5 device specific initialization (dsi) ? ro. ha rdwired to 0 to indicate that no device- specific initialization is required. 4 reserved 3 pme clock (pme_clk) ? ro. hardwired to 0 to in dicate that pci clock is not required to generate pme#. 2:0 version (ver) ? ro. hardwired to 011 to indi cates support for revision 1.2 of the pci power management specification. intel ? ich8 family datasheet 553 sata controller registers (d31:f5) 13.1.28 pmcs?pci power mana gement control and status register (sata?d31:f5) address offset: 74h ? 75h attribute: ro, r/w, r/wc default value: 0008h size: 16 bits 13.1.29 map?address map re gister (sata?d31:f5) address offset: 90h attribute: ro default value: 00h size: 8 bits bits description 15 pme status (pmes) ? r/wc. bit is set when a pme event is to be requested, and if this bit and pmee is set, a pme# will be generated from the sata controller 14:9 reserved 8 pme enable (pmee) ? r/w. when set, the sata co ntroller generates pme# form d3 hot on a wake event. 7:4 reserved 3 no soft reset (nsfrst) ? ro. these bits are used to indicate whether devices transitioning from d3 hot state to d0 state will perform an internal reset. 0 = device transitioning from d3 hot state to d0 state perfo rm an internal reset. 1 = device transitioning from d3 hot state to d0 state do not perform an internal reset. configuration content is preserved. upon transition from the d3 hot state to d0 state initialized state, no addition al operating system interventi on is required to preserve configuration context beyond writing to the powerstate bits. regardless of this bit, the controller transition from d3 hot state to d0 state by a system or bus segment reset will return to the state d0 uninitialized with only pme context preserved if pme is supported and enabled. 2 reserved 1:0 power state (ps) ? r/w. these bits are used both to determine the current power state of the sata controller and to set a new power state. 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller?s configurat ion space is available, but the i/o and memory spaces are not. addi tionally, interrupts are blocked. bits description 7:2 reserved. 1:0 map value ? ro. map value (mv): this field is ha rdwired to read-only ?00? indicating the controller shall support two logical mast er devices with port 0 and port 1 being mapped to primary channel and secondary channel respectively sata controller registers (d31:f5) 554 intel ? ich8 family datasheet 13.1.30 pcs?port control and status register (sata?d31:f5) address offset: 92h ? 93h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits by default, the sata ports are set to the di sabled state (bits [5:0] = ?0?). when enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. when disabled, the port is in the ?off? state and cannot detect any devices. if an ahci-aware or raid enabled operating system is being booted then system bios shall insure that all supported sata ports are enabled prior to passing control to the os. once the ahci aware os is booted it becomes the enabling/disabling policy owner for the individual sata ports. this is acco mplished by manipulating a port?s pxsctl and pxcmd fields. because an ahci or raid awar e os will typically not have knowledge of the pxe bits and because the pxe bits act as master on/off switches for the ports, pre- boot software must insure that these bits are set to ?1? prior to booting the os, regardless as to whether or not a device is currently on the port. bits description 15:10 reserved 9 port 1 present (p1p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabled via p1e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 1 has been detected. 8 port 0 present (p0p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabled via p0e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 0 has been detected. 7:2 reserved 1 port 1 enabled (p1e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. 0 port 0 enabled (p0e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. intel ? ich8 family datasheet 555 sata controller registers (d31:f5) 13.1.31 atc?apm trapping cont rol register (sata?d31:f5) address offset: c0h attribute: r/w default value: 00h size: 8 bits note: this sata controller does not support legacy i/o access. therefore, this register is reserved. software shall not change the default values of the register; otherwise the result will be undefined. . 13.1.32 ats?apm trapping stat us register (sata?d31:f5) address offset: c4h attribute: r/wc default value: 00h size: 8 bits note: this sata controller does not support legacy i/o access. therefore, this register is reserved. software shall not change the default values of the register; otherwise the result will be undefined. . bit description 7:0 reserved bit description 7:0 reserved sata controller registers (d31:f5) 556 intel ? ich8 family datasheet 13.2 bus master ide i/ o registers (d31:f5) the bus master ide function uses 16 bytes of i/o space, allocated via the bar register, located in device 31:function 2 configuration space, offset 20h. all bus master ide i/o space registers can be accessed as byte, word, or dword quantities. reading reserved bits returns an indeterminate, inconsistent va lue, and writes to reserved bits have no affect (but should not be attempted). these registers are only used for legacy operation. software must not use these registers when running ahci. the description of the i/o registers is shown in table 128 . table 128. bus master ide i/o register address map bar+ offset mnemonic register default type 00 bmicp command register primary 00h r/w 01 ? reserved ? ro 02 bmisp bus master ide status register primary 00h r/w, r/wc, ro 03 ? reserved ? ro 04?07 bmidp bus master ide descriptor table pointer primary xxxxxxxxh r/w 08 bmics command register secondary 00h r/w 09 ? reserved ? ro 0ah bmiss bus master ide status register secondary 00h r/w, r/wc, ro 0bh ? reserved ? ro 0ch?0fh bmids bus master ide descriptor table pointer secondary xxxxxxxxh r/w intel ? ich8 family datasheet 557 sata controller registers (d31:f5) 13.2.1 bmic[p,s]?bus master id e command register (d31:f5) address offset: primary: bar + 00h attribute: r/w secondary: bar + 08h default value: 00h size: 8 bits bit description 7:4 reserved. returns 0. 3 read / write control (r/wc) ? r/w. this bit sets the di rection of the bus master transfer: this bit must not be changed wh en the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved. returns 0. 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus master operation is still active (i.e., the bus master ide active bit (d31:f5:bar + 02h, bit 0) of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bi t in the bus master id e status register for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controller. bus master operation does not actually start unless the bus master enable bit (d31:f1:04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detected changing from 0 to 1. the controller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bu s master ide active bit being cleared or the interrupt bit of the bus master ide status register fo r that ide channel being set, or both. hardware does not clea r this bit automatically. if this bit is cleared to 0 prior to the dma data transfer being initiated by the drive in a sata controller registers (d31:f5) 558 intel ? ich8 family datasheet 13.2.2 bmis[p,s]?bus master id e status register (d31:f5) address offset: primary: bar + 02h attribute: r/w, r/wc, ro secondary: bar + 0ah default value: 00h size: 8 bits 13.2.3 bmid[p,s]?bus master id e descriptor table pointer register (d31:f5) address offset: primary: bar + 04h?07h attribute: r/w secondary: bar + 0ch ? 0fh default value: all bits undefined size: 32 bits bit description 7 prd interrupt status (prdis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the host controller execution of a prd that has its prd_int bit set. 6 reserved. 5 drive 0 dma capable ? r/w. 0 = not capable 1 = capable. set by device dependent code (b ios or device driver ) to indicate that drive 0 for this channel is capable of dm a transfers, and that the controller has been initialized for optimum performance. the ich8 does not use this bit. it is intended for systems that do no t attach bmide to the pci bus. 4:3 reserved. returns 0. 2 interrupt ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set when a device fis is received with the ?i? bit set, provided that software has not disabled interrupts via the ien bit of the device control register (see chapter 5 of the serial ata specification , revision 2.5). 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encoun ters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the ich8 when the last transfer for a region is performed, where eot for that region is set in the regi on descriptor. it is also cleared by the ich8 when the start bus master bit (d31: f5:bar+ 00h, bit 0) is cleared in the command register. when this bi t is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the ich8 when the start bit is written to the command register. bit description 31:2 address of descriptor table (addr) ? r/w. the bits in this field correspond to bits [31:2] of the memory location of the physic al region descriptor (prd). the descriptor table must be dword-aligned. the descriptor table must not cross a 64-kb boundary in memory. 1:0 reserved intel ? ich8 family datasheet 559 sata controller registers (d31:f5) 13.2.3.1 pxssts?serial ata status register (d31:f5) address offset: bar + 00h attribute: ro default value: 00000000h size: 32 bits this is a 32-bit register that conveys the current state of the interface and host. the ich8 updates it continuously and asyn chronously. when the ich8 transmits a comreset to the device, this register is updated to its reset values. bit description 31:12 reserved 11:8 interface power management (ipm) ? ro . indicates the current interface state: all other values reserved. 7:4 current interface speed (spd) ? ro. indicates the negotiated interface communication speed. all other values reserved. ich8 supports generation 1 communication rates (1.5 gb/sec) and gen 2 rates (3.0 gb/s). 3:0 device detection (det) ? ro . indicates the interface de vice detection and phy state: all other values reserved. va l ue descr i pt i on 0h device not present or communication not established 1h interface in active state 2h interface in partial power management state 6h interface in slumber power management state v a l ue d escr i p ti on 0h device not present or communication not established 1h generation 1 communication rate negotiated 2h generation 2 communication rate negotiated value description 0h no device de tected and phy communication not established 1h device presence detected but phy communication not established 3h device presence detected and phy communication established 4h phy in offline mode as a result of the interface being disabled or running in a bist loopback mode sata controller registers (d31:f5) 560 intel ? ich8 family datasheet 13.2.3.2 pxsctl ? serial ata control register (d31:f5) address offset: bar + 01h attribute: r/w, ro default value: 00000004h size: 32 bits this is a 32-bit read-write register by which software controls sata capabilities. writes to the scontrol register result in an action being taken by the ich8 or the interface. reads from the register return the last value written to it. bit description 31:20 reserved 19:16 port multiplier port (pmp) ? ro. this field is not used by ahci note: port multiplier not supported by ich8. 15:12 select power management (spm) ? ro. this field is not used by ahci 11:8 interface power management transitions allowed (ipm) ? r/w . indicates which power states the ich8 is allowed to transition to: all other values reserved 7:4 speed allowed (spd) ? r/w. indicates the highest al lowable speed of the interface. this speed is limited by the ca p.iss (abar+00h:bit 23:20) field. all other values reserved. ich8 supports generation 1 communication rates (1.5 gb/sec) and gen 2 rates (3.0 gb/s). 3:0 device detection initialization (det) ? r/w . controls the ich8?s device detection and interface initialization. all other values reserved. when this field is written to a 1h, the ich8 initiates comreset and starts the initialization process. when the initialization is complete, this field shall remain 1h until set to another value by software. this field may only be change d to 1h or 4h when pxcmd.st is 0. changing this field while the ich8 is running re sults in undefined behavior. value description 0h no interface restrictions 1h transitions to the partial state disabled 2h transitions to the slumber state disabled 3h transitions to both partial and slumber states disabled value description 0h no speed negotiation restrictions 1h limit speed negotiation to generation 1 communication rate 2h limit speed negotiation to generation 2 communication rate value description 0h no device detection or initialization action requested 1h perform interface communication initialization sequence to establish communication. this is functionally equivalent to a hard reset and results in the interface bein g reset and communications re- initialized 4h disable the serial ata interface and put phy in offline mode intel ? ich8 family datasheet 561 sata controller registers (d31:f5) 13.2.3.3 pxserr?serial ata error register (d31:f5) address offset: bar + 02h attribute: r/wc default value: 00000000h size: 32 bits bit description 31:16 diagnostics (diag) ? r/wc . contains diagnostic erro r information for use by diagnostic software in validating corre ct operation or isolating failure modes: bits description 31:27 reserved 26 exchanged (x) : when set to one this bit in dicates a cominit signal was received. this bit is reflected in the inte rrupt register pxis.pcs. 25 unrecognized fis type (f) : indicates that one or mo re fiss were received by the transport layer with good crc, but had a type field that was not recognized. 24 transport state transition error (t) : indicates that an error has occurred in the transition from one state to another within the transport layer since the last time this bit was cleared. 23 link sequence error (s) : indicates that one or more link state machine error conditions was enco untered. the link layer state machine defines the conditions under which the link layer detects an erroneous transition. 22 handshake error (h) : indicates that one or more r_err handshake response was received in response to frame transmis sion. such errors may be the result of a crc error detected by the recipient, a disparity or 8b/10b decoding error, or other error conditio n leading to a negative handshake on a transmitted frame. 21 crc error (c) : indicates that one or more crc errors oc curred with the link layer. 20 disparity error (d) : this field is not used by ahci. 19 10b to 8b decode error (b) : indicates that one or more 10b to 8b decoding errors occurred. 18 comm wake (w) : indicates that a comm wake signal was detected by the phy. 17 phy internal error (i) : indicates that the phy dete cted some internal error. 16 phyrdy change (n) : when set to 1 this bit indicates that the internal phyrdy signal changed state since th e last time this bit was cl eared. in the ich8, this bit will be set when phyrdy changes from a 0 -> 1 or a 1 -> 0. the state of this bit is then reflected in th e pxis.prcs interrupt status bit and an interrupt will be generated if enabled. software cl ears this bit by writing a 1 to it. sata controller registers (d31:f5) 562 intel ? ich8 family datasheet 15:0 error (err) ? r/wc . the err field contains error information for use by host software in determining the appropri ate response to the error condition. if one or more of bits 11:8 of this register are set, the co ntroller will stop the current transfer. bits description 15:12 reserved 11 internal error (e) : the sata controller failed due to a master or target abort when attempting to access system memory. 10 protocol error (p) : a violation of the serial ata protocol was detected. note: the ich8 does not set this bit for al l protocol violations that may occur on the sata link. 9 persistent communication or data integrity error (c) : a communication error that was not recove red occurred that is expe cted to be persistent. persistent communications errors may arise from faul ty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. 8 transient data integrity error (t) : a data integrity error occurred that was not recovered by the interface. 7:2 reserved 1 recovered communications error (m) : communications between the device and host was temporarily lost but was re-established. this can arise from a device temporarily being remo ved, from a temporary loss of phy synchronization, or from other causes and may be derived from the phynrdy signal between the phy and link layers. 0 recovered data integrity error (i) : a data integrity er ror occurred that was recovered by the interface through a retr y operation or other recovery action. bit description intel ? ich8 family datasheet 563 sata controller registers (d31:f5) 13.3 serial ata index/data pair superset registers all of these i/o registers are in the core we ll. they are exposed only when cc.scc is 01h (i.e. ide programming interface) and the controller is not in combined mode. these are index/data pair registers that are used to access the serialata superset registers (serialata status, serialata cont rol and serialata error). the i/o space for these registers is allocated through sidpba. locations with offset from 08h to 0fh are reserved for future expansion. software-write operations to the reserved locations shall have no effect while software-read operations to the reserved locations shall return 0. 13.3.1 sindx?sata index register (d31:f5) address offset: sidpba + 00h attribute: r/w default value: 00000000h size: 32 bits note: these are index/data pair registers that are used to access the ssts, sctl, and serr. the i/o space for these registers is allocated through sidpba. 13.3.2 sdata?sata index data register (d31:f5) address offset: sidpba + 04h attribute: r/w default value: all bits undefined size: 32 bits note: these are index/data pair registers that are used to access the ssts, sctl, and serr. the i/o space for these registers is allocated through sidpba. bit description 31:16 reserved 15:8 port index (pidx) ? r/w : this index field is used to specify the port of the sata controller at which the po rt-specific ssts, sctl, and serr registers are located. 00h = primary master (port 0) 02h = secondary master (port 1) all other values are reserved. 7:0 register index (ridx) ? r/w : this index field is used to specify one out of three registers currently being indexed into. 00h = ssts 01h = sctl 02h = serr all other values are reserved bit description 31:0 data (data) ? r/w : this data register is a ?window? through which data is read or written to the memory mapped regi sters. a read or write to this data register triggers a corresponding read or write to the memory mapped register poin ted to by the index register. the index register must be setup prior to the read or write to this data register. note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. since this is not a physical register, the ?default? value is the same as the default value of the register pointed to by index. sata controller registers (d31:f5) 564 intel ? ich8 family datasheet intel ? ich8 family datasheet 565 uhci controllers registers 14 uhci controllers registers 14.1 pci configuration registers (usb?d29:f0/f1/f2, d26:f0/f1) note: the usb functions may be hidden based on th e value of the corresponding bits in the function disable register (see chipset configuration registers). uhcis must be disabled from highest number to lowest within their specific pci device. note: register address locations that are not shown in table 130 and should be treated as reserved (see section 6.2 for details). table 129. uhci controlle r pci configuration map uhci pci device:function notes uhci #1 d29:f0 uhci #2 d29:f1 uhci #3 d29:f2 uhci #4 d26:f0 uhci #5 d26:f1 table 130. uhci controller pci register address map (usb?d29:f0/f1/f2, d26:f0/f1) (sheet 1 of 2) offset mnemonic register name uhci #1?5 default type 00?01h vid vendor identification 8086h ro 02?03h did device identification see register description ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0280h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 03h ro 0bh bcc base class code 0ch ro 0dh mlt master latency timer 00h ro 0eh headtyp header type see register description ro 20?23h base base address 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 3ch int_ln interrupt line 00h r/w uhci controllers registers 566 intel ? ich8 family datasheet note: refer to the intel ? ich8 family specification update for the value of the revision id register. 14.1.1 vid?vendor identi fication register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 14.1.2 did?device identi fication register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 3dh int_pn interrupt pin see register description ro 60h usb_relnum serial bus release number 10h ro c0?c1h usb_legkey usb legacy keyboard/mouse control 2000h r/w, ro r/wc c4h usb_res usb resume enable 00h r/w c8h cwp core well policy 00h r/w table 130. uhci controller pci register address map (usb?d29:f0/f1/f2, d26:f0/f1) (sheet 2 of 2) offset mnemonic register name uhci #1?5 default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich8 usb universal host controllers. refer to the intel ich8 family specification update for the value of the device id register. intel ? ich8 family datasheet 567 uhci controllers registers 14.1.3 pcicmd?pci command re gister (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable. the function is ab le to generate its interrupt to the interrupt controller. 1 = disable. the function is not ca pable of generating interrupts. note: the corresponding interrupt status bit is not affected by the interrupt enable. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? ro. hardwired to 0. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. 0 = disable 1 = enable. ich8 can act as a master on the pci bus for usb transfers. 1 memory space enable (mse) ? ro. hardwired to 0. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disable 1 = enable accesses to the usb i/o registers. the base address register for usb should be programmed before this bit is set. uhci controllers registers 568 intel ? ich8 family datasheet 14.1.4 pcists?pci status register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 06h ? 07h attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 14.1.5 rid?revision iden tification register (usb?d29:f0/f1/f2, d26:f0/f1) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = set when a data parity error data parity error is detected on writes to the uhci register space or on read completion s returned to the host controller. 14 reserved as 0b. read only. 13 received master abort (rma) ? r/wc. 0 = no master abort generated by usb. 1 = usb, as a master, gene rated a master abort. 12 reserved. always read as 0. 11 signaled target abort (sta) ? r/wc. 0 = ich8 did not terminate transaction for usb function with a target abort. 1 = usb function is targeted with a transact ion that the ich8 term inates with a target abort. 10:9 devsel# timing status (dev_sts) ? ro. this 2-bit field defines the timing for devsel# assertion. these read only bits indicate the ich8's devsel# timing when performing a positive decode. ich8 genera tes devsel# with medium timing for usb. 8 data parity error detected (dped) ? ro. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (u df) ? ro. hardwired to 0. 5 66 mhz capable ? ro. hardwired to 0. 4 capabilities list ? ro. hardwired to 0. 3 interrupt status ? ro. this bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = interrupt is deasserted. 1 = interrupt is asserted. the value reported in this bit is independen t of the value in the interrupt enable bit. 2:0 reserved bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 8 (ich8) family specification update for the value of the revision id register intel ? ich8 family datasheet 569 uhci controllers registers 14.1.6 pi?programming interface register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 09h attribute: ro default value: 00h size: 8 bits 14.1.7 scc?sub class code register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 0ah attribute: ro default value: 03h size: 8 bits 14.1.8 bcc?base clas s code register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 0bh attribute: ro default value: 0ch size: 8 bits 14.1.9 mlt?master latency timer register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 0dh attribute: ro default value: 00h size: 8 bits bit description 7:0 programming interface ? ro. 00h = no specific register level programming interface defined. bit description 7:0 sub class code (scc) ? ro. 03h = usb host controller. bit description 7:0 base class code (bcc) ? ro. 0ch = serial bus controller. bit description 7:0 master latency timer (mlt) ? ro. the usb co ntroller is implemented internal to the ich8 and not arbitrated as a pci device. therefore the device does not require a master latency timer. uhci controllers registers 570 intel ? ich8 family datasheet 14.1.10 headtyp?header type register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 0eh attribute: ro default value: see bit description size: 8 bits for uhci #2, 3, and 5 this register is ha rdwired to 00h. for uhci #1 and uhci #4, bit 7 is determined by the values in the usb function disable bits (11:8 of the function disable register chipset configuration registers:offset 3418h). 14.1.11 base?base address register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits 14.1.12 svid ? subsys tem vendor identi fication register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 2ch?2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core bit description 7 multi-function device ? ro. since the upper functi ons in this device can be individually hidden, this bit is based on the function-disab le bits in chipset config space: offset 3418h as follows: 0 = single-function device. (d efault for uhci #2,3 and5) 1 = multi-function device. (d efault for uhci #1 and 4) 6:0 configuration layout. hardwired to 00h, whic h indicates the standard pci configuration layout. bit description 31:16 reserved 15:5 base address ? r/w. bits [15:5] correspond to i/o address signals ad [15:5], respectively. this gives 32 bytes of relocatable i/o space. 4:1 reserved 0 resource type indicator (rte) ? ro. hardwire d to 1 to indicate that the base address field in this register maps to i/o space. bit description 15:0 subsystem vendor id (svid) ? r/wo. bios sets the value in this register to identify the subsystem vendor id. the usb_svid register, in combination with the usb subsystem id register, enable s the operating system to distinguish each subsystem from the others. note: the software can write to this register only once per core well reset. writes should be done as a single, 16-bit cycle. intel ? ich8 family datasheet 571 uhci controllers registers 14.1.13 sid ? subsystem id entification register (usb?d29:f0/f1/f2/f3, d26:f0/f1) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 14.1.14 int_ln?interrupt line register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 14.1.15 int_pn?interrupt pin register (usb?d29:f0/f1/f2/f3, d26:f0/f1) address offset: 3dh attribute: ro default value: see description size: 8 bits bit description 15:0 subsystem id (sid) ? r/wo. bios sets the value in this register to identify the subsystem id. the sid register, in combination with the svid register (d29:f0/f1/f2, d26:f0/f1:2c), enables the operating system to distinguish each subsystem from other(s). the value read in this register is the same as what was written to the ide_sid register. note: the software can write to this register only once per core well reset. writes should be done as a single, 16-bit cycle. bit description 7:0 interrupt line (int_ln) ? ro. this data is not used by the ich8. it is to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:0 interrupt line (int_ln) ? ro. this value tells the software which interrupt pin each usb host controller uses. the upper 4 bits are hardwired to 0000b; the lower 4 bits are determine by the interrupt pi n default values that are programmed in the memory- mapped configuration space as follows: uhci #1 - d29ip.u0p (chipset config registers:offset 3108:bits 3:0) uhci #2 - d29ip.u1p (chipset config registers:offset 3108:bits 7:4) uhci #3 - d29ip.u2p (chipset config registers:offset 3108:bits 11:8) uhci #4 - d26ip.u0p (chipset config registers:offset 3114:bits 3:0) uhci #5 - d26ip.u1p (chipset config registers:offset 3114:bits 7:4) note: this does not determine the mapping to the pirq pins. uhci controllers registers 572 intel ? ich8 family datasheet 14.1.16 usb_relnum?serial bus release number register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: 60h attribute: ro default value: 10h size: 8 bits 14.1.17 usb_legkey?usb legacy keyboard/mouse control register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: c0h ? c1h attribute: r/w, r/wc, ro default value: 2000h size: 16 bits this register is implemented separately in each of the usb uhci functions. however, the enable and status bits for the trapping logic are or?d and shared, respectively, since their functionality is not spec ific to any one host controller. bit description 7:0 serial bus release number ? ro. 10h = usb controller supports the usb specification , release 1.0. bit description 15 smi caused by end of pa ss-through (smibyendps) ? r/wc. this bit indicates if the event occurred. note that even if the co rresponding enable bit is not set in bit 7, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred 14 reserved 13 pci interrupt enable (usbpirqen) ? r/w. this bit is used to prevent the usb controller from generating an interrupt due to transactions on its ports. note that, when disabled, it will probably be configured to generate an smi using bi t 4 of this register. default to 1 for compatibilit y with older usb software. 0 = disable 1 = enable 12 smi caused by usb interrupt (smibyusb) ? ro. this bit indicates if an interrupt event occurred from this controller. the inte rrupt from the controller is taken before the enable in bit 13 has any effect to create this read-only bit. no te that even if the corresponding enable bit is not set in bit 4, this bit may still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software should clear the interrupts via th e usb controllers. writing a 1 to this bit will have no effect. 1 = event occurred. 11 smi caused by port 64 write (trapby64w) ? r/wc. this bit indicates if the event occurred. note that even if th e corresponding enable bit is not set in bit 3, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. intel ? ich8 family datasheet 573 uhci controllers registers 10 smi caused by port 64 read (trapby64r) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding en able bit is not set in bit 2, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 9 smi caused by port 60 write (trapby60w) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding en able bit is not set in bit 1, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 8 smi caused by port 60 read (trapby60r) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. it is up to the sm m code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 7 smi at end of pass-through enable (smiatendps) ? r/w. this bit enables smi at the end of a pass-through. this can occur if an smi is generated in the middle of a pass-through, and needs to be serviced later. 0 = disable 1 = enable 6 pass through state (pstate) ? ro. 0 = if software needs to reset this bit, it should set bit 5 in all of the host controllers to 0. 1 = indicates that the state machine is in the middle of an a20gate pass-through sequence. 5 a20gate pass-through enable (a20passen) ? r/w. 0 = disable. 1 = enable. allows a20gate sequence pass-through function. a specific cycle sequence involving writes to port 60h and 64h does no t result in the setting of the smi status bits. 4 smi on usb irq enable (usbsmien) ? r/w. 0 = disable 1 = enable. usb interrupt will cause an smi event. 3 smi on port 64 writes enable (64wen) ? r/w. 0 = disable 1 = enable. a 1 in bit 11 will cause an smi event. 2 smi on port 64 reads enable (64ren) ? r/w. 0 = disable 1 = enable. a 1 in bit 10 will cause an smi event. 1 smi on port 60 writes enable (60wen) ? r/w. 0 = disable 1 = enable. a 1 in bit 9 will cause an smi event. 0 smi on port 60 reads enable (60ren) ? r/w. 0 = disable 1 = enable. a 1 in bit 8 will cause an smi event. bit description uhci controllers registers 574 intel ? ich8 family datasheet 14.1.18 usb_res?usb resu me enable register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: c4h attribute: r/w default value: 00h size: 8 bits 14.1.19 cwp?core well policy register (usb?d29:f0/f1/f2, d26:f0/f1) address offset: c8h attribute: r/w default value: 00h size: 8 bits bit description 7:2 reserved 1 port1en ? r/w. enable port 1 of the usb controller to respond to wakeup events. 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/ disconnect events. 0 port0en ? r/w. enable port 0 of the usb controller to respond to wakeup events. 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/ disconnect events. bit description 7:1 reserved 0 static bus master status policy enable (sbmspe) ? r/w. 0 = the uhci host controller dynamically sets the bus master status bit (power management 1 status register,[pmbase +00h], bit 4) based on the memory accesses that are sc heduled. for mobile components, the default setting provides a more accurate indication of snoopable me mory accesses in order to help with software-invoked entry to c3 and c4 power states. 1 = the uhci host controller statically fo rces the bus master status bit in power management space to 1 whenever the hchalted bit (usb status register, base+02h, bit 5) is cleared. note: the pci power management registers are enabled in the pci device 31: function 0 space (pm_io_en), and can be moved to any i/o location (128-byte aligned). intel ? ich8 family datasheet 575 uhci controllers registers 14.2 usb i/o registers some of the read/write register bits that deal with changing the state of the usb hub ports function such that on read back they reflect the current state of the port, and not necessarily the state of the last write to the register. this allows the software to poll the state of the port and wait until it is in the proper state before proceeding. a host controller reset, global reset, or port rese t will immediately terminate a transfer on the affected ports and disable the port. this affects the usbcmd register, bit 4 and the portsc registers, bits [12,6,2]. see individual bit descriptions for more detail. notes: 1. these registers are word writable only. byte writes to these registers have unpredictable effects. table 131. usb i/o registers base + offset mnemonic register name default type 00?01h usbcmd usb command 0000h r/w 02?03h usbsts usb status 0020h r/wc 04?05h usbintr usb interrupt enable 0000h r/w 06?07h frnum frame number 0000h r/w (see note 1) 08?0bh frbaseadd frame list base address undefined r/w 0ch sofmod start of frame modify 40h r/w 0d?0fh ? reserved ? ? 10?11h portsc0 port 0 status/control 0080h r/wc, ro, r/w (see note 1) 12?13h portsc1 port 1 status/control 0080h r/wc, ro, r/w (see note 1) uhci controllers registers 576 intel ? ich8 family datasheet 14.2.1 usbcmd?usb command register i/o offset: base + (00h ? 01h) attribute: r/w default value: 0000h size: 16 bits the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. table 132 provides additional information on the op eration of the run/stop and debug bits. bit description 15:7 reserved 8 loop back test mode ? r/w. 0 = disable loop back test mode. 1 = ich8 is in loop back test mode. when both ports are co nnected together, a write to one port will be seen on the other port and the data will be stored in i/o offset 18h. 7 max packet (maxp) ? r/w. this bit selects the maximum packet size that can be used for full speed bandwidth re clamation at the end of a fram e. this value is used by the host controller to determine whether it should initiate another transaction based on the time remaining in the sof counter. us e of reclamation packets larger than the programmed size will cause a babble error if executed during the critical window at frame end. the babble error results in the of fending endpoint being st alled. software is responsible for ensuring that any packet which could be executed under bandwidth reclamation be within this size limit. 0 = 32 bytes 1 = 64 bytes 6 configure flag (cf) ? r/w. this bit has no effect on the hardware. it is provided only as a semaphore service for software. 0 = indicates that software has not co mpleted host controller configuration. 1 = hcd software sets this bit as the last action in its process of configuring the host controller. 5 software debug (swdbg) ? r/w. the swdbg bit must only be manipulated when the controller is in the stopped state. this can be determined by checking the hchalted bit in the usbsts register. 0 = normal mode. 1 = debug mode. in sw debug mode, the host controller clears th e run/stop bit after the completion of each usb transaction. the next transaction is executed when software sets the run/stop bit back to 1. 4 force global resume (fgr) ? r/w. 0 = software resets this bit to 0 after 20 ms has elapsed to stop sending the global resume signal. at that time all usb devices should be ready for bus activity. the 1 to 0 transition causes the port to send a low speed eop signal. this bit will remain a 1 until the eop has completed. 1 = host controller sends the global resume si gnal on the usb, and sets this bit to 1 when a resume event (connect, disconnect, or k-state) is detected while in global suspend mode. 3 enter global suspend mode (egsm) ? r/w. 0 = software resets this bit to 0 to come ou t of global suspend mode. software writes this bit to 0 at the same time that force global resume (bit 4) is written to 0 or after writing bit 4 to 0. 1 = host controller enters the global suspen d mode. no usb transactions occur during this time. the host controller is able to receive resume signals from usb and interrupt the system. software must ensure that the run/stop bit (bit 0) is cleared prior to setting this bit. intel ? ich8 family datasheet 577 uhci controllers registers 2 global reset (greset) ? r/w. 0 = this bit is reset by the software after a minimum of 10 ms has elapsed as specified in chapter 7 of th e usb specification. 1 = global reset. the host controller sends the global reset signal on the usb and then resets all its logic, including the internal hub registers. the hub registers are reset to their power on state. chip hardware re set has the same effe ct as global reset (bit 2), except that the host controller does not send the global reset on usb. 1 host controller reset (hcreset) ? r/w. the effects of hcreset on hub registers are slightly different from chip hardware reset and global usb reset. the hcreset affects bits [8,3:0] of the po rt status and control regist er (portsc) of each port. hcreset resets the state machines of the host controller including the connect/ disconnect state machine (one for each port). when the connect/disconnect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signalin g a disconnect, even if a device is attached to the port. this virtual disconnect causes the port to be disabled. this disconnec t and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the portsc to get set. the disconnect also caus es bit 8 of portsc to reset. about 64 bit times after hcreset goes to 0, the connect and low-speed detect wi ll take place, and bits 0 and 8 of the portsc will change accordingly. 0 = reset by the host controller wh en the reset process is complete. 1 = reset. when this bit is set, the host controller module re sets its inte rnal timers, counters, state machines, etc. to their in itial value. any transaction currently in progress on usb is im mediately terminated. 0 run/stop (rs) ? r/w. when set to 1, the ich8 proceeds with execution of the schedule. the ich8 continues execution as long as this bit is set. when this bit is cleared, the ich8 completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. the host contro ller clears this bit when the following fatal errors occur: cons istency check failure, pci bus errors. 0 = stop 1 = run note: this bit should only be cleared if there are no active transaction descriptors in the executable schedule or software will reset the host controller prior to setting this bit again. bit description uhci controllers registers 578 intel ? ich8 family datasheet when the usb host controller is in software debug mode (usbcmd register bit 5=1), the single stepping software debug operation is as follows: to enter software debug mode: 1. hcd puts host controller in stop state by setting the run/stop bit to 0. 2. hcd puts host controller in debug mode by setting the swdbg bit to 1. 3. hcd sets up the correct command list and start of frame value for starting point in the frame list single step loop. 4. hcd sets run/stop bit to 1. 5. host controller executes next active td, sets run/stop bit to 0, and stops. 6. hcd reads the usbcmd register to check if the single step execution is completed (hchalted=1). 7. hcd checks results of td execution. go to step 4 to execute next td or step 8 to end software debug mode. 8. hcd ends software debug mode by setting swdbg bit to 0. 9. hcd sets up normal command list and frame list table. 10. hcd sets run/stop bit to 1 to resume normal schedule execution. in software debug mode, when the run/stop bit is set, the host controller starts. when a valid td is found, the run/stop bi t is reset. when the td is finished, the hchalted bit in the usbsts register (bit 5) is set. the sw debug mode skips over inactive tds an d only halts after an active td has been executed. when the last active td in a frame has been executed, the host controller waits until the next sof is sent and then fetc hes the first td of the next frame before halting. table 132. run/stop, debug bit interaction sw dbg (bit 5), run/stop (bit 0) operation swdbg (bit 5) run/stop (bit 0) description 0 0 if executing a command, the host controller completes the command and then stops. the 1.0 ms frame counter is reset and command list execution resumes from start of fr ame using the frame list pointer selected by the current value in the frnum register. (while run/ stop=0, the frnum register (bas e + 06h) can be reprogrammed). 0 1 execution of the command list resumes from start of frame using the frame list pointer selected by the current value in the frnum register. the host controller remains running until the run/stop bit is cleared (by software or hardware). 1 0 if executing a command, the host controller completes the command and then stops and the 1.0 ms fram e counter is frozen at its current value. all status are preserved. the host controller begins execution of the command list from where it le ft off when the run/stop bit is set. 1 1 execution of the command list resumes from where the previous execution stopped. the run/stop bit is set to 0 by the host controller when a td is being fetched. this ca uses the host controller to stop again after the execution of the td (single step). when the host controller has completed execution, the hc halted bit in the status register is set. intel ? ich8 family datasheet 579 uhci controllers registers this hchalted bit can also be used outside of software debug mode to indicate when the host controller has detected the run/stop bit and has completed the current transaction. outside of the software debug mode, setting the run/stop bit to 0 always resets the sof counter so that when the run/stop bit is set the host controller starts over again from the frame list location pointed to by the frame list index (see frnum register description) rather than continuing where it stopped. 14.2.2 usbsts?usb status register i/o offset: base + (02h ? 03h) attribute: r/wc default value: 0020h size: 16 bits this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. bit description 15:6 reserved 5 hchalted ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = the host controller has stopped executing as a result of the r un/stop bit being set to 0, either by software or by the host controller hardware (debug mode or an internal error). default. 4 host controller process error ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = the host controller has detected a fatal e rror. this indicates that the host controller suffered a consistency check failure while processing a transfer descriptor. an example of a consistency check failure woul d be finding an invalid pid field while processing the packet header portion of the td. when this e rror occurs, the host controller clears the run/stop bit in the command register (d29:f0/f1/f2, d26:f0/f1:base + 00h, bit 0) to prevent further schedule exec ution. a hardware interrupt is generated to the system. 3 host system error ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = a serious error occurred duri ng a host system access involving the host controller module. in a pci system, conditions that se t this bit to 1 include pci parity error, pci master abort, and pci target abort. wh en this error occurs, the host controller clears the run/stop bit in the command re gister to prevent further execution of the scheduled tds. a hardware inte rrupt is generated to the system. 2 resume detect (rsm_det) ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = the host controller received a ?resume? signal from a usb device. this is only valid if the host controller is in a global suspend state (command register, d29:f0/ f1/f2, d26:f0/f1:base + 00h, bit 3 = 1). 1 usb error interrupt ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = completion of a usb transaction resulted in an error condition (e.g., error counter underflow). if the td on which the erro r interrupt occurred al so had its ioc bit (d29:f0/f1/f2, d26:f0/f1:base + 04h, bit 2) set, both this bit and bit 0 are set. 0 usb interrupt (usbint) ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = the host controller sets this bit when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. also set when a short packet is detected (actual length field in td is less than maximum length field in td), and short packet detection is enabled in that td. uhci controllers registers 580 intel ? ich8 family datasheet 14.2.3 usbintr?usb interrupt enable register i/o offset: base + (04h ? 05h) attribute: r/w default value: 0000h size: 16 bits this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. fatal errors (host controller processor error, (d29:f0/f1/f2, d26:f0/f1:base + 02h, bit 4, usbsts register) cannot be disabled by the host controller. interrupt sources that are disabled in this register still appear in the status register to allow the software to poll for events. 14.2.4 frnum?frame number register i/o offset: base + (06 ? 07h) attribute: r/w (writes must be word writes) default value: 0000h size: 16 bits bits [10:0] of this register contain the current frame number that is included in the frame sof packet. this register reflects the count value of the internal frame number counter. bits [9:0] are used to select a particular entry in the frame list during scheduled execution. this register is updated at the end of each frame time. this register must be written as a word. by te writes are not supported. this register cannot be written unless the host controller is in the stopped state as indicated by the hchalted bit (d29:f0/f1/f2/, d26:f0/f1:base + 02h, bit 5). a write to this register while the run/stop bit is set (d29:f0/f1/f2/, d26:f0/f1:base + 00h, bit 0) is ignored. bit description 15:5 reserved 4 scratchpad (sp) ? r/w. 3 short packet interrupt enable ? r/w. 0 = disabled. 1 = enabled. 2 interrupt on complete enable (ioc) ? r/w. 0 = disabled. 1 = enabled. 1 resume interrupt enable ? r/w. 0 = disabled. 1 = enabled. 0 timeout/crc interrupt enable ? r/w. 0 = disabled. 1 = enabled. bit description 15:11 reserved 10:0 frame list current index/frame number ? r/w. this field provides the frame number in the sof frame. the value in this register increments at the end of each time frame (approximately every 1 ms). in addition, bits [9:0] are used for the frame list current index and correspond to memory address signals [11:2]. intel ? ich8 family datasheet 581 uhci controllers registers 14.2.5 frbaseadd?frame list base address register i/o offset: base + (08h ? 0bh) attribute: r/w default value: undefined size: 32 bits this 32-bit register contains the beginning address of the frame list in the system memory. hcd loads this register prior to starting the schedule execution by the host controller. when written, only the upper 20 bits are used. the lower 12 bits are written as 0?s (4 kb alignment). the contents of this register are combined with the frame number counter to enable the host contro ller to step through the frame list in sequence. the two least significant bits are always 00. this requires dword-alignment for all list entries. this configuration supports 1024 frame list entries. 14.2.6 sofmod?start of frame modify register i/o offset: base + (0ch) attribute: r/w default value: 40h size: 8 bits this 1-byte register is used to modify the va lue used in the generation of sof timing on the usb. only the 7 least significant bits are used. when a new value is written into these 7 bits, the sof timing of the next fr ame will be adjusted. this feature can be used to adjust out any offset from the clock source that generates the clock that drives the sof counter. this register can also be used to maintain real time synchronization with the rest of the system so that all devi ces have the same sense of real time. using this register, the frame length can be adju sted across the full range required by the usb specification. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. it may be reprogrammed by usb sy stem software at any time. its value will take effect from the beginning of the next frame. this register is reset upon a host controller reset or global reset. software must maintain a copy of its value for reprogramming if necessary. bit description 31:12 base address ? r/w. these bits correspond to memory address signals [31:12], respectively. 11:0 reserved bit description 7 reserved 6:0 sof timing value ? r/w. guidelines for the modifica tion of frame time are contained in chapter 7 of the usb specification. the sof cycle time (number of sof counter clock periods to generate a sof frame length) is equal to 11936 + value in this field. the default value is decimal 64 which gives a sof cycle time of 12000. for a 12 mhz sof counter clock input, this produces a 1 ms frame period. the following table indicates what sof timing value to program into this field for a certain frame period. f rame l eng th (# 12 mh z clocks) (decimal) sof ti m i ng v a l ue (thi s reg i s t er ) (decimal) 11936 0 11937 1 ? ? 11999 63 12000 64 12001 65 ? ? 12062 126 12063 127 uhci controllers registers 582 intel ? ich8 family datasheet 14.2.7 portsc[0,1]?port status and control register i/o offset: port 0/2/4/6/8: base + (10h ? 11h) attribute:r/wc, ro, port 1/3/5/7/9: base + (12h ? 13h) r/w (word writes only) default value: 0080h size:16 bits note: for uhci #1 (d29:f0), this applies to ich8 usb ports 0 and 1; for uhci #2 (d29:f1), this applies to ich8 usb ports 2 and 3; for uhci #3 (d29:f2), this applies to ich8 usb ports 4 and 5, for uhci #4 (d26:f0), this applies to ich8 usb ports 6 and 7, and for uhci #5 (d26:f1), this applies to ich8 usb ports 8 and 9. after a power-up reset, global reset, or host controller reset, the initial conditions of a port are: no device connected, port disabled, and the bus line status is 00 (single- ended 0). port reset and enable sequence when software wishes to reset a usb device it will assert the port reset bit in the port status and control register. the minimum reset signaling time is 10 ms and is enforced by software. to complete the reset sequence, software clears the port reset bit. the intel uhci controller must re-detect the port connect after reset signaling is complete before the controller will allow the port enable bit to de set by software. this time is approximately 5.3 us. software has several possible options to meet the timing requirement and a partial list is enumerated below: ? iterate a short wait, setting the port enab le bit and reading it back to see if the enable bit is set. ? poll the connect status bit and wait for the hardware to recognize the connect prior to enabling the port. ? wait longer than the hardware detect time after clearing the port reset and prior to enabling the port. intel ? ich8 family datasheet 583 uhci controllers registers bit description 15:13 reserved ? ro. 12 suspend ? r/w this bit should not be written to a 1 if global suspend is active (bit 3=1 in the usbcmd register). bit 2 and bi t 12 of this register define the hub states as follows: when in suspend state, downst ream propagation of data is blocked on this port, except for single-ended 0 resets (global reset and po rt reset). the blocking occurs at the end of the current transaction, if a transaction wa s in progress when this bit was written to 1. in the suspend state, the port is sensit ive to resume detectio n. note that the bit status does not change until the port is suspended and th at there may be a delay in suspending a port if there is a transa ction currently in pr ogress on the usb. 1 = port in suspend state. 0 = port not in suspend state. note: normally, if a transaction is in progress when this bit is set, the port will be suspended when the current transaction completes. however, in the case of a specific error condition (out transact ion with babble), the ich8 may issue a start-of-frame, and then suspend the port. 11 overcurrent indicator ? r/wc. set by hardware. 0 = software clears this bit by writing a 1 to it. 1 = overcurrent pin has gone from in active to active on this port. 10 overcurrent active ? ro. this bit is set and cleared by hardware. 0 = indicates that the overcurre nt pin is inactive (high). 1 = indicates that the overcurrent pin is active (low). 9 port reset ? r/w 0 = port is not in reset. 1 = port is in reset. when set, the port is disabled and sends the usb reset signaling. 8 low speed device attached (ls) ? ro 0 = full speed device is attached. 1 = low speed device is attached to this port. 7 reserved ? ro. always read as 1. 6 resume detect (rsm_det) ? r/w. software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected for at least 32 microseconds while the port is in the suspend state. the ich8 will then reflect the k-state back onto the bus as long as the bit remains a 1, and the port is still in the suspend state (bit 12,2 are ?11?). writing a 0 (from 1) causes the port to send a low speed eop. this bit will remain a 1 until the eop has completed. 0 = no resume (k-state) detected/driven on port. 1 = resume detected /driven on port. 5:4 line status ? ro these bits reflect the d+ (bit 4) an d d? (bit 5) signals lines? logical levels. these bits are used for fault detect an d recovery as well as for usb diagnostics. this field is updated at eof2 time (see chapter 11 of the usb specification). 3 port enable/disable change ? r/wc for the root hub, this bit gets set only when a port is disabled due to disconnect on that port or due to the appropriate conditions existing at the eof2 point (see ch apter 11 of the usb specification). 0 = no change. software clears this bi t by writing a 1 to the bit location. 1 = port enabled/ disabled status has changed. bits [12,2] hub state x,0 disable 0, 1 enable 1, 1 suspend uhci controllers registers 584 intel ? ich8 family datasheet 2 port enabled/disabled (port_en) ? r/w ports can be enabled by host software only. ports can be disabled by either a faul t condition (disconnect event or other fault condition) or by host software . note that the bit status does not change until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction currently in progress on the usb. 0 = disable 1 = enable 1 connect status change ? r/wc this bit indicates that a change has occurred in the port?s current connect status (see bit 0). the hub device se ts this bit for any changes to the port device connect status, even if system software has not cleared a connect status change. if, for example, the insert ion status changes twice before system software has cleared the change d condition, hub hardware wi ll be setting? an already- set bit (i.e., the bit will remain set). however, the hub transfers the change bit only once when the host controller requests a da ta transfer to the status change endpoint. system software is re sponsible for determining state change history in such a case. 0 = no change. software clears th is bit by writing a 1 to it. 1 = change in current connect status. 0 current connect status ? ro this value reflects the current state of the port, and may not correspond directly to the event th at caused the connect status change bit (bit 1) to be set. 0 = no device is present. 1 = device is present on port. bit description intel ? ich8 family datasheet 585 ehci controller registers (d29:f7, d26:f7) 15 ehci controller registers (d29:f7, d26:f7) 15.1 usb ehci configuration registers (usb ehci?d29:f7, d26:f7) note: register address locations that are not shown in table 133 should be treated as reserved (see section 6.2 for details). table 133. usb ehci pci register address ma p (usb ehci?d29:f7, d26:f7) (sheet 1 of 2) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0290h r/w, ro 08h rid revision identification see register description ro 09h pi programming interface 20h ro 0ah scc sub class code 03h ro 0bh bcc base class code 0ch ro 0dh pmlt primary master latency timer 00h ro 10h?13h mem_base memory base address 00000000h r/w, ro 2ch?2dh svid usb ehci subsystem vendor identification xxxxh r/w (special) 2eh?2fh sid usb ehci subsystem identification xxxxh r/w (special) 34h cap_ptr capabili ties pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 50h pwr_capid pci power management capability id 01h ro 51h nxt_ptr1 next item pointer 58h r/w (special) 52h?53h pwr_cap power management capabilities c9c2h r/w (special) 54h?55h pwr_cntl_sts power management control/status 0000h r/w, r/wc, ro 58h debug_capid debug port capability id 0ah ro 59h nxt_ptr2 next item pointer #2 00h ro ehci controller registers (d29:f7, d26:f7) 586 intel ? ich8 family datasheet note: all configuration registers in this section are in the core well and reset by a core well reset and the d3-to-d0 warm reset, except as noted. 15.1.1 vid?vendor identi fication register (usb ehci?d29:f7, d26:f7) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 15.1.2 did?device identi fication register (usb ehci?d29:f7, d26:f7) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 5ah?5bh debug_base debug port base offset 20a0h ro 60h usb_relnum usb release number 20h ro 61h fl_adj frame length adjustment 20h r/w 62h?63h pwake_cap port wake capabilities 01ffh r/w 64h?67h ? reserved ? ? 68h?6bh leg_ext_cap usb ehci legacy support extended capability 00000001h r/w, ro 6ch?6fh leg_ext_cs usb ehci legacy extended support control/status 00000000h r/w, r/wc, ro 70h?73h special_smi intel specific usb 2.0 smi 00000000h r/w, r/wc 74h?7fh ? reserved ? ? 80h access_cntl access control 00h r/w 84h ehciir1 ehci initialization register 1 (mobile only) 01h r/w, r/wl fc?ffh ehciir2 ehci initialization register 2 20001706 r/w table 133. usb ehci pci register address ma p (usb ehci?d29:f7, d26:f7) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id ? ro. this is a 16-b it value assigned to the intel ? ich8 usb ehci controller. refer to the intel ich8 family specification update for the value of the device id register. intel ? ich8 family datasheet 587 ehci controller registers (d29:f7, d26:f7) 15.1.3 pcicmd?pci co mmand register (usb ehci?d29:f7, d26:f7) address offset: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = the function is capable of genera ting interrupts. 1 = the function can not generate its interrupt to the interrupt controller. note that the corresponding interrupt status bit (d29:f7, d26:f7:06h, bit 3) is not affected by the interrupt enable. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. 0 = disables ehc?s capability to generate an serr#. 1 = the enhanced host controller (ehc) is capable of generating (internally) serr# when it receive a completion status other than ?succe ssful? for one of its dma- initiated memory reads on dmi (and su bsequently on its internal interface). 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? ro. hardwired to 0. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. 0 = disables this functionality. 1 = enables the ich8 to act as a mast er on the pci bus for usb transfers. 1 memory space enable (mse) ? r/w. this bit controls access to the usb 2.0 memory space registers. 0 = disables this functionality. 1 = enables accesses to the usb 2.0 registers. the base address register (d29:f7, d26:f7:10h) for usb 2.0 should be pr ogrammed before this bit is set. 0 i/o space enable (iose) ? ro. hardwired to 0. ehci controller registers (d29:f7, d26:f7) 588 intel ? ich8 family datasheet 15.1.4 pcists?pci status register (usb ehci?d29:f7, d26:f7) address offset: 06h ? 07h attribute: r/w, ro default value: 0290h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? ro. hardwired to 0. 14 signaled system error (sse) ? r/w. 0 = no serr# signaled by ich8. 1 = this bit is set by the ich8 when it sign als serr# (internally). the ser_en bit (bit 8 of the command register) must be 1 for this bit to be set. 13 received master abort (rma) ? r/w. 0 = no master abort received by ehc on a memory access. 1 = this bit is set when ehc, as a master, receives a master abort status on a memory access. this is treated as a host error and halts the dma engines. this event can optionally generate an serr# by setting the serr# enable bit . 12 received target abort (rta) ? r/w. 0 = no target abort received by ehc on memory access. 1 = this bit is set when ehc, as a master, re ceives a target abort status on a memory access. this is treated as a host error and halts the dma engines. this event can optionally generate an serr# by setting the serr# enable bit (d29:f7, d26:f7:04h, bit 8). 11 signaled target abort (sta) ? ro. this bit is used to indicate wh en the ehci function responds to a cycle with a target abort. there is no reason for this to happen, so this bit will be hardwired to 0. 10:9 devsel# timing status (devt_sts) ? ro. this 2-bit field defines the timing for devsel# assertion. 8 master data parity error detected (dped) ? r/w. 0 = no data parity error detected on usb2.0 read completion packet. 1 = this bit is set by the ich8 when a data parity error is detect ed on a usb 2.0 read completion packet on the internal interface to the ehci host controller and bit 6 of the command regist er is set to 1. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (u df) ? ro. hardwired to 0. 5 66 mhz capable (66 mhz _cap) ? ro. hardwired to 0. 4 capabilities list (cap _list) ? ro. hardwired to 1 indica ting that offset 34h contains a valid capabilities pointer. 3 interrupt status ? ro. this bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = this bit will be 0 when the interrupt is deasserted. 1 = this bit is a 1 when th e interrupt is asserted. the value reported in this bit is independen t of the value in the interrupt enable bit. 2:0 reserved intel ? ich8 family datasheet 589 ehci controller registers (d29:f7, d26:f7) 15.1.5 rid?revision identification register (usb ehci?d29:f7, d26:f7) offset address: 08h attribute: ro default value: see bit description size: 8 bits 15.1.6 pi?programming interface register (usb ehci?d29:f7, d26:f7) address offset: 09h attribute: ro default value: 20h size: 8 bits 15.1.7 scc?sub class code register (usb ehci?d29:f7, d26:f7) address offset: 0ah attribute: ro default value: 03h size: 8 bits 15.1.8 bcc?base clas s code register (usb ehci?d29:f7, d26:f7) address offset: 0bh attribute: ro default value: 0ch size: 8 bits bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 8 (ich8) family specification update for the value of the revision id register bit description 7:0 programming interface ? ro. a value of 20h indicates that this usb 2.0 host controller conforms to the ehci specification. bit description 7:0 sub class code (scc) ? ro. 03h = universal serial bus host controller. bit description 7:0 base class code (bcc) ? ro. 0ch = serial bus controller. ehci controller registers (d29:f7, d26:f7) 590 intel ? ich8 family datasheet 15.1.9 pmlt?primary master latency timer register (usb ehci?d29:f7, d26:f7) address offset: 0dh attribute: ro default value: 00h size: 8 bits 15.1.10 mem_base?memory ba se address register (usb ehci?d29:f7, d26:f7) address offset: 10h ? 13h attribute: r/w, ro default value: 00000000h size: 32 bits 15.1.11 svid?usb ehci subsys tem vendor id register (usb ehci?d29:f7, d26:f7) address offset: 2ch ? 2dh attribute: r/w (special) default value: xxxxh size: 16 bits reset: none bit description 7:0 master latency timer count (mltc) ? ro . hardwired to 00h. because the ehci controller is internally implemented with arbitration on an interface (and not pci), it does not need a master latency timer. bit description 31:10 base address ? r/w. bits [31:10] correspond to memory address signals [31:10], respectively. this gives 1-kb of locatable memory space aligned to 1-kb boundaries. 9:4 reserved 3 prefetchable ? ro. hardwired to 0 indicating that this range should not be prefetched. 2:1 type ? ro. hardwired to 00b indicating that this range can be mapped anywhere within 32-bit address space. 0 resource type indicator (rte) ? ro. hardwire d to 0 indicating that the base address field in this register maps to memory space. bit description 15:0 subsystem vendor id (svid) ? r/w (special). this register, in combination with the usb 2.0 subsystem id register, enables th e operating system to distinguish each subsystem from the others. note: writes to this register are enable d when the wrt_rdonly bit (d29:f7, d26:f7:80h, bit 0) is set to 1. intel ? ich8 family datasheet 591 ehci controller registers (d29:f7, d26:f7) 15.1.12 sid?usb ehci su bsystem id register (usb ehci?d29:f7, d26:f7) address offset: 2eh ? 2fh attribute: r/w (special) default value: xxxxh size: 16 bits reset: none 15.1.13 cap_ptr?capabilit ies pointer register (usb ehci?d29:f7, d26:f7) address offset: 34h attribute: ro default value: 50h size: 8 bits 15.1.14 int_ln?interrupt line register (usb ehci?d29:f7, d26:f7) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 15.1.15 int_pn?interrupt pin register (usb ehci?d29:f7, d26:f7) address offset: 3dh attribute: ro default value: see description size: 8 bits bit description 15:0 subsystem id (sid) ? r/w (special). bios sets the va lue in this register to identify the subsystem id. this register, in combination with th e subsystem vendor id register, enables the operating system to distinguish each subsystem from other(s). note: writes to this register are enabled when the wrt_rdonly bit (d29:f7, d26:f7:80h, bit 0) is set to 1. bit description 7:0 capabilities pointer (cap_ptr) ? ro. this register points to the starting offset of the usb 2.0 capabilities ranges. bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich8. it is used as a scratchpad register to communicate to software th e interrupt line that the interrupt pin is connected to. bit description 7:0 interrupt pin ? ro. this reflects the value of d29ip.eip (chipset config registers:offset 3108:bits 31:28) or d26ip.eip (chipset config registers:offset 3114:bits 31:28). note: bits 7:4 are always 0h ehci controller registers (d29:f7, d26:f7) 592 intel ? ich8 family datasheet 15.1.16 pwr_capid?pci power management capability id register (usb ehci?d29:f7, d26:f7) address offset: 50h attribute: ro default value: 01h size: 8 bits 15.1.17 nxt_ptr1?next item pointer #1 register (usb ehci?d29:f7, d26:f7) address offset: 51h attribute: r/w (special) default value: 58h size: 8 bits bit description 7:0 power management capability id ? ro. a va lue of 01h indicates that this is a pci power management ca pabilities field. bit description 7:0 next item pointer 1 value ? r/w (special). this regi ster defaults to 58h, which indicates that the next capa bility registers begin at co nfiguration offset 58h. this register is writable when the wrt_rdonly bit (d29:f7, d26:f7:80h, bit 0) is set. this allows bios to effectively hide the debug port capability registers, if necessary. this register should only be written during sy stem initialization before the plug-and-play software has enabled any master-initiated tr affic. only values of 58h (debug port visible) and 00h (debug port invisible) are expected to be programmed in this register. note: register not reset by d3-to-d0 warm reset. intel ? ich8 family datasheet 593 ehci controller registers (d29:f7, d26:f7) 15.1.18 pwr_cap?power manageme nt capabilities register (usb ehci?d29:f7, d26:f7) address offset: 52h ? 53h attribute: r/w (special), ro default value: c9c2h size: 16 bits notes: 1. normally, this register is read-only to re port capabilities to the power management software. to report different power management capabilities, dependin g on the system in which the ich8 is used, bits 15:11 and 8:6 in this register are writable when the wrt_rdonly bit (d29:f7, d26:f7:80h, bit 0) is set. the value written to this register does not affect the hardware other than changi ng the value returned during a read. 2. reset: core well, but not d3-to-d0 warm reset. bit description 15:11 pme support (pme_sup) ? r/w (special). this 5-bit field indica tes the power states in which the function ma y assert pme#. the intel ? ich8 ehc does not support the d1 or d2 states. for all other states, the ich8 ehc is capable of generating pme#. software should never need to modify this field. 10 d2 support (d2_sup) ? ro. 0 = d2 state is not supported 9 d1 support (d1_sup) ? ro. 0 = d1 state is not supported 8:6 auxiliary current (aux_cur) ? r/w (special) . the ich8 ehc reports 375 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi )? ro. the ich8 reports 0, indicating that no device-specific initialization is required. 4 reserved 3 pme clock (pme_clk) ? ro. the ich8 reports 0, indicating that no pci clock is required to generate pme#. 2:0 version (ver) ? ro. the ich8 reports 010b, indicating that it complies with revision 1.1 of the pci power management specification. ehci controller registers (d29:f7, d26:f7) 594 intel ? ich8 family datasheet 15.1.19 pwr_cntl_sts?power management control/ status register (usb ehci?d29:f7, d26:f7) address offset: 54h ? 55h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits note: reset (bits 15, 8): suspend well, and not d3 -to-d0 warm reset no r core well reset. bit description 15 pme status ? r/wc. 0 = writing a 1 to this bit will clear it and cause the internal pme to deassert (if enabled). 1 = this bit is set when the ich8 ehc wo uld normally assert the pme# signal independent of the state of the pme_en bit. note: this bit must be explicitly cleared by the operating system each time the operating system is loaded. 14:13 data scale ? ro. hardwired to 00b indicating it does not support the associated data register. 12:9 data select ? ro. hardwired to 0000b indicating it does not support the associated data register. 8 pme enable ? r/w. 0 = disable. 1 = enable. enables intel ? ich8 ehc to generate an internal pme signal when pme_status is 1. note: this bit must be explicitly cleared by the operating system each time it is initially loaded. 7:2 reserved 1:0 power state ? r/w. this 2-bit field is used both to determine the cu rrent power state of ehc function and to set a new power state. the definition of the field values are: 00 = d0 state 11 = d3 hot state if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. when in the d3 hot state, the ich8 must not accept accesses to the ehc memory range; but the configuration space must still be accessible. when not in the d0 state, the generation of the interrupt output is bloc ked. specifically, the pirqh is not asserted by the ich8 when not in the d0 state. when software changes this value from the d3 hot state to the d0 state, an internal warm (soft) reset is gene rated, and software must re-initialize the function. intel ? ich8 family datasheet 595 ehci controller registers (d29:f7, d26:f7) 15.1.20 debug_capid?debug port capability id register (usb ehci?d29:f7, d26:f7) address offset: 58h attribute: ro default value: 0ah size: 8 bits 15.1.21 nxt_ptr2?next item pointer #2 register (usb ehci?d29:f7, d26:f7) address offset: 59h attribute: ro default value: 00h size: 8 bits 15.1.22 debug_base?debug port base offset register (usb ehci?d29:f7, d26:f7) address offset: 5ah ? 5bh attribute: ro default value: 20a0h size: 16 bits 15.1.23 usb_relnum?usb re lease number register (usb ehci?d29:f7, d26:f7) address offset: 60h attribute: ro default value: 20h size: 8 bits bit description 7:0 debug port capability id ? ro. hardwired to 0ah indicating that this is the start of a debug port capability structure. bit description 7:0 next item pointer 2 capability ? ro. hardwi red to 00h to indicate there are no more capability structures in this function. bit description 15:13 bar number ? ro. hardwired to 001b to indicate the memory bar begins at offset 10h in the ehci configuration space. 12:0 debug port offset ? ro. hardwired to 0a0h to indica te that the debug port registers begin at offset a0h in the ehci memory range. bit description 7:0 usb release number ? ro. a value of 20h indicates that this controller follows universal serial bus (usb) sp ecification, revision 2.0 . ehci controller registers (d29:f7, d26:f7) 596 intel ? ich8 family datasheet 15.1.24 fl_adj?frame length adjustment register (usb ehci?d29:f7, d26:f7) address offset: 61h attribute: r/w default value: 20h size: 8 bits this feature is used to adjust any offset from the clock source that generates the clock that drives the sof counter. when a new value is written into these six bits, the length of the frame is adjusted. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. this register should only be modified when the hcha lted bit (d29:f7, d26:f7:caplength + 24h, bit 12) in the usb2.0_sts register is a 1. changing value of this register while the host controller is operating yields undefined resu lts. it should not be reprogrammed by usb system software unless the default or bios programmed values are incorrect, or the system is restoring the register while returning from a suspended state. these bits in suspend well and not reset by a d3-to-d0 warm rest or a core well reset. bit description 7:6 reserved ? ro. these bits are reserved for future use and sh ould read as 00b. 5:0 frame length timing value ? r/w. each decimal value change to this register corresponds to 16 high-speed bit times. th e sof cycle time (number of sof counter clock periods to generate a sof micro-frame length) is equal to 59488 + value in this field. the default value is decimal 32 (20h), which gives a sof cycle time of 60000. frame length (# 480 mhz clocks) (decimal) frame length timing value (this register) (decimal) 59488 0 59504 1 59520 2 ? ? 59984 31 60000 32 ? ? 60480 62 60496 63 intel ? ich8 family datasheet 597 ehci controller registers (d29:f7, d26:f7) 15.1.25 pwake_cap?port wake capability register (usb ehci?d29:f7, d26:f7) address offset: 62 ? 63h attribute: r/w default value: 01ffh size: 16 bits this register is in the suspend power well. the intended use of this register is to establish a policy about which ports are to be used for wake events. bit positions 1? 6(d29) or 1?4(d26) in the mask correspon d to a physical port implemented on the current ehci controller. a 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/ connect or overcurrent events as wake-up events. this is an information-only mask register. the bits in this register do not affect the actual operation of the ehci host controller. the system-specific policy can be established by bios initializing this register to a system-specific value. system software uses the information in this register when enabling devices and ports for remote wake-up. these bits are not reset by a d3-to-d0 warm rest or a core well reset. 15.1.26 leg_ext_cap?usb ehci legacy support extended capability register (u sb ehci?d29:f7, d26:f7) address offset: 68 ? 6bh attribute: r/w, ro default value: 00000001h size: 32 bits power well: suspend note: these bits are not reset by a d3-to-d0 warm rest or a core well reset. bit description 15:7 (d29) 15:5 (d26) reserved ? ro. 6:1 (d29) 4:1 (d26) port wake up capability mask ? r/w. bit positions 1 through 6 (device 29) or 1 through 4 (device 26) correspond to a physical port im plemented on this host controller. for example, bit position 1 corresponds to port 1, bit position 2 corresponds to port 2, etc. 0 port wake implemented ? r/w. a 1 in this bit indicates that this register is implemented to software. bit description 31:25 reserved ? ro. hardwired to 00h 24 hc os owned semaphore ? r/w. system software sets this bit to request ownership of the ehci controller. ownership is obtained when this bit reads as 1 and the hc bios owned semaphore bit reads as clear. 23:17 reserved ? ro. hardwired to 00h 16 hc bios owned semaphore ? r/w. the bios sets this bit to establish ownership of the ehci controller. system bios will clea r this bit in response to a request for ownership of the ehci contro ller by system software. 15:8 next ehci capability pointer ? ro. hardwired to 00h to indicate that there are no ehci extended capability st ructures in this device. 7:0 capability id ? ro. hardwired to 01h to indicate th at this ehci extended capability is the legacy support capability. ehci controller registers (d29:f7, d26:f7) 598 intel ? ich8 family datasheet 15.1.27 leg_ext_cs?usb ehci legacy support extended control / status register (usb ehci?d29:f7, d26:f7) address offset: 6c ? 6fh attribute: r/w, r/wc, ro default value: 00000000h size: 32 bits power well: suspend note: these bits are not reset by a d3-to- d0 warm rest or a core well reset. bit description 31 smi on bar ? r/wc. software clears this bit by writing a 1 to it. 0 = base address regist er (bar) not written. 1 = this bit is set to 1 when the base address register (bar) is written. 30 smi on pci command ? r/wc. software clears this bit by writing a 1 to it. 0 = pci command (pcicmd) register not written. 1 = this bit is set to 1 when the pci command (pcicmd) re gister is written. 29 smi on os ownership change ? r/wc. software clears this bit by writing a 1 to it. 0 = no hc os owned semaphore bit change. 1 = this bit is set to 1 when the hc os owned semaphore bit in the leg_ext_cap register (d29:f7, d26:f7:68h, bit 24) transitions from 1 to 0 or 0 to 1. 28:22 reserved ? ro. hardwired to 00h 21 smi on async advance ? ro. this bit is a shadow bit of the interrupt on async advance bit (d29:f7, d26:f7:caplength + 24 h, bit 5) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the interrupt on async advance bit in the usb2.0_sts register. 20 smi on host system error ? ro. this bit is a shadow bit of host system error bit in the usb2.0_sts register (d29:f7, d26:f7:caplength + 24h, bit 4). note: to clear this bit system so ftware must write a 1 to th e host system error bit in the usb2.0_sts register. 19 smi on frame list rollover ? ro. this bit is a shadow bit of frame list rollover bit (d29:f7, d26:f7:caplength + 24h, bi t 3) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the frame list rollover bit in the usb2.0_sts register. 18 smi on port change detect ? ro. this bit is a shadow bi t of port chan ge detect bit (d29:f7, d26:f7:caplength + 24h, bi t 2) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the port change detect bit in the usb2.0_sts register. 17 smi on usb error ? ro. this bit is a shadow bit of usb error interrupt (usberrint) bit (d29:f7, d26:f7:caplength + 24h, bit 1) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the usb error interrupt bit in the usb2.0_sts register. 16 smi on usb complete ? ro. this bit is a shadow bit of usb interrupt (usbint) bit (d29:f7, d26:f7:caplength + 24h, bi t 0) in the usb2.0_sts register. note: to clear this bit system so ftware must write a 1 to th e usb interrupt bit in the usb2.0_sts register. intel ? ich8 family datasheet 599 ehci controller registers (d29:f7, d26:f7) 15 smi on bar enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on bar (d29:f7, d26:f7:6ch, bit 31) is 1, then the host controller will issue an smi. 14 smi on pci command enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on pci command (d29:f7, d26:f7:6ch, bit 30) is 1, then the host cont roller will issue an smi. 13 smi on os ownership enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and the os ownership change bit (d29:f7, d26:f7:6ch, bit 29) is 1, the host controller will issue an smi. 12:6 reserved ? ro. hardwired to 00h 5 smi on async advance enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on as ync advance bit (d29:f7, d26:f7:6ch, bit 21) is a 1, the host co ntroller will issue an smi immediately. 4 smi on host system error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on host system error (d29:f7, d26:f7:6ch, bit 20) is a 1, the ho st controller will issue an smi. 3 smi on frame list rollover enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on frame list rollover bit (d29:f7, d26:f7:6ch, bit 19) is a 1, the ho st controller will issue an smi. 2 smi on port change enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on port change detect bit (d29:f7, d26:f7:6ch, bit 18) is a 1, the ho st controller will issue an smi. 1 smi on usb error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb error bit (d29:f7, d26:f7:6ch, bit 17) is a 1, the host controller will issue an smi immediately. 0 smi on usb complete enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb complete bit (d29:f7, d26:f7:6ch, bit 16) is a 1, the host co ntroller will issue an smi immediately. bit description ehci controller registers (d29:f7, d26:f7) 600 intel ? ich8 family datasheet 15.1.28 special_smi?intel spec ific usb 2.0 smi register (usb ehci?d29:f7, d26:f7) address offset: 70h ? 73h attribute: r/w, r/wc default value: 00000000h size: 32 bits power well: suspend note: these bits are not reset by a d3-to- d0 warm rest or a core well reset. bit description 31:28 (d29) 31:26 (d26) reserved ? ro. hardwired to 00h 27:22 (d29) 25:22 (d26) smi on portowner ? r/wc. software clears these bits by writing a 1 to it. 0 = no port owner bit change. 1 = bits 27:22, 25:22 correspond to the port owner bits for ports 1 (22) through 4 (25) or 6 (27). these bits are set to 1 when the associated port owner bits transition from 0 to 1 or 1 to 0. 21 smi on pmcsr ? r/wc. software clears these bits by writing a 1 to it. 0 = power state bits not modified. 1 = software modified the power state bi ts in the power ma nagement control/ status (pmcsr) register (d29:f7, d26:f7:54h). 20 smi on async ? r/wc. software clears thes e bits by writing a 1 to it. 0 = no async schedule enable bit change 1 = async schedule enable bit transitioned from 1 to 0 or 0 to 1. 19 smi on periodic ? r/wc. software clears this bit by writing a 1 it. 0 = no periodic schedule enable bit change. 1 = periodic schedule enable bit transitions from 1 to 0 or 0 to 1. 18 smi on cf ? r/wc. software clears this bit by writing a 1 it. 0 = no configure flag (cf) change. 1 = configure flag (cf) transitions from 1 to 0 or 0 to 1. 17 smi on hchalted ? r/wc. software clears th is bit by writing a 1 it. 0 = hchalted did not transition to 1 (a s a result of the run/stop bit being cleared). 1 = hchalted transitions to 1 (as a result of the run/stop bit being cleared). 16 smi on hcreset ? r/wc. software clears this bit by writing a 1 it. 0 = hcreset did not transitioned to 1. 1 = hcreset transitioned to 1. 15:14 reserved ? ro. hardwired to 00h 13:6 smi on portowner enable ? r/w. 0 = disable. 1 = enable. when any of these bits are 1 and the corresponding smi on portowner bits are 1, then the host co ntroller will issue an smi. unused ports should have their co rresponding bits cleared. 5 smi on pmscr enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on pmscr is 1, then the host controller will issue an smi. 4 smi on async enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on async is 1, then the host controller will issue an smi intel ? ich8 family datasheet 601 ehci controller registers (d29:f7, d26:f7) 15.1.29 access_cntl?acce ss control register (usb ehci?d29:f7, d26:f7) address offset: 80h attribute: r/w default value: 00h size: 8 bits 3 smi on periodic enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on periodic is 1, then the host controller will issue an smi. 2 smi on cf enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on cf is 1, then the ho st controller will issue an smi. 1 smi on hchalted enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and smi on hchalted is 1, then the host controller will issue an smi. 0 smi on hcreset enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and smi on hcreset is 1, th en host controller will issue an smi. bit description bit description 7:1 reserved 0 wrt_rdonly ? r/w. when set to 1, this bit enables a select group of normally read- only registers in the ehc function to be writ ten by software. registers that may only be written when this mode is entered are no ted in the summary tables and detailed description as ?read/write-special?. the registers fall into two categories: 1. system-configure d parameters, and 2. status bits ehci controller registers (d29:f7, d26:f7) 602 intel ? ich8 family datasheet 15.1.30 ehciir1?ehci initializati on register 1 (mobile only) (usb ehci?d29:f7, d26:f7) address offset: 84h attribute: r/w, r/wl default value: 01h size: 8 bits 15.1.31 ehciir2?ehci init ialization register 2 (usb ehci?d29:f7, d26:f7) address offset: fch attribute: r/w default value: 20001706h size: 32 bits bit description 7:5 reserved 4 pre-fetch based pause disable ? r/w. 0 = pre-fetch based pause is enabled 1 = pre-fetch based pause is disabled. 3:0 reserved bit description 31:30 reserved 29 ehciir2 field 2 ? r/w. bios must set this bit 28:18 reserved 17 ehciir2 field 1 ? r/w. bios must set this bit 16:0 reserved intel ? ich8 family datasheet 603 ehci controller registers (d29:f7, d26:f7) 15.2 memory-mapped i/o registers the ehci memory-mapped i/o space is composed of two sets of registers: capability registers and operational registers. note: the ich8 ehci controller will not accept memory transactions (neither reads nor writes) as a target that are locked transactions. the locked transactions should not be forwarded to pci as the address space is known to be allocated to usb. note: when the ehci function is in the d3 pci power state, accesses to the usb 2.0 memory range are ignored and result a master abort. similarly, if the memory space enable (mse) bit (d29:f7, d26:f7:04h, bit 1) is not set in the command register in configuration space, the memory range will no t be decoded by the ich8 enhanced host controller (ehc). if the mse bit is not set, then the ich8 must default to allowing any memory accesses for the range specified in the bar to go to pci. this is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. 15.2.1 host controller capability registers these registers specify the limits, restrictio ns and capabilities of the host controller implementation. within the host controller capability registers, only the structural parameters register is writable. these re gisters are implemented in the suspend well and is only reset by the standard suspend- well hardware reset, not by hcreset or the d3-to-d0 reset. note: note that the ehci controller does not support as a target memory transactions that are locked transactions. attempting to a ccess the ehci controller memory-mapped i/o space using locked memory transactions will result in undefined behavior. note: note that when the usb2 function is in th e d3 pci power state, accesses to the usb2 memory range are ignored and will result in a master abort similarly, if the memory space enable (mse) bit is not set in the co mmand register in configuration space, the memory range will not be decoded by the e nhanced host controller (ehc). if the mse bit is not set, then the ehc will not claim any memory accesses for the range specified in the bar. note: ?read/write special? means that the register is normally read-only, but may be written when the wrt_rdonly bit is set. because these registers are expected to be programmed by bios during initialization, their contents must not get modified by hcreset or d3-to- d0 internal reset. table 134. enhanced host controller capability registers mem_base + offset mnemonic register default type 00h caplength capabilities registers length 20h ro 02h?03h hciversion host controller interface version number 0100h ro 04h?07h hcsparams host controller structural parameters 00104208h r/w (special), ro 08h?0bh hccparams host controller capability parameters 00006871h ro ehci controller registers (d29:f7, d26:f7) 604 intel ? ich8 family datasheet 15.2.1.1 caplength?capab ility registers length offset: mem_base + 00h attribute: ro default value: 20h size: 8 bits 15.2.1.2 hciversion?host contro ller interface version number offset: mem_base + 02h ? 03h attribute: ro default value: 0100h size: 16 bits bit description 7:0 capability register length valu e ? ro. this register is used as an offset to add to the memory base register (d29:f7, d26:f7:10h) to find the beginning of the operational register space. this field is hardwired to 20h indicating that the operation registers begin at offset 20h. bit description 15:0 host controller interface version number ? ro. this is a two-byte re gister containing a bcd encoding of the version number of inte rface that this host controll er interface conforms. intel ? ich8 family datasheet 605 ehci controller registers (d29:f7, d26:f7) 15.2.1.3 hcsparams?host controller structural parameters offset: mem_base + 04h ? 07h attribute: r/w (special), ro default value: 00103206h (d29:f7) size: 32 bits 00102204h (d26:f7) note: this register is reset by a suspend well reset and not a d3-to-d0 reset or hcreset. note: this register is writable when the wrt_rdonly bit is set. bit description 31:24 reserved ? ro. default=0h. 23:20 debug port number (d p_n) ? ro (special). hardwired to 1h indicating that the debug port is on the lowest numbered port on the ehci. 19:16 reserved 15:12 number of companion controllers (n_cc) ? r/w (special). this field indicates the number of companion controllers associated with this usb ehci host controller. a 0 in this field indicates there are no comp anion host controllers. port-ownership hand- off is not supported. only hi gh-speed devices are supported on the host controller root ports. a value of 1 or more in this field indicates there are companion usb uhci host controller(s). port-ownership hand-offs are supported. high, full- and low-speed devices are supported on the host controller root ports. the ich8 allows the default value of 3h (d29) or 2 (d26) to be over-written by bios. when removing classic controllers, they mu st be disabled in the following order: function 2, function 1, and function 0, which correspond to ports 5:4, 3:2, and 1:0, respectively for device 29. for device 26 the following order is func tion 1 then function 0, which correspond to port s 9:8 and 7:6, respectively. 11:8 number of ports per companion controller (n_pcc) ? ro. hardwired to 2h. this field indicates the number of ports supported per companion host controll er. it is used to indicate the port routing conf iguration to system software. 7:4 reserved. these bits are reserved and default to 0. 3:0 n_ports ? r/w (special). this field specifies the numbe r of physical downstream ports implemented on th is host controller. the value of this field determines how many port registers are addressable in the operational register space. valid values are in the range of 1h to fh. the ich8 reports 6h for d29 and 4h for d26 by default. however, software may write a value less than the default for some platfo rm configurations. a 0 in this field is undefined. ehci controller registers (d29:f7, d26:f7) 606 intel ? ich8 family datasheet 15.2.1.4 hccparams?host cont roller capability parameters register offset: mem_base + 08h ? 0bh attribute: ro default value: 00006871h size: 32 bits bit description 31:16 reserved 15:8 ehci extended capabilities pointer (eecp) ? ro. this fi eld is hardwired to 68h, indicating that the ehci capa bilities list exists and begins at offset 68h in the pci configuration space. 7:4 isochronous scheduli ng threshold ? ro. this field indicates, re lative to the current position of the executing host controller , where software can reliably update the isochronous schedule. wh en bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller hold a set of isochr onous data structures (one or more) before fl ushing the state. when bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. refer to the ehci specification for details on how software uses this information for scheduling isochronous transfers. this field is hardwired to 7h. 3 reserved. these bits are reserved and should be set to 0. 2 asynchronous schedule park capability ? ro. this bit is hardwired to 0 indicating that the host controller does not support this optional feature 1 programmable frame list flag ? ro. 0 = system software must use a frame list length of 1024 elements with this host controller. the usb2.0_cmd register (d 29:f7, d26:f7:caplength + 20h, bits 3:2) frame list size field is a read-only regist er and must be set to 0. 1 = system software can specify and use a sm aller frame list and configure the host controller via the us b2.0_cmd register frame list size field. the frame list must always be aligned on a 4k page boundary . this requirement en sures that the frame list is always physically contiguous. 0 64-bit addressing capability ? ro. this field documents th e addressing range capability of this implementation. the value of this field determin es whether software should use the 32-bit or 64-bit data structures . values for this field have the following interpretation: 0 = data structures using 32- bit address memory pointers 1 = data structures using 64-bit address memory pointers this bit is hardwired to 1. note: ich8 only implements 44 bits of addressing. bits 63:44 will always be 0. intel ? ich8 family datasheet 607 ehci controller registers (d29:f7, d26:f7) 15.2.2 host controller operational registers this section defines the enhanced host controller operational registers. these registers are located after the capabilities registers. the operational register base must be dword-aligned and is calculated by adding the value in the first capabilities register (caplength) to the base address of the enhanced host controller register address space (mem_base). since caplength is always 20h, table 135 already accounts for this offset. all registers are 32 bits in length. note: software must read and write these registers using only dword accesses.these registers are divided into two sets. the fi rst set at offsets mem_base + 00:3bh are implemented in the core powe r well. unless otherwise noted, the core well registers are reset by the assertion of any of the following: ? core well hardware reset ? hcreset ? d3-to-d0 reset table 135. enhanced host controller operational register address map mem_base + offset mnemonic register name default special notes type 20h?23h usb2.0_cmd usb 2.0 command 00080000h r/w, ro 24h?27h usb2.0_sts usb 2.0 status 00001000h r/wc, ro 28h?2bh usb2.0_intr usb 2.0 interrupt enable 00000000h r/w 2ch?2fh frindex usb 2.0 frame index 00000000h r/w, 30h?33h ctrldssegm ent control data structure segment 00000000h r/w, ro 34h?37h perodiclist base period frame list base address 00000000h r/w 38h?3bh asynclistad dr current asynchronous list address 00000000h r/w 3ch?5fh ? reserved 0h ro 60h?63h configflag configure flag 00000000h suspend r/w 64h?67h port0sc port 0 status and control 00003000h suspend r/w, r/wc, ro 68h?6bh port1sc port 1 status and control 00003000h suspend r/w, r/wc, ro 6ch?6fh port2sc port 2 status and control 00003000h suspend r/w, r/wc, ro 70h?73h port3sc port 3 status and control 00003000h suspend r/w, r/wc, ro 74h?77h d29 only port4sc port 4 status and control 00003000h suspend r/w, r/wc, ro 78h?7bh d29 only port5sc port 5 status and control 00003000h suspend r/w, r/wc, ro 7ch?9fh ? reserved undefined ro a0h?b3h ? debug port registers undefined see register description b4h?3ffh ? reserved undefined ro ehci controller registers (d29:f7, d26:f7) 608 intel ? ich8 family datasheet the second set at offsets mem_base + 60h to the end of the implemented register space are implemented in the suspend po wer well. unless otherwise noted, the suspend well registers are reset by the assertion of either of the following: ? suspend well hardware reset ? hcreset 15.2.2.1 usb2.0_cmd?usb 2.0 command register offset: mem_base + 20?23h attribute: r/w, ro default value: 00080000h size: 32 bits bit description 31:24 reserved. these bits are reserved and should be set to 0 when writing this register. 23:16 interrupt threshold control ? r/w. system software uses this field to select the maximum rate at which the host controller wi ll issue interrupts. the only valid values are defined below. if software writes an in valid value to this re gister, the results are undefined. 15:8 reserved. these bits are reserved and should be set to 0 when writing this register. 11:8 unimplemented asynchronous park mode bits. hardwired to 000b indicating the host controller does not support this optional feature. 7 light host controller reset ? ro. hardwired to 0. the ich8 does not implement this optional reset. 6 interrupt on async advance doorbell ? r/w. this bit is us ed as a doorbell by software to tell the host controller to is sue an interrupt the next time it advances asynchronous schedule. 0 = the host controller sets this bit to a 0 after it has set the interrupt on async advance status bit (d29:f7, d26:f7:caplength + 24h, bit 5) in the usb2.0_sts register to a 1. 1 = software must write a 1 to this bit to ri ng the doorbell. when the host controller has evicted all appropriate cached schedule state, it sets th e interrupt on async advance status bit in the us b2.0_sts register. if the interrupt on async advance enable bit in the usb2.0_intr register (d29:f7, d26:f7:caplength + 28h, bit 5) is a 1 then the host controller will as sert an interrupt at the next interrupt threshold. see the ehci specif ication for operational details. note: software should not write a 1 to this bit when the asynchronous schedule is inactive. doing so will yield undefined results. 5 asynchronous schedule enable ? r/w. default 0b. this bit controls whether the host controller skips processi ng the asynchronous schedule. 0 = do not process the asynchronous schedule 1 = use the asynclistaddr register to access the asynchronous schedule. va l ue max i mum interrupt interva l 00h reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) intel ? ich8 family datasheet 609 ehci controller registers (d29:f7, d26:f7) note: the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. 4 periodic schedule enable ? r/w. default 0b. this bi t controls whether the host controller skips processing the periodic schedule. 0 = do not process the periodic schedule 1 = use the periodiclistbase register to access the periodic schedule. 3:2 frame list size ? ro. the ich8 hardwires this fiel d to 00b because it only supports the 1024-element frame list size. 1 host controller reset (hcreset) ? r/w. this control bit used by software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset (i.e., rsmrst# assertion and pw rok deassertion on the ich8). when software writes a 1 to th is bit, the host controller re sets its internal pipelines, timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediat ely terminated. a usb reset is not driven on downstream ports. note: pci configuration registers and host controller capability registers are not effected by this reset. all operational registers, including port registers and port state machines are set to their initial values. port ownership reverts to the companion host controller(s), with the side effects described in the ehci spec. softwa re must re-initialize the host controller in order to return the host contro ller to an operational state. this bit is set to 0 by the host controller when the reset process is complete. software cannot terminate the reset process earl y by writing a 0 to this register. software should not set this bit to a 1 when the hchalted bit (d29:f7, d26:f7:caplength + 24h, bit 12) in the usb2.0_sts register is a 0. attempting to reset an actively running host controller will result in undefined behavior. this reset me be used to leave eh ci port test modes. 0 run/stop (rs) ? r/w. 0 = stop (default) 1 = run. when set to a 1, the host controller proceeds with execution of the schedule. the host controller continues execution as long as this bit is set. when this bit is set to 0, the host controller completes the current transaction on the usb and then halts. the hchalted bit in the usb2.0_sts register indicates when the host controller has finished the transactio n and has entered the stopped state. software should not wr ite a 1 to this field unless the ho st controller is in the halted state (i.e., hchalted in the usbsts regi ster is a 1). the halted bit is cleared immediately when the run bit is set. the following table expl ains how the different combinatio ns of run and halted should be interpreted: memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being cleared. bit description run/stop halted interpretation 0b 0b in the process of halting 0b 1b halted 1b 0b running 1b 1b invalid - the hchalted bit clears immediately ehci controller registers (d29:f7, d26:f7) 610 intel ? ich8 family datasheet 15.2.2.2 usb2.0_sts?usb 2.0 status register offset: mem_base + 24h?27h attribute: r/wc, ro default value: 00001000h size: 32 bits this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. see the interrupts description in section 4 of the ehci specification for additional information concerning usb 2.0 interrupt conditions. note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 has no effect. bit description 31:16 reserved. these bits are reserved and should be set to 0 when writing this register. 15 asynchronous schedule status ro. this bit reports the cu rrent real status of the asynchronous schedule. 0 = status of the asynchronous sc hedule is disabled. (default) 1 = status of the asynchrono us schedule is enabled. note: the host controller is not required to immediately disable or enable the asynchronous schedule when software transitions the asynchronous schedule enable bit (d29:f7, d26:f7:caplength + 20h, bit 5) in the usb2.0_cmd register. when th is bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). 14 periodic schedule status ro. this bit reports the current real status of the periodic schedule. 0 = status of the periodic sche dule is disabled. (default) 1 = status of the periodic schedule is enabled. note: the host controller is not required to immediately disable or enable the periodic schedule when softwa re transitions the periodic schedule enable bit (d29:f7, d26:f7:caplength + 20h, bit 4) in the us b2.0_cmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). 13 reclamation ro. 0=default. this read-only status bit is used to detect an empty asynchronous schedule. the operational mode l and valid transitions for this bit are described in section 4 of the ehci specification. 12 hchalted ro. 0 = this bit is a 0 when the run/stop bit is a 1. 1 = the host controller sets this bit to 1 afte r it has stopped executin g as a result of the run/stop bit being set to 0, either by soft ware or by the host controller hardware (e.g., internal error). (default) 11:6 reserved 5 interrupt on async advance ? r/wc. 0=default. system softwa re can force the host controller to issue an inte rrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the interrupt on async advance doorbell bit (d29:f7, d26:f7:caplength + 20h, bit 6) in the usb2.0_cmd register. this bit indicates the assertion of that interrupt source. intel ? ich8 family datasheet 611 ehci controller registers (d29:f7, d26:f7) 4 host system error ? r/wc. 0 = no serious error occurred during a host system access involving the host controller module 1 = the host controller sets this bit to 1 when a serious error oc curs during a host system access involving the host contro ller module. a hardware interrupt is generated to the system. memory read cycl es initiated by the ehc that receive any status other than successful will result in this bit being set. when this error occurs, the host contro ller clears the run/stop bit in the usb2.0_cmdregister (d29:f7, d26:f7:caplength + 20h, bit 0) to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system (if enabled in the interrupt enable register). 3 frame list rollover ? r/wc. 0 = no frame list index rollover from its maximum value to 0. 1 = the host controller sets this bit to a 1 when the frame list index (see section) rolls over from its maximum value to 0. sinc e the ich8 only supports the 1024-entry frame list size, the frame list index rolls over every time frnum13 toggles. 2 port change detect ? r/wc. this bit is allowed to be maintained in the auxiliary power well. alternatively, it is also acceptable that on a d3 to d0 transition of the ehci hc device, this bit is loaded with the or of all of the portsc change bits (including: force port resume, overcurr ent change, enable/disable change and connect status change). regardless of the implementation, wh en this bit is readable (i.e., in the d0 state), it must provide a valid vi ew of the port status registers. 0 = no change bit transition from a 0 to 1 or no force port resume bit transition from 0 to 1 as a result of a j-k transiti on detected on a suspended port. 1 = the host controller sets this bi t to 1 when any port for which the port owner bit is set to 0 has a change bit transition fro m a 0 to 1 or a force port resume bit transition from 0 to 1 as a result of a j- k transition detected on a suspended port. 1 usb error interrupt (usberrint) ? r/wc. 0 = no error condition. 1 = the host controller sets this bit to 1 wh en completion of a usb transaction results in an error condition (e.g., e rror counter underflow). if the td on which the error interrupt occurred also had it s ioc bit set, both this bit and bit 0 are set. see the ehci specification for a list of the usb errors that will result in this interrupt being asserted. 0 usb interrupt (usbint) ? r/wc. 0 = no completion of a usb transaction whose transfer descriptor had its ioc bit set. no short packet is detected. 1 = the host controller sets this bit to 1 wh en the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). bit description ehci controller registers (d29:f7, d26:f7) 612 intel ? ich8 family datasheet 15.2.2.3 usb2.0_intr?usb 2.0 interrupt enable register offset: mem_base + 28h?2bh attribute: r/w default value: 00000000h size: 32 bits this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that are disabled in this register still appear in the usb2.0_sts register to allow the software to poll for events. each interrupt enable bit description indicates whether it is depe ndent on the interrupt threshold mechanism (see section 4 of the ehci specification), or not. bit description 31:6 reserved. these bits are reserved and should be 0 when writing this register. 5 interrupt on async advance enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and th e interrupt on async advance bit (d29:f7, d26:f7:caplength + 24h, bit 5) in the us b2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshol d. the interrupt is acknowledged by software clearing the interrupt on async advance bit. 4 host system error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and th e host system error status bit (d29:f7, d26:f7:caplength + 24h, bit 4) in the us b2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknow ledged by software clearing the host system error bit. 3 frame list rollover enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the frame list rollover bit (d29:f7, d26:f7:caplength + 24h, bit 3) in the us b2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknow ledged by software clearing the frame list rollover bit. 2 port change interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, an d the port change detect bit (d29:f7, d26:f7:caplength + 24h, bit 2) in the us b2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknow ledged by software clearing the port change detect bit. 1 usb error interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the usberrint bit (d29:f7, d26:f7:caplength + 24h, bit 1) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interru pt threshold. the interrupt is acknow ledged by software by clearing the usberrint bit in the usb2.0_sts register. 0 usb interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and th e usbint bit (d29:f7, d26:f7:caplength + 24h, bit 0) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interru pt threshold. the interrupt is acknow ledged by software by clearing the usbint bit in the usb2.0_sts register. intel ? ich8 family datasheet 613 ehci controller registers (d29:f7, d26:f7) 15.2.2.4 frindex?frame index register offset: mem_base + 2ch?2fh attribute: r/w default value: 00000000h size: 32 bits the sof frame number value for the bus sof token is derived or alternatively managed from this register. refer to section 4 of the ehci specification for a detailed explanation of the sof value management requirements on the host controller. the value of frindex must be within 125 s (1 micro-frame) ahead of the sof token value. the sof value may be implemented as an 11-bit shadow register. for this discussion, this shadow register is 11 bits and is named sofv. sofv updates every 8 micro-frames. (1 millisecond). an example implementation to ac hieve this behavior is to increment sofv each time the frindex[2:0] increments from 0 to 1. software must use the value of frindex to derive the current micro-frame number, both for high-speed isochronous sched uling purposes and to provide the get micro- frame number function required to client drivers. therefore, the value of frindex and the value of sofv must be kept consistent if chip is reset or software writes to frindex. writes to frindex must also write-through frindex[13:3] to sofv[10:0]. in order to keep the update as simple as possible, software should never write a frindex value where the three least significant bits are 111b or 000b. note: this register is used by the host controller to index into the periodic frame list. the register updates every 125 microseconds (once each micro-frame). bits [12:3] are used to select a particular entry in the periodic frame list during periodic schedule execution. the number of bits used for the inde x is fixed at 10 for the ich8 since it only supports 1024-entry frame lists. this register must be written as a dword. word and byte writes produce undefined results. this register cannot be written unless the host controller is in the halted state as indicated by the hchalted bit (d29:f7, d26:f7:caplength + 24h, bit 12). a write to this register while the run/stop bit (d29:f7, d26:f7:caplength + 20h, bit 0) is set to a 1 (usb2.0_cmd register) produces undefined results. writes to this register also effect the sof value. see section 4 of the ehci specification for details. bit description 31:14 reserved 13:0 frame list current index/frame number ? r/w. the value in this register increments at the end of each time frame (e.g., micro-frame). bits [12:3] are used fo r the frame list current index. th is means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. ehci controller registers (d29:f7, d26:f7) 614 intel ? ich8 family datasheet 15.2.2.5 ctrldssegment?control data structure segment register offset: mem_base + 30h?33h attribute: r/w, ro default value: 00000000h size: 32 bits this 32-bit register corresponds to the most significant address bits [63:32] for all ehci data structures. since the ich8 hardwires the 64-bit addressing capability field in hccparams to 1, then this register is used with the link pointers to construct 64-bit addresses to ehci control data structures. th is register is concatenated with the link pointer from either the periodiclistbase , asynclistaddr, or any control data structure link field to construct a 64-bit address. this register allows the host software to locate all control data structures within the same 4 gb memory segment. 15.2.2.6 periodiclistbase?periodic frame list base address register offset: mem_base + 34h?37h attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the beginning address of the periodic frame list in the system memory. since the ich8 host contro ller operates in 64-bit mode (as indicated by the 1 in the 64-bit addressing capability field in the hccsparams register) (offset 08h, bit 0), then the most significant 32 bi ts of every control data structure address comes from the ctrldssegment register. hcd loads this register prior to starting the schedule execution by the host controller. the memory structure referenced by this physical memory pointer is assumed to be 4-kbyte aligned. the contents of this register are combined with the frame index register (frindex) to enable the host controller to step through the periodic frame list in sequence. bit description 31:12 upper address[63:44] ? ro. ha rdwired to 0s. the ich8 ehc is only capable of generating addresses up to 16 terabytes (44 bits of address). 11:0 upper address[43:32] ? r/w. this 12-bit field corresponds to address bits 43:32 when forming a control data structure address. bit description 31:12 base address (low) ? r/w. these bits correspon d to memory address signals [31:12], respectively. 11:0 reserved. must be written as 0s. during runtime, the value of these bits are undefined. intel ? ich8 family datasheet 615 ehci controller registers (d29:f7, d26:f7) 15.2.2.7 asynclistaddr?current asynchronous list address register offset: mem_base + 38h?3bh attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the address of the next asynchronous queue head to be executed. since the ich8 host controller operat es in 64-bit mode (as indicated by a 1 in 64-bit addressing capability field in the hccp arams register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register (offset 08h). bits [4:0 ] of this register cannot be modified by system software and will always return 0?s when read. the memory structure referenced by this physical memory poin ter is assumed to be 32-byte aligned. 15.2.2.8 configflag?configure flag register offset: mem_base + 60h?63h attribute: r/w default value: 00000000h size: 32 bits this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. bit description 31:5 link pointer low (lpl) ? r/w. these bits correspon d to memory address signals [31:5], respectively. this field may only reference a queue head (qh). 4:0 reserved. these bits are reserved and their value has no e ffect on operation. bit description 31:1 reserved. read from this field will always return 0. 0 configure flag (cf) ? r/w. host software sets this bit as the last action in its process of configuring the host controller. this bit co ntrols the default port-r outing control logic. bit values and side-effects are listed below. see section 4 of the ehci spec for operation details. 0 = port routing control logic default-rout es each port to the uhcis (default). 1 = port routing control logic default-rout es all ports to this host controller. ehci controller registers (d29:f7, d26:f7) 616 intel ? ich8 family datasheet 15.2.2.9 portsc?port n status and control register offset: port 0, port 6: mem_base + 64h ? 67h port 1, port 7: mem_base + 68 ? 6bh port 2, port 8: mem_base + 6c ? 6fh port 3, port 9: mem_base + 70 ? 73h port 4: mem_base + 74 ? 77h (device 29 only) port 5: mem_base + 78 ? 7bh (device 29 only) attribute: r/w, r/wc, ro default value: 00003000h size: 32 bits a host controller must implement one or more port registers. software uses the n_port information from the structural parameters register to determine how many ports need to be serviced. all ports have the st ructure defined below. software must not write to unreported port status and control registers. this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in resp onse to a host controller reset. the initial conditions of a port are: ? no device connected ? port disabled. when a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. refer to section 4 of the ehci specification for operational requirements for how change events interact with port suspend mode. bit description 31:23 reserved. these bits are reserved for future use and will return a value of 0?s when read. 22 wake on overcurrent enable (wkoc_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the overcurrent active bit (bit 4 of this register) is set. 21 wake on disconnect enable (wkdscnnt_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offs et 54, bit 15) when the current connect status changes from connected to disconnected (i.e., bit 0 of this register changes from 1 to 0). 20 wake on connect enable (wkcnnt_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offs et 54, bit 15) when the current connect status changes from disconnected to connecte d (i.e., bit 0 of th is register changes from 0 to 1). intel ? ich8 family datasheet 617 ehci controller registers (d29:f7, d26:f7) 19:16 port test control ? r/w. when this field is 0s, the port is not operating in a test mode. a non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the spec ific value. the encoding of the test mode bits are (0110b ? 1111b are reserved): refer to usb specification revision 2.0, chapter 7 for details on each test mode. 15:14 reserved ? r/w. should be written to =00b. 13 port owner ? r/w. default = 1b. this bit unconditionally goes to a 0 when the configured flag bit in the usb2.0_cmd register makes a 0 to 1 transition. system software uses this field to release ownership of the port to a selected host controller (in the event that the attached de vice is not a high-spe ed device). software writes a 1 to this bit when the attached device is not a high-speed device. a 1 in this bit means that a companion host controller owns and controls the port. see section 4 of the ehci specification for operational details. 12 port power (pp) ? ro. read-only with a value of 1. this indicates that the port does have power. 11:10 line status ? ro.these bits reflect the current logical levels of the d+ (bit 11) and d? (bit 10) signal lines. these bits are used fo r detection of low-speed usb devices prior to the port reset and enable sequen ce. this field is valid only when the port enable bit is 0 and the current connect stat us bit is set to a 1. 00 = se0 10 = j-state 01 = k-state 11 = undefined 9 reserved. this bit will return a 0 when read. bit description value maximum interrupt interval 0000b test mode not enabled (default) 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b force_enable ehci controller registers (d29:f7, d26:f7) 618 intel ? ich8 family datasheet 8 port reset ? r/w. default = 0. when software wr ites a 1 to this bit (from a 0), the bus reset sequence as defined in the usb specification, revision 2.0 is started. software writes a 0 to this bit to terminate the bus reset sequence. software must keep this bit at a 1 long enough to assure the reset sequence completes as specified in the usb specification, revision 2.0. 1 = port is in reset. 0 = port is not in reset. note: when software writes a 0 to this bit, th ere may be a delay be fore the bit status changes to a 0. the bit status will no t read as a 0 until after the reset has completed. if the port is in high-speed mode after re set is complete, the host controller will automatically en able this port (e.g., set the port enable bit to a 1). a host controller must terminate the reset and stabilize th e state of the port within 2 milliseconds of software transitioning this bit from 0 to 1. for example: if the port de tects that the attached device is high-speed during reset, then the host controller must ha ve the port in the enabled state within 2 ms of software writing this bit to a 0. the hchalted bit (d29:f7, d26:f7:caplength + 24h, bit 12) in the usb2.0_sts register should be a 0 before software attempts to use this bit. the host controller may hold port reset asserted to a 1 when the hchalted bit is a 1. this bit is 0 if port power is 0 note: system software should not at tempt to reset a port if the hchalted bit in the usb2.0_sts register is a 1. doing so will result in undefined behavior. 7 suspend ? r/w. 0 = port not in suspend state.(default) 1 = port in suspend state. port enabled bit and suspend bit of this re gister define the port states as follows: when in suspend state, downstream propagatio n of data is blocked on this port, except for port reset. note that the bit status does not change un til the port is suspended and that there may be a delay in suspending a po rt depending on the ac tivity on the port. the host controller will unconditionally se t this bit to a 0 when software sets the force port resume bit to a 0 (from a 1). a write of 0 to this bit is ignored by the host controller. if host software sets this bit to a 1 when the port is not enabled (i.e., port enabled bit is a 0) the results are undefined. bit description port enabled suspend port state 0 x disabled 1 0 enabled 1 1 suspend intel ? ich8 family datasheet 619 ehci controller registers (d29:f7, d26:f7) 6 force port resume ? r/w. 0 = no resume (k-state) detected/driven on port. (default) 1 = resume detected/driven on port. software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected while the port is in the suspend state. wh en this bit transitions to a 1 because a j- to-k transition is detected, the port change detect bit (d29:f7, d26:f7:caplength + 24h, bit 2) in the usb2.0_sts register is also set to a 1. if software sets this bit to a 1, the host controller must not set the port change detect bit. note: when the ehci controller owns the po rt, the resume sequence follows the defined sequence documented in the us b specification, revision 2.0. the resume signaling (full-speed 'k') is driv en on the port as long as this bit remains a 1. software must appropriately time the resume and set this bit to a 0 when the appropriate amount of time has elapsed. writing a 0 (from 1) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). this bit will remain a 1 until the port has switched to the high-speed idle. 5 overcurrent change ? r/wc. the functionality of this bit is not dependent upon the port owner. software clears th is bit by writing a 1 to it. 0 = no change. (default) 1 = there is a change to overcurrent active. 4 overcurrent active ? ro. 0 = this port does not have an overcurrent condition. (default) 1 = this port currently has an overcurrent condition. this bit will automatically transition from 1 to 0 when the over cu rrent condition is removed. the ich8 automatically disables the port when the overcurrent active bit is 1. 3 port enable/disable change ? r/wc. for the root hub, this bit gets set to a 1 only when a port is disabled due to the appropri ate conditions existing at the eof2 point (see chapter 11 of the usb specification for th e definition of a port error). this bit is not set due to the disabled-to-enabled tran sition, nor due to a disconnect. software clears this bit by writing a 1 to it. 0 = no change in status. (default). 1 = port enabled/disabled status has changed. bit description ehci controller registers (d29:f7, d26:f7) 620 intel ? ich8 family datasheet 15.2.3 usb 2.0-based debug port register the debug port?s registers are located in the same memory area, defined by the base address register (mem_base), as the standard ehci registers. the base offset for the debug port registers (a0h) is declared in the debug port base offset capability register at configuration offset 5ah (d 29:f7, d26:f7:offset 5ah). the specific ehci port that supports this debug capability (port 0 for d29: f7 and port 6 for d26:f7) is indicated by a 4-bit field (bits 20?23) in the hcsparams register of the ehci controller. the address map of the debug port registers is shown in table 136 . notes: 1. all of these registers are implemented in the core well and reset by pltrst#, ehc hcreset, and a ehc d3-to-d0 transition. 2. the hardware associated with this register provides no chec ks to ensure that software programs the interface correctly. how the ha rdware behaves when programmed invalidlly is undefined. 2 port enabled/disabled ? r/w. ports can only be enabled by the host controller as a part of the reset and enable. so ftware cannot enable a port by writing a 1 to this bit. ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software . note that the bit status does not change until the port state actually changes. there may be a dela y in disabling or enabling a port due to other host controller and bus events. 0 = disable 1 = enable (default) 1 connect status change ? r/wc. this bit indicates a change has occurred in the port?s current connect status . software sets this bit to 0 by writing a 1 to it. 0 = no change (default). 1 = change in current connect status. the host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. for example, the insertion status changes twice before system software has cleared the ch anged condition, hub hardware will be ?setting? an already-set bit (i.e ., the bit will remain set). 0 current connect status ? ro. this value reflects the current state of the port, and may not correspond directly to the event th at caused the connec t status change bit (bit 1) to be set. 0 = no device is present. (default) 1 = device is present on port. bit description table 136. debug port register address map mem_base + offset mnemonic register name default type a0?a3h cntl_sts control/status 00000000h r/w, r/wc, ro, wo a4?a7h usbpid usb pids 00000000h r/w, ro a8?abh databuf[3:0] data buffer (bytes 3:0) 00000000h r/w ac?afh databuf[7:4] data buffer (bytes 7:4) 00000000h r/w b0?b3h config configuration 00007f01h r/w intel ? ich8 family datasheet 621 ehci controller registers (d29:f7, d26:f7) 15.2.3.1 cntl_sts?control/status register offset: mem_base + a0h attribute: r/w, r/wc, ro, wo default value: 0000h size: 32 bits bit description 31 reserved 30 owner_cnt ? r/w. 0 = ownership of the debug port is not fo rced to the ehci controller (default) 1 = ownership of the debug port is forced to the ehci controller (i.e. immediately taken away from the companion classic usb host controller) if the port was already owned by the ehci controller, then setting this bit has no effect. this bit overrides all of the owners hip-related bits in the standard ehci registers. 29 reserved 28 enabled_cnt ? r/w. 0 = software can clear this by writing a 0 to it. the hardware clears this bit for the same conditions where the port enable /disable change bit (in the portsc register) is set. (default) 1 = debug port is enabled for operation. softwa re can directly set this bit if the port is already enabled in the associated portsc register (this is enforced by the hardware). 27:17 reserved 16 done_sts ? r/wc. software can clear th is by writing a 1 to it. 0 = request not complete 1 = set by hardware to indicate that the request is complete. 15:12 link_id_sts ? ro. this field identifies the link interface. 0h = hardwired. indicates that it is a usb debug port. 11 reserved. this bit returns 0 when read. writes have no effect. 10 in_use_cnt ? r/w. set by software to indicate th at the port is in use. cleared by software to indicate that the port is free an d may be used by other software. this bit is cleared after reset. (this bit has no affect on hardware.) 9:7 exception_sts ? ro. this field indicates the exception when the error_good#_sts bit is set. this field should be ignored if the error_good#_sts bit is 0. 000 =no error. (default) note: this should not be seen, since this field should only be checked if there is an error. 001 =transaction error: indicates the usb 2. 0 transaction had an error (crc, bad pid, timeout, etc.) 010 =hardware error. request was attemp ted (or in progress) when port was suspended or reset. all other combinations are reserved 6 error_good#_sts ? ro. 0 = hardware clears this bit to 0 after the proper completion of a read or write. (default) 1 = error has occurred. details on the nature of the error are provided in the exception field. ehci controller registers (d29:f7, d26:f7) 622 intel ? ich8 family datasheet notes: 1. software should do read-modify-write operations to this register to preserve the contents of bits not being modified. this include reserved bits. 2. to preserve the usage of reserved bits in the future, software should always write the same value read from th e bit until it is define d. reserved bits will always return 0 when read. 15.2.3.2 usbpid?usb pids register offset: mem_base + a4h attribute: r/w, ro default value: 0000h size: 32 bits this dword register is used to communicate pid information between the usb debug driver and the usb debug port. the debug port uses some of these fields to generate usb packets, and uses other fields to retu rn pid information to the usb debug driver. 5 go_cnt ? wo. 0 = hardware clears this bit when hardwa re sets the done_sts bit. (default) 1 = causes hardware to perform a read or write request. note: writing a 1 to this bit when it is alre ady set may result in undefined behavior. 4 write_read#_cnt ? r/w. software clears this bit to indicate that the current request is a read. software sets this bit to indicate that the current request is a write. 0 = read (default) 1 = write 3:0 data_len_cnt ? r/w. this field is used to indicate the size of the data to be transferred. default = 0h. for write operations, this field is set by soft ware to indicate to the hardware how many bytes of data in data buffer are to be tr ansferred to the console. a value of 0h indicates that a zero-length packet should be sent. a value of 1?8 indicates 1?8 bytes are to be transferred. values 9?fh are inva lid and how hardware behaves if used is undefined. for read operations, this fiel d is set by hardware to indicate to software how many bytes in data buffer are valid in response to a read operation. a value of 0h indicates that a zero length packet was returned and the state of data buffe r is not defined. a value of 1?8 indicates 1?8 bytes were received. hardware is not allowed to return values 9?fh. the transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. bit description bit description 31:24 reserved: these bits will return 0 wh en read. writes will have no effect. 23:16 received_pid_sts[23:16] ? ro. hardware updates this field with the received pid for transactions in either direction. when the controller is writing data, this field is updated with the handshake pid that is received from the device. when the host controller is reading data, this field is updated with the da ta packet pid (if the device sent data), or the handshake pid (if the devi ce naks the request). this field is valid when the hardware clears the go_done#_cnt bit. 15:8 send_pid_cnt[15:8] ? r/w. hardware sends this pid to begin the data packet when sending data to usb (i.e., write_re ad#_cnt is asserted). software typically sets this field to either data0 or data1 pid values. 7:0 token_pid_cnt[7:0] ? r/w. hardware sends this pid as the token pid for each usb transaction. software typically sets th is field to either in , out, or setup pid values. intel ? ich8 family datasheet 623 ehci controller registers (d29:f7, d26:f7) 15.2.3.3 databuf[7:0]?data buffer bytes[7:0] register offset: mem_base + a8h?afh attribute: r/w default value: 0000000000000000h size: 64 bits this register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register. 15.2.3.4 config?configuration register offset: mem_base + b0?b3h attribute: r/w default value: 00007f01h size: 32 bits bit description 63:0 databuffer[63:0] ? r/w. this field is the 8 byte s of the data buffer. bits 7:0 correspond to least significant byte (byte 0). bits 63:56 correspond to the most significant byte (byte 7). the bytes in the data buffer mu st be written with data befo re software initiates a write request. for a read request, the data buffer contains va lid data when done_sts bit (offset a0, bit 16) is cleared by the hard ware, error_good#_sts (offset a0, bit 6) is cleared by the hardware, and the data _length_cnt field (offset a0, bits 3:0) indicates the number of bytes that are valid. bit description 31:15 reserved 14:8 usb_address_cnf ? r/w. this 7-bit field identifi es the usb device address used by the controller for all token pid generation. (default = 7fh) 7:4 reserved 3:0 usb_endpoint_cnf ? r/w. this 4-bit field identi fies the endpoint used by the controller for all token pid generation. (default = 01h) ehci controller registers (d29:f7, d26:f7) 624 intel ? ich8 family datasheet intel ? ich8 family datasheet 625 smbus controller registers (d31:f3) 16 smbus controller registers (d31:f3) 16.1 pci configuration registers (smbus?d31:f3) note: registers that are not shown should be treated as reserved (see section 6.2 for details). 16.1.1 vid?vendor identificati on register (smbus?d31:f3) address: 00h ? 01h attribute: ro default value: 8086h size: 16 bits table 137. smbus controller pci re gister address map (smbus?d31:f3) offset mnemonic register name default type 00h?01h vid vendor identification 8086 ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0280h ro, r/wc 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 05h ro 0bh bcc base class code 0ch ro 14h smbmbar1 memory based address register 1 (bit 35:32) 00000000h ro 20h?23h smb_base smbus base address 00000001h r/w, ro 2ch?2dh svid subsystem vendor identification 00h ro 2eh?2fh sid subsystem identification 00h r/wo 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 40h hostc host configuration 00h r/w bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel smbus controller registers (d31:f3) 626 intel ? ich8 family datasheet 16.1.2 did?device identificati on register (smbus?d31:f3) address: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 16.1.3 pcicmd?pci command register (smbus?d31:f3) address: 04h ? 05h attributes: ro, r/w default value: 0000h size: 16 bits bit description 15:0 device id ? ro. this is a 16-bit value assi gned to the intel? ich8 smbus controller. refer to the intel ? ich8 family specification update for the value of the device id register. bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable 1 = disables smbus to assert its pirqb# signal. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. 0 = enables serr# generation. 1 = disables serr# generation. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? r/w. 0 = disable 1 = sets detected parity error bit (d31:f3:06 , bit 15) when a parity error is detected. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle en able (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? ro. hardwired to 0. 1 memory space enable (mse) ? r/w. 0 = disables memory mapped configuration space. 1 = enables memory mapped configuration space. 0 i/o space enable (iose) ? r/w. 0 = disable 1 = enables access to the sm bus i/o space registers as defined by the base address register. intel ? ich8 family datasheet 627 smbus controller registers (d31:f3) 16.1.4 pcists?pci status register (smbus?d31:f3) address: 06h ? 07h attributes: ro, r/wc default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 16.1.5 rid?revision identificati on register (smbus?d31:f3) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = parity error detected. 14 signaled system error (sse) ? r/wc. 0 = no system error detected. 1 = system error detected. 13 received master abort (rma) ? ro. hardwired to 0. 12 received target abort (rta) ? ro. hardwired to 0. 11 signaled target abort (sta) ? r/wc. 0 = ich8 did not terminate transaction fo r this function with a target abort. 1 = the function is targeted wi th a transaction that the intel ? ich8 terminates with a target abort. 10:9 devsel# timing status (devt) ? ro. this 2-bit field defines the timing for devsel# assertion for positive decode. 01 = medium timing. 8 data parity error detected (d ped) ? ro. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 0 because there are no capability list structures in this function 3 interrupt status (ints) ? ro. this bit indicates that an in terrupt is pending. it is independent from the state of the interrupt enable bit in the pci command register. 2:0 reserved bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 8 (ich8) family specification update for the value of the revision id register. smbus controller registers (d31:f3) 628 intel ? ich8 family datasheet 16.1.6 pi?programming interfac e register (smbus?d31:f3) offset address: 09h attribute: ro default value: 00h size: 8 bits 16.1.7 scc?sub class code register (smbus?d31:f3) address offset: 0ah attributes: ro default value: 05h size: 8 bits 16.1.8 bcc?base class code register (smbus?d31:f3) address offset: 0bh attributes: ro default value: 0ch size: 8 bits 16.1.9 smbmbar0 ? d31_f3_smbu s memory base address 0 address offset: 10h attributes: r/w default value: 00000000h size: 32 bits bit description 7:0 reserved bit description 7:0 sub class code (scc) ? ro. 05h = sm bus serial controller bit description 7:0 base class code (bcc) ? ro. 0ch = serial controller. bit description 31:8 base address: provides the 32 byte t system memo ry base address fo r the intel ich8 smb logic. 7:1 reserved 0 memory space indicator: this read-only bit always is 0, indicating that the smb logic is memory mapped. intel ? ich8 family datasheet 629 smbus controller registers (d31:f3) 16.1.10 smb_base?smbus ba se address register (smbus?d31:f3) address offset: 20 ? 23h attribute: r/w, ro default value: 00000001h size: 32-bits 16.1.11 svid ? subsystem vend or identification register (smbus?d31:f2/f4) address offset: 2ch ? 2dh attribute: ro default value: 0000h size: 16 bits lockable: no power well: core 16.1.12 sid ? subsystem id entification register (smbus?d31:f2/f4) address offset: 2eh ? 2fh attribute: r/wo default value: 00h size: 16 bits lockable: no power well: core bit description 31:16 reserved ? ro 15:5 base address ? r/w. this field provides the 32-b yte system i/o base address for the ich8 smb logic. 4:1 reserved ? ro 0 io space indicator ? ro. hardwired to 1 in dicating that the smb logic is i/o mapped. bit description 15:0 subsystem vendor id (svid) ? ro. the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide svid register. note: software can write to this register only once per core well re set. writes should be done as a single 16-bit cycle. bit description 15:0 subsystem id (sid) ? ro. the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide sid register. note: software can write to this register only once per core well re set. writes should be done as a single 16-bit cycle. smbus controller registers (d31:f3) 630 intel ? ich8 family datasheet 16.1.13 int_ln?interrupt line register (smbus?d31:f3) address offset: 3ch attributes: r/w default value: 00h size: 8 bits 16.1.14 int_pn?interrupt pin register (smbus?d31:f3) address offset: 3dh attributes: ro default value: see description size: 8 bits 16.1.15 hostc?host configurat ion register (smbus?d31:f3) address offset: 40h attribute: r/w default value: 00h size: 8 bits bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the ich8. it is to communicate to software the interrupt line that the interrupt pin is connected to pirqb#. bit description 7:0 interrupt pin (int_pn) ? ro. this reflec ts the value of d31ip.smip in chipset configuration space. bit description 7:4 reserved 3 soft smbus reset (ssreset) ? r/w. 0 = the hw will reset this bit to 0 wh en smbus reset operation is completed. 1 = the smbbus state machine and logic in ich8 is reset. 2 i 2 c_en ? r/w. 0 = smbus behavior. 1 = the ich8 is enabled to communicate with i 2 c devices. this will change the formatting of some commands. 1 smb_smi_en ? r/w. 0 = smbus interrupts will not generate an smi#. 1 = any source of an smb interrupt will inst ead be routed to generate an smi#. refer to section 5.20.4 (interrupts / smi#). this bit needs to be set fo r smbalert# to be enabled. 0 smbus host enab le (hst_en) ? r/w. 0 = disable the smbus host controller. 1 = enable. the smb host cont roller interface is enable d to execute commands. the intren bit (offset smbase + 02h, bit 0) needs to be enabled for the smb host controller to interrupt or smi#. note that the smb host controller will not respond to any new requests until all inte rrupt requests have been cleared. intel ? ich8 family datasheet 631 smbus controller registers (d31:f3) 16.2 smbus i/o and memory mapped i/o registers table 138. smbus i/o and memory mapped i/o regist er address map smb_base + offset mnemonic register name default type 00h hst_sts host status 00h r/wc, ro, r/wc (special) 02h hst_cnt host control 00h r/w, wo 03h hst_cmd host command 00h r/w 04h xmit_slva transmit slave address 00h r/w 05h hst_d0 host data 0 00h r/w 06h hst_d1 host data 1 00h r/w 07h host_block_db host block data byte 00h r/w 08h pec packet error check 00h r/w 09h rcv_slva receive slave address 44h r/w 0ah?0bh slv_data receive slave data 0000h ro 0ch aux_sts auxiliary status 00h r/wc, ro 0dh aux_ctl auxiliary control 00h r/w 0eh smlink_pin_ctl smlink pin control (tco compatible mode) see register description r/w, ro 0fh smbus_pin_ctl smbus pin control see register description r/w, ro 10h slv_sts slave status 00h r/wc 11h slv_cmd slave command 00h r/w 14h notify_daddr notify device address 00h ro 16h notify_dlow notify data low byte 00h ro 17h notify_dhigh notify data high byte 00h ro smbus controller registers (d31:f3) 632 intel ? ich8 family datasheet 16.2.1 hst_sts?host status register (smbus?d31:f3) register offset: smbase + 00h attribute: r/wc, r/wc (special), ro default value: 00h size: 8-bits all status bits are set by hardware and cleared by the software writing a one to the particular bit position. writing a 0 to any bit position has no effect. bit description 7 byte done status (ds) ? r/wc. 0 = software can clear this by writing a 1 to it. 1 = host controller received a byte (for bl ock read commands) or if it has completed transmission of a byte (for block write commands) when the 32 -byte buffer is not being used. note that this bit will be set, even on the last byte of the transfer. this bit is not set when transmission is due to the lan interface heartbeat. this bit has no meaning for block transf ers when the 32-byte buffer is enabled. note: when the last byte of a block message is received, the host controller will set this bit. however, it will not immediately set the intr bit (bit 1 in this register). when the interrupt handler clears the ds bit, the message is considered complete, and the host controller will then set the intr bit (and generate another interrupt). thus, for a block message of n bytes, the ich8 will generate n+1 interrupts. the interrupt handler needs to be implemented to handle these cases. when not using the 32 byte bu ffer, hardware will drive the smbclk signal low when the ds bit is set until sw clears the bit. this includes the last byte of a transfer. software must clear the ds bit before it can clear the busy bit. 6 inuse_sts ? r/wc (special). th is bit is used as semaphore among various independent software threads that may need to use the ich8?s smbus logic, and has no other effect on hardware. 0 = after a full pci reset, a read to this bit returns a 0. 1 = after the first read, subsequent reads will return a 1. a write of a 1 to this bit will reset the next read value to 0. writing a 0 to this bit has no effect. software can poll this bit until it reads a 0, and will then own the usage of the host controller. 5 smbalert_sts ? r/wc. 0 = interrupt or smi# was not generated by smbalert#. software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# wa s the smbalert# signal. this bit is only cleared by software writing a 1 to the bit position or by rsmrst# going low. if the signal is programmed as a gpio , then this bit will never be set. 4 failed ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# was a failed bus transaction. this bit is set in response to the kill bit being set to terminate the host transaction. 3 bus_err ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the source of the interrupt of smi# was a transaction collision. 2 dev_err ? r/wc. 0 = software clears this bit by writing a 1 to it. the ich8 will then deassert the interrupt or smi#. 1 = the source of the interrupt or sm i# was due to one of the following: ? invalid command field, ? unclaimed cycle (host initiated), ? host device time-out error. intel ? ich8 family datasheet 633 smbus controller registers (d31:f3) 16.2.2 hst_cnt?host control register (smbus?d31:f3) register offset: smbase + 02h attribute: r/w, wo default value: 00h size: 8-bits note: a read to this register will clear the byte pointer of the 32-byte buffer. 1 intr ? r/wc (special). this bit can only be set by termination of a command. intr is not dependent on the intren bit (offset smbase + 02h, bit 0) of the host controller register (offset 02h). it is only dependent on the term ination of the command. if the intren bit is not set, then the intr bit will be set, although the interrupt will not be generated. software can poll the in tr bit in this non-interrupt case. 0 = software clears this bit by writing a 1 to it. the ich8 then deasserts the interrupt or smi#. 1 = the source of the interrupt or smi# wa s the successful completion of its last command. 0 host_busy ? r/wc. 0 = cleared by the ich8 when the current transaction is completed. 1 = indicates that the ich8 is running a command from the host interface. no smb registers should be accessed while this bit is set, except the block data byte register. the block data byte register can be accessed when this bit is set only when the smb_cmd bits in the host co ntrol register are programmed for block command or i 2 c read command. this is nece ssary in order to check the done_sts bit. bit description bit description 7 pec_en . ? r/w. 0 = smbus host controller does not perf orm the transaction with the pec phase appended. 1 = causes the host controller to perform th e smbus transaction with the packet error checking phase appended. for writes, the value of the pec byte is transferred from the pec register. for reads, the pec byte is loaded in to the pec register. this bit must be written prior to the write in which the start bit is set. 6 start ? wo. 0 = this bit will always retu rn 0 on reads. the host_bus y bit in the host status register (offset 00h) can be used to identify when the intel ? ich8 has finished the command. 1 = writing a 1 to this bit initiates the co mmand described in th e smb_cmd field. all registers should be setup prior to writing a 1 to this bit position. 5 last_byte ? wo. this bit is used for block read commands. 1 = software sets this bit to indicate that the next byte will be the last byte to be received for the block. this causes the ich8 to send a nack (instead of an ack) after receiving the last byte. note: once the second_to_sts bit in tco2_s ts register (d31:f0, tcobase+6h, bit 1) is set, the last_byte bit also ge ts set. while the second_to_sts bit is set, the last_byte bit cannot be cleared. this prevents the ich8 from running some of the smbus commands (block read/write, i 2 c read, block i 2 c write). smbus controller registers (d31:f3) 634 intel ? ich8 family datasheet 4:2 smb_cmd ? r/w. the bit encoding below indica tes which command the ich8 is to perform. if enabled, the ich8 will genera te an interrupt or smi# when the command has completed if the value is for a non-suppo rted or reserved comm and, the ich8 will set the device error (dev_err) status bit (o ffset smbase + 00h, bit 2) and generate an interrupt when the start bit is set. the ich8 will perform no command, and will not operate until dev_err is cleared. 000 = quick : the slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = byte : this command uses the transmit slave address and command registers. bit 0 of the slave address register determines if this is a read or write command. 010 = byte data : this command uses the transmit slave address, command, and data0 registers. bit 0 of the slave address register determines if this is a read or write command. if it is a read, the da ta0 register will contain the read data. 011 = word data : this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave a ddress register determines if this is a read or write command. if it is a read, after the command completes, the data0 and data1 registers wi ll contain the read data. 100 = process call: this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. after the command completes, the data0 and data1 registers will contain the read data. 101 = block : this command uses the transmit slave address, command, data0 registers, and the block data byte regist er. for block write, the count is stored in the data0 register and indicates how ma ny bytes of data will be transferred. for block reads, the count is received an d stored in the data0 register. bit 0 of the slave address register selects if this is a read or write command. for writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. 110 = i 2 c read : this command uses the transmit slave address, command, data0, data1 registers, and the block data byte register. the read data is stored in the block data byte register. the ich8 continues reading data until the nak is received. 111 = block process: this command uses the transmit slave address, command, data0 and the block data byte register. fo r block write, the count is stored in the data0 register and indicates how many bytes of data will be transferred. for block read, the count is received and stored in the data0 register. bit 0 of the slave address register al ways indicate a write command. for writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. note: e32b bit in the auxiliary co ntrol register must be set for this command to work. 1 kill ? r/w. 0 = normal smbus host controller functionality. 1 = kills the current host tran saction taking place, sets the failed status bit, and asserts the interrupt (or smi#). this bit, once se t, must be cleare d by software to allow the smbus host controll er to function normally. 0 intren ? r/w. 0 = disable. 1 = enable the generation of an interrupt or smi# upon the completion of the command. bit description intel ? ich8 family datasheet 635 smbus controller registers (d31:f3) 16.2.3 hst_cmd?host command register (smbus?d31:f3) register offset: smbase + 03h attribute: r/w default value: 00h size: 8 bits 16.2.4 xmit_slva?transmit slave address register (smbus?d31:f3) register offset: smbase + 04h attribute: r/w default value: 00h size: 8 bits this register is transmitted by the host controller in the slave address field of the smbus protocol. 16.2.5 hst_d0?host data 0 register (smbus?d31:f3) register offset: smbase + 05h attribute: r/w default value: 00h size: 8 bits 16.2.6 hst_d1?host data 1 register (smbus?d31:f3) register offset: smbase + 06h attribute: r/w default value: 00h size: 8 bits bit description 7:0 this 8-bit field is transmitte d by the host controller in the command field of the smbus protocol during the execution of any command. bit description 7:1 address ? r/w. this field provides a 7-bit a ddress of the targeted slave. 0 read-write ? r/w. direction of the host transfer. 0 = write 1 = read bit description 7:0 data0/count ? r/w. this field contains the 8-bit data sent in the data0 field of the smbus protocol. for block write commands, this register reflects th e number of bytes to transfer. this register should be programm ed to a value between 1 and 32 for block counts. a count of 0 or a count above 32 will result in unpredictable behavior. the host controller does not check or log invalid block counts. bit description 7:0 data1 ? r/w. this 8-bit register is transm itted in the data1 field of the smbus protocol during the execution of any command. smbus controller registers (d31:f3) 636 intel ? ich8 family datasheet 16.2.7 host_block_db?host bl ock data byte register (smbus?d31:f3) register offset: smbase + 07h attribute: r/w default value: 00h size: 8 bits 16.2.8 pec?packet error check (pec) register (smbus?d31:f3) register offset: smbase + 08h attribute: r/w default value: 00h size: 8 bits bit description 7:0 block data (bdta) ? r/w. this is either a register, or a pointer into a 32-byte block array, depending upon whether the e32b bit is set in the auxiliary control register. when the e32b bit (offset smbase + 0dh, bit 1) is cleared, this is a register containing a byte of data to be sent on a block writ e or read from on a block read, just as it behaved on the ich3. when the e32b bit is set, read s and writes to this register are used to access the 32- byte block data storage array. an internal index pointer is used to address the array, which is reset to 0 by reading the hctl re gister (offset 02h). the index pointer then increments automatically upon each access to this register. the transfer of block data into (read) or out of (write) this storag e array during an smbus transaction always starts at index address 0. when the e2b bit is set, for writes, software will write up to 32-bytes to this register as part of the setup for the command. after th e host controller has sent the address, command, and byte count fields , it will send the bytes in the sram pointed to by this register. when the e2b bit is cleared for writes, software will place a single byte in this register. after the host controller has sent the address, command, and byte count fields, it will send the byte in this register. if there is more data to send, software will write the next series of bytes to the sram pointed to by th is register and clear the done_sts bit. the controller will then send the next byte. du ring the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. when the e2b bit is set for reads, after receiving the byte count into the data0 register, the first series of data bytes go into the sram pointed to by this register. if the byte count has been exhausted or the 32-byte sram has been filled, the controller will generate an smi# or interrupt (depending on configuration) and set the done_sts bit. software will then read the data. during th e time between when the last byte is read from the sram to when the done_sts bit is cleared, the controller will insert wait- states on the interface. bit description 7:0 pec_data ? r/w. this 8-bit register is written with the 8-bit crc value that is used as the smbus pec data prior to a write transa ction. for read transactions, the pec data is loaded from the smbus into this register an d is then read by so ftware. software must ensure that the inuse_sts bit is properly ma intained to avoid having this field over- written by a write transaction following a read transaction. intel ? ich8 family datasheet 637 smbus controller registers (d31:f3) 16.2.9 rcv_slva?receive sl ave address register (smbus?d31:f3) register offset: smbase + 09h attribute: r/w default value: 44h size: 8 bits lockable: no power well: resume 16.2.10 slv_data?receive slave data register (smbus?d31:f3) register offset: smbase + 0ah?0bh attribute: ro default value: 0000h size: 16 bits lockable: no power well: resume this register contains the 16-bit data valu e written by the external smbus master. the processor can then read the value from this re gister. this register is reset by rsmrst#, but not pltrst# . 16.2.11 aux_sts?auxiliary status register (smbus?d31:f3) register offset: smbase + 0ch attribute: r/wc, ro default value: 00h size: 8 bits lockable: no power well: resume . bit description 7 reserved 6:0 slave_addr ? r/w. this field is the sl ave address that the intel ? ich8 decodes for read and write cycles. the default is not 0, so the smbus slave interface can respond even before the processor comes up (or if the processor is dead). this register is cleared by rsmrst#, but not by pltrst#. bit description 15:8 data message byte 1 (data_msg1) ? ro. see section 5.20.7 for a discussion of this field. 7:0 data message byte 0 (data_msg0) ? ro. see section 5.20.7 for a discussion of this field. bit description 7:2 reserved 1 smbus tco mode (stco) ? ro. this bit reflects the st rap setting of tco compatible mode vs. advanced tco mode. 0 = intel ? ich8 is in the compatible tco mode. 1 = ich8 is in the advanced tco mode. this register reflects the value of bit 7 in section 20.2.5.1 . 0 crc error (crce) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set if a received message contai ned a crc error. when this bit is set, the derr bit of the host status register will also be set. this bit will be set by the controller if a software abort occurs in the middle of the crc portion of the cycle or an abort happens after the ich8 has received the final data bit transmitted by an external slave. smbus controller registers (d31:f3) 638 intel ? ich8 family datasheet 16.2.12 aux_ctl?auxiliary cont rol register (smbus?d31:f3) register offset: smbase + 0dh attribute: r/w default value: 00h size: 8 bits lockable: no power well: resume . 16.2.13 smlink_pin_ctl?smlin k pin control register (smbus?d31:f3) register offset: smbase + 0eh attribute: r/w, ro default value: see below size: 8 bits note: this register is in the resume well and is reset by rsmrst#. this register is only applicable in the tco compatible mode. bit description 7:2 reserved 1 enable 32-byte buffer (e32b) ? r/w. 0 = disable. 1 = enable. when set, the host block data register is a pointer into a 32-byte buffer, as opposed to a single register. this enables the block commands to transfer or receive up to 32-bytes before the ic h8 generates an interrupt. 0 automatically append crc (aac) ? r/w. 0 = ich8 will not automatically append the crc. 1 = the ich8 will automatically append the crc. this bit must not be changed during smbus transactions or undetermined behavior will result. it should be programmed only once during the li fetime of the function. bit description 7:3 reserved 2 smlink_clk_ctl ? r/w. 0 = ich8 will drive the smlink0 pin low, in dependent of what the other smlink logic would otherwise indicate for the smlink0 pin. 1 = the smlink0 pin is not overdriven low. the other smlink logic controls the state of the pin. (default) 1 smlink1_cur_sts ? ro. this read-only bit has a de fault value that is dependent on an external signal level. th is pin returns the value on the smlink1 pin. this allows software to read the current state of the pin. 0 = low 1 = high 0 smlink0_cur_sts ? ro. this read-only bit has a de fault value that is dependent on an external signal level. th is pin returns the value on the smlink0 pin. this allows software to read the current state of the pin. 0 = low 1 = high intel ? ich8 family datasheet 639 smbus controller registers (d31:f3) 16.2.14 smbus_pin_ctl?smbu s pin control register (smbus?d31:f3) register offset: smbase + 0fh attribute: r/w, ro default value: see below size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 16.2.15 slv_sts?slave status register (smbus?d31:f3) register offset: smbase + 10h attribute: r/wc default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. all bits in this register are implemented in the 64 khz clock domain. therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. bit description 7:3 reserved 2 smbclk_ctl ? r/w. 0 = ich8 drives the smbclk pin low, indepe ndent of what the other smb logic would otherwise indicate for th e smbclk pin. (default) 1 = the smbclk pin is not overdriven low. the other smbus logic controls the state of the pin. 1 smbdata_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin return s the value on the smbdata pin. this allows software to read the cu rrent state of the pin. 0 = low 1 = high 0 smbclk_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal le vel. this pin returns the value on the smbclk pin. this allows software to read the cu rrent state of the pin. 0 = low 1 = high bit description 7:1 reserved 0 host_notify_sts ? r/wc. the ich8 sets this bit to a 1 when it has completely received a successful host notify command on the smlink pins. software reads this bit to determine that the source of the interru pt or smi# was the reception of the host notify command. software clears this bit after reading any information needed from the notify address and data regi sters by writing a 1 to this bit. note that the ich8 will allow the notify address and data registers to be over-written once this bit has been cleared. when this bit is 1, the ich8 will nack the first byte (hos t address) of any new ?host notify? commands on the smlink. writing a 0 to this bit has no effect. smbus controller registers (d31:f3) 640 intel ? ich8 family datasheet 16.2.16 slv_cmd?slave comman d register (smbus?d31:f3) register offset: smbase + 11h attribute: r/w default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 16.2.17 notify_daddr?notify device address register (smbus?d31:f3) register offset: smbase + 14h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. bit description 7:2 reserved 2 smbalert_dis ? r/w. 0 = allows the generation of the interrupt or smi#. 1 = software sets this bit to block the generation of the interrupt or smi# due to the smbalert# source. this bit is logi cally inverted and anded with the smbalert_sts bit (offset smbase + 00h, bi t 5). the resulting si gnal is distributed to the smi# and/or interrupt generation logic. this bi t does not effect the wake logic. 1 host_notify_wken ? r/w. software sets this bit to 1 to enable the reception of a host notify command as a wake event. when enabled this event is ?or??d in with the other smbus wake events and is reflecte d in the smb_wak_sts bit of the general purpose event 0 status register. 0 = disable 1 = enable 0 host_notify_intren ? r/w. software sets this bit to 1 to enable the generation of interrupt or smi# when host_notify_sts (offset smbase + 10h, bit 0) is 1. this enable does not affect the se tting of the host_notify_sts bit. when the interrupt is generated, either pirqb# or smi# is generated, depending on the value of the smb_smi_en bit (d31:f3:40h, bit 1). if the host_notify_sts bit is set when this bit is written to a 1, then the interrupt (or smi#) will be generated. the interrupt (or smi#) is logically generated by and?ing the sts and intren bits. 0 = disable 1 = enable bit description 7:1 device_address ? ro. this field contains the 7-bi t device address received during the host notify protocol of the smbus 2.0 sp ecification. software should only consider this field valid when the host_notify_sts bit (d31:f3:smbase +10, bit 0) is set to 1. 0 reserved intel ? ich8 family datasheet 641 smbus controller registers (d31:f3) 16.2.18 notify_dlow?notify data low byte register (smbus?d31:f3) register offset: smbase + 16h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 16.2.19 notify_dhigh?notify data high byte register (smbus?d31:f3) register offset: smbase + 17h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. bit description 7:0 data_low_byte ? ro. this field contains the firs t (low) byte of data received during the host notify protocol of the smbu s 2.0 specification. software should only consider this field valid when the host_n otify_sts bit (d31:f3:smbase +10, bit 0) is set to 1. bit description 7:0 data_high_byte ? ro. this field contains the second (high) byte of data received during the host notify protocol of the smbu s 2.0 specification. software should only consider this field valid when the host_n otify_sts bit (d31:f3: smbase +10, bit 0) is set to 1. smbus controller registers (d31:f3) 642 intel ? ich8 family datasheet intel ? ich8 family datasheet 643 intel ? high definition audio controller registers (d27:f0) 17 intel ? high definition audio controller registers (d27:f0) the intel high definition audio controller resi des in pci device 27, function 0 on bus 0. this function contains a set of dma engines that are used to move samples of digitally encoded data between system memory and external codecs. note: all registers in this function (including me mory-mapped registers) must be addressable in byte, word, and dword quantities. the software must always make register accesses on natural boundaries (i.e., dword accesses must be on dword boundaries; word accesses on word boundaries, etc.) in ad dition, the memory-mapped register space must not be accessed with the lock semantic exclusive-access mechanism. if software attempts exclusive-access mechanisms to the intel high definition audio memory- mapped space, the results are undefined. note: users interested in providing feedback on th e intel high definition audio specification or planning to implement the intel high definition audio specification into a future product will need to execute the intel ? high definition audio specification developer?s agreement . for more information, contact nextgenaudio@intel.com. 17.1 intel ? high definition audio pci configuration space (intel ? high definition audio? d27:f0) note: address locations that are not shown should be treated as reserved. table 139. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) offset mnemonic register name default access 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 03h ro 0bh bcc base class code 04h ro 0ch cls cache line size 00h r/w 0dh lt latency timer 00h ro 0eh headtyp header type 00h ro 10h?13h hdbarl intel ? high definition audio lower base address (memory) 00000004h r/w, ro 14h?17h hdbaru intel high definition audio upper base address (memory) 00000000h r/w 2ch?2dh svid subsystem vendor identification 0000h r/wo intel ? high definition audio controller registers (d27:f0) 644 intel ? ich8 family datasheet 2eh?2fh sid subsystem identification 0000h r/wo 34h capptr capability list pointer 50h ro 3ch intln interrupt line 00h r/w 3dh intpn interrupt pin see register description ro 40h hdctl intel high definiti on audio control 00h r/w, ro 44h tcsel traffic class select 00h r/w 4ch dckctl docking control (mobile only) 00h r/w, ro 4dh dcksts docking status (mobile only) 80h r/wo, ro 50h?51h pid pci power management capability id 6001h ro 52h?53h pc power management capabilities c842 ro 54h?57h pcs power management control and status 00000000h r/w, ro, r/wc 60h?61h mid msi capability id 7005h ro 62h?63h mmc msi message control 0080h r/w, ro 64h?67h mmla msi message lower address 00000000h r/w, ro 68h?6bh mmua smi message upper address 00000000h r/w 6ch?6dh mmd msi message data 0000h r/w 70h?71h pxid pci express* capability identifiers 0010h ro 72h?73h pxc pci express capabilities 0091h ro 74h?77h devcap device capabilities 00000000h ro, r/wo 78h?79h devc device control 0800h r/w, ro 7ah?7bh devs device status 0010h ro 100h?103h vccap virtual channel enhanced capability header 13010002h ro 104h?107h pvccap1 port vc capability register 1 00000001h ro 108h?10bh pvccap2 port vc capability register 2 00000000h ro 10ch?10d pvcctl port vc control 0000h ro 10eh?10fh pvcsts port vc status 0000h ro 110h?103h vc0cap vc0 resource capability 00000000h ro 114h?117h vc0ctl vc0 resource control 800000ffh r/w, ro 11ah?11bh vc0sts vc0 resource status 0000h ro 11ch?11fh vcicap vci resource capability 00000000h ro 120h?123h vcictl vci resource control 00000000h r/w, ro 126h?127h vcists vci resource status 0000h ro 130h?133h rccap root complex link declaration enhanced capability header 00010005h ro 134h?137h esd element self description 0f000100h ro table 139. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) offset mnemonic register name default access intel ? ich8 family datasheet 645 intel ? high definition audio controller registers (d27:f0) 17.1.1 vid?vendor identi fication register (intel ? high definition au dio controller?d27:f0) offset: 00h-01h attribute: ro default value: 8086h size: 16 bits 17.1.2 did?device identification register (intel ? high definition au dio controller?d27:f0) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 140h?143h l1desc link 1 description 00000001h ro 148h?14bh l1addl link 1 lower address see register description ro 14ch?14fh l1addu link 1 upper address 00000000h ro table 139. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) offset mnemonic register name default access bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bi t value assigned to the intel ? ich8 intel high definition audio controller. refer to the intel ? ich8 family specification update for the value of the device id register. intel ? high definition audio controller registers (d27:f0) 646 intel ? ich8 family datasheet 17.1.3 pcicmd?pci command register (intel ? high definition audio controller?d27:f0) offset address: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable (id) ? r/w. 0 = the intx# signals may be asserted. 1 = the intel ? high definition audio controller?s intx# signal will be de-asserted note that this bit does not affect the generation of msis. 9 fast back to back enable (fbe) ? ro. not implemented. hardwired to 0. 8 serr# enable (serr_en) ? r/w. serr# is not generated by the ich8 intel high definition audio controller. 7 wait cycle control (wcc) ? ro. no t implemented. hardwired to 0. 6 parity error response (per) ? ro. not implemented. hardwired to 0. 5 vga palette snoop (vps). not implemented. hardwired to 0. 4 memory write and invalidate enable (mwi e) ? ro. not implemented. hardwired to 0. 3 special cycle enable (sce). not implemented. hardwired to 0. 2 bus master enable (bme) ? r/w. this bit controls standard pci express* bus mastering capabilities for memory and i/o, reads and writes. note that this bit also controls msi generation since msis are essentially memory writes. 0 = disable 1 = enable 1 memory space enable (mse) ? r/w. this bit enables memory space addresses to the intel high definiti on audio controller. 0 = disable 1 = enable 0 i/o space enable (iose)?ro. hardwired to 0 since the intel high definition audio controller does not implement i/o space. intel ? ich8 family datasheet 647 intel ? high definition audio controller registers (d27:f0) 17.1.4 pcists?pci status register (intel ? high definition au dio controller?d27:f0) offset address: 06h ? 07h attribute: ro, r/wc default value: 0010h size: 16 bits 17.1.5 rid?revision identification register (intel ? high definition au dio controller?d27:f0) offset: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? ro . not implemented. hardwired to 0. 14 serr# status (serrs) ? ro. not implemented. hardwired to 0. 13 received master abort (rma) ? r/wc. software clears this bit by writing a 1 to it. 0 = no master abort received. 1 = the intel ? high definition audio co ntroller sets this bit when, as a bus master, it receives a master abort. wh en set, the intel high de finition audio controller clears the run bit for the chan nel that received the abort. 12 received target abort (rta) ? ro. not implemented. hardwired to 0. 11 signaled target abort (sta) ? ro. not implemented. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. does not apply. hardwired to 0. 8 data parity error detected (dped) ? ro. not implemented. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. does not apply. hardwired to 0. 6 reserved. 5 66 mhz capable (66mhz_cap) ? ro. does not apply. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 1. indicates that the controller contains a capabilities poin ter list. the first item is pointed to by looking at configuration offset 34h. 3 interrupt status (is) ? ro. 0 = this bit is 0 after th e interrupt is cleared. 1 = intx# is asserted. note that this bit is not set by an msi. 2:0 reserved. bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 8 (ich 8) family specification update for the value of the revision id register intel ? high definition audio controller registers (d27:f0) 648 intel ? ich8 family datasheet 17.1.6 pi?programming interface register (intel ? high definition audio controller?d27:f0) offset: 09h attribute: ro default value: 00h size: 8 bits 17.1.7 scc?sub class code register (intel ? high definition audio controller?d27:f0) address offset: 0ah attribute: ro default value: 03h size: 8 bits 17.1.8 bcc?base class code register (intel ? high definition audio controller?d27:f0) address offset: 0bh attribute: ro default value: 04h size: 8 bits 17.1.9 cls?cache line size register (intel ? high definition audio controller?d27:f0) address offset: 0ch attribute: r/w default value: 00h size: 8 bits 17.1.10 lt?latency timer register (intel ? high definition audio controller?d27:f0) address offset: 0dh attribute: ro default value: 00h size: 8 bits bit description 7:0 programming interface ? ro. bit description 7:0 sub class code (scc) ? ro. 03h = audio device bit description 7:0 base class code (bcc) ? ro. 04h = multimedia device bit description 7:0 cache line size ? r/w. implem ented as r/w register, but ha s no functional impact to the ich8 bit description 7:0 latency timer ? ro. hardwired to 00 intel ? ich8 family datasheet 649 intel ? high definition audio controller registers (d27:f0) 17.1.11 headtyp?header type register (intel ? high definition au dio controller?d27:f0) address offset: 0eh attribute: ro default value: 00h size: 8 bits 17.1.12 hdbarl?intel ? high definition audio lower base address register (intel ? high definition audio?d27:f0) address offset: 10h?13h attribute: r/w, ro default value: 00000004h size: 32 bits 17.1.13 hdbaru?intel ? high definition audio upper base address register (intel ? high definition audio controller?d27:f0) address offset: 14h?17h attribute: r/w default value: 00000000h size: 32 bits bit description 7:0 header type ? ro. hardwired to 00. bit description 31:14 lower base address (lba) ? r/w. base address for the intel ? high definition audio controller?s memory-mapped configuration re gisters. a 16 kb size are requested by hardwiring bits 13:4 to 0s. 13:4 ro. hardwired to 0?s 3 prefetchable (pref) ? ro. hardwired to 0 to indicate that this bar is not prefetchable 2:1 address range (addrng) ? ro. hardwired to 10b indicating that this bar can be located anywhere in 64-bit address space. 0 space type (sptyp) ? ro. hardwired to 0 in dicating this bar is located in memory space. bit description 31:0 upper base address (uba) ? r/w. this field contains th e upper 32 bits of the base address for the intel ? high definition audio controll er?s memory-mapped configuration registers. intel ? high definition audio controller registers (d27:f0) 650 intel ? ich8 family datasheet 17.1.14 svid?subsystem vendor identification register (intel ? high definition audio controller?d27:f0) address offset: 2ch?2dh attribute: r/wo default value: 0000h size: 16 bits the svid register, in combination with the subsystem id register (d27:f0:2eh), enable the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subseq uent writes will have no effect. this register is not affected by the d3 hot to d0 transition. 17.1.15 sid?subsystem identification register (intel ? high definition audio controller?d27:f0) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits the sid register, in combination with the subsystem vendor id register (d27:f0:2ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subseq uent writes will have no effect. this register is not affected by the d3 hot to d0 transition. t 17.1.16 capptr?capabilities poin ter register (audio?d30:f2) address offset: 34h attribute: ro default value: 50h size: 8 bits this register indicates the offset for the capability pointer. bit description 15:0 subsystem vendor id ? r/wo. bit description 15:0 subsystem id ? r/wo. bit description 7:0 capabilities pointer (cap_ptr) ? ro. this fiel d indicates that the fi rst capabili ty pointer offset is offset 50h (pow er management capability) intel ? ich8 family datasheet 651 intel ? high definition audio controller registers (d27:f0) 17.1.17 intln?interrup t line register (intel ? high definition au dio controller?d27:f0) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 17.1.18 intpn?interrupt pin register (intel ? high definition au dio controller?d27:f0) address offset: 3dh attribute: ro default value: see description size: 8 bits 17.1.19 hdctl?intel ? high definition au dio control register (intel ? high definition au dio controller?d27:f0) address offset: 40h attribute: r/w, ro default value: 00h size: 8 bits bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich8. it is used to communicate to software th e interrupt line that the in terrupt pin is connected to. bit description 7:4 reserved. 3:0 interrupt pin ? ro. this reflects the value of d2 7ip.zip (chipset configuration registers, offset 3110h, bits 3:0). bit description 7:1 reserved. 0 intel ? high definition signal mode ? ro. this bit is hardwired to 1 (high definition audio mode) intel ? high definition audio controller registers (d27:f0) 652 intel ? ich8 family datasheet 17.1.20 tcsel?traffic class select register (intel ? high definition audio controller?d27:f0) address offset: 44h attribute: r/w default value: 00h size: 8 bits this register assigned the value to be placed in the tc field. corb and rirb data will always be assigned tc0. 17.1.21 dckctl?docking control register (intel ? high definition audio controller?d27:f0) (mobile only) address offset: 4ch attribute: r/w, ro default value: 00h size: 8 bits bit description 7:3 reserved. 2:0 intel ? high definition audio traffi c class assignment (tcsel) ? r/w. this register assigns the value to be placed in the traffic class field for input data, output data, and buffer descriptor transactions. 000 = tc0 001 = tc1 010 = tc2 011 = tc3 100 = tc4 101 = tc5 110 = tc6 111 = tc7 note: these bits are not reset on d3 hot to d0 transition; however, they are reset by pltrst#. bit description 7:1 reserved. 0 dock attach (da) ? r/w / ro. software writes a 1 to this bit to initiate the docking sequence on the hda_dock_en# and hda_ dock_rst# signals. when the docking sequence is complete hardware will set th e dock mated (gsts.dm) status bit to 1. software writes a 0 to this bit to initiate the undocking sequence on the hda_dock_en# and hda_dock _rst# signals. when the undocking sequence is complete hardware will set the dock mated (gsts.dm) status bit to 0. note that software must ch eck the state of the dock mated (gsts.dm) bit prior to writing to the dock attach bit. software sh all only change the da bit from 0 to 1 when dm=0. likewise, software shall only change the da bit from 1 to 0 when dm=1. if these rules are violated, the results are undefined. note that this bit is read on ly when the dcksts.ds bit = 0. intel ? ich8 family datasheet 653 intel ? high definition audio controller registers (d27:f0) 17.1.22 dcksts?docking status register (intel ? high definition audio controller?d27:f0) (mobile only) address offset: 4dh attribute: r/wo, ro default value: 80h size: 8 bits 17.1.23 pid?pci power management capability id register (intel ? high definition au dio controller?d27:f0) address offset: 50h-51h attribute: ro default value: 6001h size: 16 bits bit description 7 docking supported (ds) ? r/wo. a 1 indicate s that ich8 supports hd audio docking. the dckctl.da bit is only writable when this ds bit is 1. acpi bios software should only branch to the docking routine when this ds bit is 1. bios may clear this bit to 0 to prohibit the acpi bios software from at tempting to run the docking routines. note that this bit is reset to its default value only on a pltrst#, but not on a crst# or d3hot-to-d0 transition. 6:1 reserved. 0 dock mated (dm) ? ro. this bit effectively communicates to software that an intel ? hd audio docked codec is physic ally and electrically attached. controller hardware sets this bit to 1 afte r the docking sequence triggered by writing a 1 to the dock attach (gctl.da) bit is co mpleted (hda_dock_rst# deassertion). this bit indicates to software that the docked co dec(s) may be discovered via the statests register and then enumerated. controller hardware sets this bit to 0 afte r the undocking sequence triggered by writing a 0 to the dock attach (gctl.da) bit is completed (hda_dock_en# deasserted). this bit indicates to software that the dock ed codec(s) may be physically undocked. bit description 15:8 next capability (next) ? ro. hardwired to 60h. points to th e next capability structure (msi) 7:0 cap id (cap) ? ro. hardwired to 01h. indi cates that this pointer is a pci power management capability. intel ? high definition audio controller registers (d27:f0) 654 intel ? ich8 family datasheet 17.1.24 pc?power management capabilities register (intel ? high definition audio controller?d27:f0) address offset: 52h-53h attribute: ro default value: c842h size: 16 bits 17.1.25 pcs?power management co ntrol and status register (intel ? high definition audio controller?d27:f0) address offset: 54h-57h attribute: ro, r/w, r/wc default value: 00000000h size: 32 bits bit description 15:11 pme support ? ro. hardwired to 11001b. indicates pme# can be generated from d3 and d0 states. 10 d2 support ? ro. hardwired to 0. indi cates that d2 state is not supported. 9 d1 support ?ro. hardwired to 0. indi cates that d1 state is not supported. 8:6 aux current ? ro. hardwired to 001b. repo rts 55 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi) ? ro. ha rdwired to 0. indicates that no device specific initialization is required. 4 reserved 3 pme clock (pmec) ? ro. does not apply. hardwired to 0. 2:0 version ? ro. hardwired to 010b. indicates support for version 1.1 of the pci power management specification. bit description 31:24 data ? ro. does not apply. hardwired to 0. 23 bus power/clock control enable ? ro . does not apply. hardwired to 0. 22 b2/b3 support ? ro. does not apply. hardwired to 0. 21:16 reserved. 15 pme status (pmes) ? r/wc. 0 = software clears the bit by writing a 1 to it. 1 = this bit is set when the intel ? high definition audio controller would normally assert the pme# signal independent of the state of the pme_en bit (bit 8 in this register) this bit is in the resume well and only clea red on a power-on rese t. software must not make assumptions about the reset state of this bit and must se t it appropriately. 14:9 reserved 8 pme enable (pmee) ? r/w. 0 = disable 1 = enable. when set and if corresponding pm es also set, the intel high definition audio controller sets the pme_b0_sts bit in the gpe0_sts register (pmbase +28h). this bit is in the resume well and only clea red on a power-on rese t. software must not make assumptions about the reset state of this bit and must se t it appropriately. 7:2 reserved intel ? ich8 family datasheet 655 intel ? high definition audio controller registers (d27:f0) 17.1.26 mid?msi capability id register (intel ? high definition au dio controller?d27:f0) address offset: 60h-61h attribute: ro default value: 7005h size: 16 bits 17.1.27 mmc?msi messag e control register (intel ? high definition au dio controller?d27:f0) address offset: 62h-63h attribute: ro, r/w default value: 0080h size: 16 bits 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the intel high definition audio co ntroller and to set a new power state. 00 = d0 state 11 = d3 hot state others = reserved notes: 1. if software attempts to write a value of 01b or 10b in to this field, the write operation must complete normally; howeve r, the data is discarded and no state change occurs. 2. when in the d3 hot states, the intel high defi nition audio controller?s configuration space is available, bu t the i/o and memory space are not. additionally, interrupts are blocked. 3. when software changes this value from d3 hot state to the d0 st ate, an internal warm (soft) reset is generated, and so ftware must re-initialize the function. bit description bit description 15:8 next capability (next) ? ro. hardwired to 70h. points to the pci express* capability structure. 7:0 cap id (cap) ? ro. hardwired to 05h. indi cates that this pointer is a msi capability bit description 15:8 reserved 7 64b address capability (64add) ? ro. hardwire d to 1. indicates the ability to generate a 64-bit message address 6:4 multiple message enable (mme) ? ro. normally this is a r/w regi ster. however, since only 1 message is supported, these bi ts are hardwired to 000 = 1 message. 3:1 multiple message capable (mmc) ? ro. ha rdwired to 0 indicating request for 1 message. 0 msi enable (me) ? r/w. 0 = msi may not be generated 1 = msi will be generated in stead of an intx signal. intel ? high definition audio controller registers (d27:f0) 656 intel ? ich8 family datasheet 17.1.28 mmla?msi message lower address register (intel ? high definition audio controller?d27:f0) address offset: 64h-67h attribute: ro, r/w default value: 00000000h size: 32 bits 17.1.29 mmua?msi message upper address register (intel ? high definition audio controller?d27:f0) address offset: 68h-6bh attribute: r/w default value: 00000000h size: 32 bits 17.1.30 mmd?msi messag e data register (intel ? high definition audio controller?d27:f0) address offset: 6ch-6dh attribute: r/w default value: 0000h size: 16 bits 17.1.31 pxid?pci express* capability id register (intel ? high definition audio controller?d27:f0) address offset: 70h-71h attribute: ro default value: 0010h size: 16 bits bit description 31:2 message lower address (mla) ? r/w. lower address used for msi message. 1:0 reserved. bit description 31:0 message upper address (mua) ? r/w. upper 32-bits of address used for msi message. bit description 15:0 message data (md) ? r/w. data used for msi message. bit description 15:8 next capability (next) ? ro. ha rdwired to 0. indicates that this is the last capability structure in the list. 7:0 cap id (cap) ? ro. hardwired to 10h. indica tes that this pointer is a pci express* capability structure intel ? ich8 family datasheet 657 intel ? high definition audio controller registers (d27:f0) 17.1.32 pxc?pci express* capabilities register (intel ? high definition au dio controller?d27:f0) address offset: 72h-73h attribute: ro default value: 0091h size: 16 bits 17.1.33 devcap?device ca pabilities register (intel ? high definition au dio controller?d27:f0) address offset: 74h-77h attribute: r/wo, ro default value: 00000000h size: 32 bits bit description 15:14 reserved 13:9 interrupt message number (imn) ? ro. hardwired to 0. 8 slot implemented (si) ? ro. hardwired to 0. 7:4 device/port type (dpt) ? ro. hardwired to 1001b. indicates that this is a root complex integrated endpoint device. 3:0 capability version (cv) ? ro. hardwired to 0001b. indicates version #1 pci express capability bit description 31:28 reserved 27:26 captured slot power limit sc ale (spls) ? ro. hardwired to 0. 25:18 captured slot power limit va lue (splv) ? ro. hardwired to 0. 17:15 reserved 14 power indicator present ? ro. hardwired to 0. 13 attention indicator present ? ro. hardwired to 0. 12 attention button presen t ? ro. hardwired to 0. 11:9 endpoint l1 acceptable latency ? r/wo. 8:6 endpoint l0s acceptable latency ? r/wo. 5 extended tag field support ? ro. hardwire d to 0. indicates 5- bit tag field support 4:3 phantom functions supported ? ro. hardwired to 0. indicates that phantom functions not supported 2:0 max payload size supported ? ro. hardwire d to 0. indicates 128-b maximum payload size capability intel ? high definition audio controller registers (d27:f0) 658 intel ? ich8 family datasheet 17.1.34 devc?device control register (intel ? high definition audio controller?d27:f0) address offset: 78h-79h attribute: r/w, ro default value: 0800h size: 16 bits bit description 15 reserved 14:12 max read request size ? ro. hardwired to 0 enabling 128b maximum read request size. 11 no snoop enable (nsnpen) ? r/w. 0 = the intel ? high definition audio controller will not set the no snoop bit. in this case, isochronous transfers will not use vc1 (vci) even if it is enabled since vc1 is never snooped. isochronous transfers will use vc0. 1 = the intel high definition audio controller is permitted to set the no snoop bit in the requester attributes of a bus master transaction. in this case, vc0 or vc1 may be used for isochronous transfers. note: this bit is not reset on d3 hot to d0 transition; however, it is reset by pltrst#. 10 auxiliary power enable ? ro. hardwired to 0, indicating that intel high definition audio device does not draw aux power 9 phantom function enable ? ro. hardwi red to 0 disabling phantom functions. 8 extended tag field enable ? ro. ha rdwired to 0 enabling 5-bit tag. 7:5 max payload size ? ro. hardwired to 0 indicating 128b. 4 enable relaxed ordering ? ro. hardwi red to 0 disabling relaxed ordering. 3 unsupported request reporting enable ? ro. not implemented. hardwired to 0. 2 fatal error reporting enable ? ro . not implemented. hardwired to 0. 1 non-fatal error reporting enable ? ro. not implemented. hardwired to 0. 0 correctable error reporting enable ? ro. not implemented. hardwired to 0. intel ? ich8 family datasheet 659 intel ? high definition audio controller registers (d27:f0) 17.1.35 devs?device status register (intel ? high definition au dio controller?d27:f0) address offset: 7ah-7bh attribute: ro default value: 0010h size: 16 bits 17.1.36 vccap?virtual channel enhanced capability header (intel ? high definition au dio controller?d27:f0) address offset: 100h-103h attribute: ro default value: 13010002h size: 32 bits bit description 15:6 reserved 5 transactions pending ? ro. 0 = completions for all non-posted requests have been received 1 = intel ? high definition audio controller has issued non-posted requests that have not been completed. 4 aux power detected ? ro. hardwired to 1 indi cating the device is connected to resume power 3 unsupported request detected ? ro . not implemented. hardwired to 0. 2 fatal error detected ? ro. no t implemented. hardwired to 0. 1 non-fatal error detected ? ro. not implemented. hardwired to 0. 0 correctable error detected ? ro. not implemented. hardwired to 0. bit description 31:20 next capability offset ? ro. hardwired to 130h. points to the next capability header, which is the root complex link decl aration enhanced capability header. 19:16 capability version ? ro. hardwired to 1h. 15:0 pci express* extended capabi lity ? ro. hardwired to 0002h. intel ? high definition audio controller registers (d27:f0) 660 intel ? ich8 family datasheet 17.1.37 pvccap1?port vc capability register 1 (intel ? high definition audio controller?d27:f0) address offset: 104h-107h attribute: ro default value: 00000001h size: 32 bits 17.1.38 pvccap2 ? port vc capability register 2 (intel ? high definition audio controller?d27:f0) address offset: 108h-10bh attribute: ro default value: 00000000h size: 32 bits 17.1.39 pvcctl ? port vc control register (intel ? high definition audio controller?d27:f0) address offset: 10ch-10dh attribute: ro default value: 0000h size: 16 bits bit description 31:12 reserved. 11:10 port arbitration table entry size ? ro. hard wired to 0 since this is an endpoint device. 9:8 reference clock ? ro. hardwired to 0 since this is an endpoint device. 7 reserved. 6:4 low priority extended vc count ? ro. hardwired to 0. indicates that only vc0 belongs to the low priority vc group 3 reserved. 2:0 extended vc count ? ro. hardwired to 001b. indicates that 1 extended vc (in addition to vc0) is supported by the intel ? high definition audio controller. bit description 31:24 vc arbitration table offset ? ro. hardwired to 0 indicating that a vc arbitration table is not present. 23:8 reserved. 7:0 vc arbitration capability ? ro. hardwired to 0. these bits are not applicable since the intel ? high definition audio controller report s a 0 in the low priority extended vc count bits in the pvccap1 register. bit description 15:4 reserved. 3:1 vc arbitration select ? ro. hardwired to 0. normally these bits are r/w. however, these bits are not applicable since the intel ? high definition audio controller reports a 0 in the low priority extended vc count bits in the pvccap1 register. 0 load vc arbitration table ? ro. hardwired to 0 since an arbitration table is not present. intel ? ich8 family datasheet 661 intel ? high definition audio controller registers (d27:f0) 17.1.40 pvcsts?port vc status register (intel ? high definition au dio controller?d27:f0) address offset: 10eh?10fh attribute: ro default value: 0000h size: 16 bits 17.1.41 vc0cap?vc0 resour ce capability register (intel ? high definition au dio controller?d27:f0) address offset: 110h?113h attribute: ro default value: 00000000h size: 32 bits 17.1.42 vc0ctl?vc0 reso urce control register (intel ? high definition au dio controller?d27:f0) address offset: 114h?117h attribute: r/w, ro default value: 800000ffh size: 32 bits bit description 15:1 reserved. 0 vc arbitration table status ? ro. hardwire d to 0 since an arbitration table is not present. bit description 31:24 port arbitration table offset ? ro. hardwire d to 0 since this field is not valid for endpoint devices 23 reserved. 22:16 maximum time slots ? ro. hardwired to 0 si nce this field is not valid for endpoint devices 15 reject snoop transactions ? ro. hardwired to 0 since this field is not valid for endpoint devices. 14 advanced packet switching ? ro. hardwired to 0 since this field is not valid for endpoint devices 13:8 reserved. 7:0 port arbitration capability ? ro. hardwired to 0 since this field is not valid for endpoint devices bit description 31 vc0 enable ? ro. hardwired to 1 for vc0. 30:27 reserved. 26:24 vc0 id ? ro. hardwired to 0 since th e first vc is always assigned as vc0. 23:20 reserved. 19:17 port arbitration select ? ro. hardwired to 0 since this field is not valid for endpoint devices. 16 load port arbitration table ? ro. hardwired to 0 since this field is not valid for endpoint devices. 15:8 reserved. 7:0 tc/vc0 map ? r/w, ro. bit 0 is hardwired to 1 si nce tc0 is always mapped vc0. bits 7:1 are implemented as r/w bits. intel ? high definition audio controller registers (d27:f0) 662 intel ? ich8 family datasheet 17.1.43 vc0sts?vc0 resource status register (intel ? high definition audio controller?d27:f0) address offset: 11ah?11bh attribute: ro default value: 0000h size: 16 bits 17.1.44 vcicap?vci resour ce capability register (intel ? high definition audio controller?d27:f0) address offset: 11ch?11fh attribute: ro default value: 00000000h size: 32 bits bit description 15:2 reserved. 1 vc0 negotiation pending ? ro. hardwired to 0 since this bit does not apply to the integrated intel ? high definition audio device. 0 port arbitration table status ? ro. hardwire d to 0 since this field is not valid for endpoint devices. bit description 31:24 port arbitration table offset ? ro. hardwire d to 0 since this field is not valid for endpoint devices. 23 reserved. 22:16 maximum time slots ? ro. hardwired to 0 si nce this field is not valid for endpoint devices. 15 reject snoop transactions ? ro. hardwired to 0 since this field is not valid for endpoint devices. 14 advanced packet switching ? ro. hardwired to 0 since this field is not valid for endpoint devices. 13:8 reserved 7:0 port arbitration capability ? ro. hardwired to 0 since this field is not valid for endpoint devices. intel ? ich8 family datasheet 663 intel ? high definition audio controller registers (d27:f0) 17.1.45 vcictl?vci reso urce control register (intel ? high definition au dio controller?d27:f0) address offset: 120h?123h attribute: r/w, ro default value: 00000000h size: 32 bits 17.1.46 vcists?vci resource status register (intel ? high definition au dio controller?d27:f0) address offset: 126h?127h attribute: ro default value: 0000h size: 16 bits bit description 31 vci enable ? r/w. 0 = disabled 1 = enabled note: this bit is not reset on d3 hot to d0 transition; however, it is reset by pltrst#. 30:27 reserved. 26:24 vci id ? r/w. this field assigns a vc id to th e vci resource. this field is not used by the ich8 hardware, but it is r/ w to avoid confusing software. 23:20 reserved. 19:17 port arbitration select ? ro. hardwired to 0 since this field is not valid for endpoint devices 16 load port arbitration table ? ro. hardwired to 0 since this field is not valid for endpoint devices 15:8 reserved. 7:0 tc/vci map ? r/w, ro. this field indicates the tcs that are mapped to the vci resource. bit 0 is hardwired to 0 indicating th at it cannot be mapped to vci. bits [7:1] are implemented as r/w bits. th is field is not used by the ich8 hardware, but it is r/w to avoid confusing software. bit description 15:2 reserved. 1 vci negotiation pending ? ro. does not apply. hardwired to 0. 0 port arbitration table status ? ro. hardwire d to 0 since this field is not valid for endpoint devices. intel ? high definition audio controller registers (d27:f0) 664 intel ? ich8 family datasheet 17.1.47 rccap?root complex link declaration enhanced capability header register (intel ? high definition audio controller?d27:f0) address offset: 130h attribute: ro default value: 00010005h size: 32 bits 17.1.48 esd?element self description register (intel ? high definition audio controller?d27:f0) address offset: 134h?137h attribute: ro default value: 0f000100h size: 32 bits 17.1.49 l1desc?link 1 description register (intel ? high definition audio controller?d27:f0) address offset: 140h?143h attribute: ro default value: 00000001h size: 32 bits bit description 31:20 next capability offset ? ro. hardwired to 0 indicating this is the last capability. 19:16 capability version ? ro. hardwired to 1h. 15:0 pci express* extended capability id ? ro. hardwired to 0005h. bit description 31:24 port number ? ro. hardwired to 0fh indicating that the intel ? high definition audio controller is assigned as port #15d. 23:16 component id ? ro. this field returns the value of the esd.cid field of the chip configuration section. esd.cid is programmed by bios. 15:8 number of link entries ? ro. the intel hi gh definition audio only connects to one device, the ich8 egress port. therefor e this field reports a value of 1h. 7:4 reserved. 3:0 element type (eltyp) ? ro. the intel high defi nition audio controller is an integrated root complex device. therefore, the field reports a value of 0h. bit description 31:24 target port number ? ro. the intel high de finition audio controll er targets the intel ? ich8?s port #0. 23:16 target component id ? ro. this field returns the value of th e esd.cid field of the chip configuration section. esd.cid is programmed by bios. 15:2 reserved. 1 link type ? ro. hardwired to 0 indicating type 0. 0 link valid ? ro. hardwired to 1. intel ? ich8 family datasheet 665 intel ? high definition audio controller registers (d27:f0) 17.1.50 l1addl?link 1 lo wer address register (intel ? high definition au dio controller?d27:f0) address offset: 148h?14bh attribute: ro default value: see register description size: 32 bits 17.1.51 l1addu?link 1 upper address register (intel ? high definition au dio controller?d27:f0) address offset: 14ch?14fh attribute: ro default value: 00000000h size: 32 bits bit description 31:14 link 1 lower address ? ro. hardwired to matc h the rcba register value in the pci-lpc bridge (d31:f0:f0h). 13:0 reserved. bit description 31:0 link 1 upper address ? ro. hardwired to 00000000h. intel ? high definition audio controller registers (d27:f0) 666 intel ? ich8 family datasheet 17.2 intel ? high definition audio memory mapped configuration registers (intel ? high definition audio? d27:f0) the base memory location for these memory-mapped configuration registers is specified in the hdbar register (d27:f0, offset 10h and d27:f0, offset 14h). the individual registers are then accessible at hdbar + offset as indicated in the following table. these memory-mapped registers must be acce ssed in byte, word, or dword quantities. table 140. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 1 of 4) hdbar + offset mnemonic register name default access 00h?01h gcap global capabilities 4401h ro 02h vmin minor version 00h ro 03h vmaj major version 01h ro 04h?05h outpay output payload capability 003ch ro 06h?07h inpay input payload capability 001dh ro 08h?0bh gctl global control 00000000h r/w 0ch?0dh wakeen wake enable 0000h r/w 0eh?0fh statests state change status 0000h r/wc 10h?11h gsts global status 0000h r/wc 12h?13h rsv reserved 0000h ro 14h?17h ecap extended capabilities 00000001h ro 18h?19h outstrmpay output stream payload capability 0030h ro 1ah?1bh instrmpay input stream payload capability 0018h ro 1ch?1fh rsv reserved 00000000h ro 20h?23h intctl interrupt control 00000000h r/w 24h?27h intsts interrupt status 00000000h ro 30h?33h walclk wall clock counter 00000000h ro 34h?37h ssync stream synchronization 00000000h r/w 40h?43h corblbase corb lower base address 00000000h r/w, ro 44h?47h corbubase corb upper base address 00000000h r/w 48h?49h corbwp corb write pointer 0000h r/w 4ah?4bh corbrp corb read pointer 0000h r/w 4ch corbctl corb control 00h r/w 4dh corbst corb status 00h r/wc 4eh corbsize corb size 42h ro 50h?53h rirblbase rirb lower base address 00000000h r/w, ro 54h?57h rirbubase rirb upper base address 00000000h r/w 58h?59h rirbwp rirb write pointer 0000h r/w, ro intel ? ich8 family datasheet 667 intel ? high definition audio controller registers (d27:f0) 5ah?5bh rintcnt response interrupt count 0000h r/w 5ch rirbctl rirb control 00h r/w 5dh rirbsts rirb status 00h r/wc 5eh rirbsize rirb size 42h ro 60h?63h ic immediate command 00000000h r/w 64h?67h ir immediate response 00000000h ro 68h?69h irs immediate command status 0000h r/w, r/ wc 70h?73h dplbase dma position lower base address 00000000h r/w, ro 74h?77h dpubase dma position upper base address 00000000h r/w 80?82h isd0ctl input stream desc riptor 0 (isd0) control 040000h r/w, ro 83h isd0sts isd0 status 00h r/wc, ro 84h?87h isd0lpib isd0 link position in buffer 00000000h ro 88h?8bh isd0cbl isd0 cyclic buffer length 00000000h r/w 8ch?8dh isd0lvi isd0 last valid index 0000h r/w 8eh?8f isd0fifow isd0 fifo watermark 0004h r/w 90h?91h isd0fifos isd0 fifo size 0077h ro 92h?93h isd0fmt isd0 format 0000h r/w 98h?9bh isd0bdpl isd0 buffer descriptor list pointer- lower base address 00000000h r/w, ro 9ch?9fh isd0bdpu isd0 buffer description list pointer- upper base address 00000000h r/w a0h?a2h isd1ctl input stream desc riptor 1(isd01) control 040000h r/w, ro a3h isd1sts isd1 status 00h r/wc, ro a4h?a7h isd1lpib isd1 link position in buffer 00000000h ro a8h?abh isd1cbl isd1 cyclic buffer length 00000000h r/w ach?adh isd1lvi isd1 last valid index 0000h r/w aeh?afh isd1fifow isd1 fifo watermark 0004h r/w b0h?b1h isd1fifos isd1 fifo size 0077h ro b2h?b3h isd1fmt isd1 format 0000h r/w b8h?bbh isd1bdpl isd1 buffer descriptor list pointer- lower base address 00000000h r/w, ro bch?bfh isd1bdpu isd1 buffer description list pointer- upper base address 00000000h r/w c0h?c2h isd2ctl input stream desc riptor 2 (isd2) control 040000h r/w, ro c3h isd2sts isd2 status 00h r/wc, ro table 140. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 2 of 4) hdbar + offset mnemonic register name default access intel ? high definition audio controller registers (d27:f0) 668 intel ? ich8 family datasheet c4h?c7h isd2lpib isd2 link position in buffer 00000000h ro c8h?cbh isd2cbl isd2 cyclic buffer length 00000000h r/w cch?cdh isd2lvi isd2 last valid index 0000h r/w ceh?cfh isd1fifow isd1 fifo watermark 0004h r/w d0h?d1h isd2fifos isd2 fifo size 0077h ro d2h?d3h isd2fmt isd2 format 0000h r/w d8h?dbh isd2bdpl isd2 buffer descriptor list pointer- lower base address 00000000h r/w, ro dch?dfh isd2bdpu isd2 buffer descripti on list pointer- upper base address 00000000h r/w e0h?e2h isd3ctl input stream descriptor 3 (isd3) control 040000h r/w, ro e3h isd3sts isd3 status 00h r/wc, ro e4h?e7h isd3lpib isd3 link position in buffer 00000000h ro e8h?ebh isd3cbl isd3 cyclic buffer length 00000000h r/w ech?edh isd3lvi isd3 last valid index 0000h r/w eeh?efh isd3fifow isd3 fifo watermark 0004h r/w f0h?f1h isd3fifos isd3 fifo size 0077h ro f2h?f3h isd3fmt isd3 format 0000h r/w f8h?fbh isd3bdpl isd3 buffer descriptor list pointer- lower base address 00000000h r/w, ro fch?ffh isd3bdpu isd3 buffer descripti on list pointer- upper base address 00000000h r/w 100h?102h osd0ctl output stream descriptor 0 (osd0) control 040000h r/w, ro 103h osd0sts osd0 status 00h r/wc, ro 104h?107h osd0lpib osd0 link position in buffer 00000000h ro 108h?10bh osd0cbl osd0 cyclic buffer length 00000000h r/w 10ch?10dh osd0lvi osd0 last valid index 0000h r/w 10eh?10fh osd0fifow osd0 fifo watermark 0004h r/w 110h?111h osd0fifos osd0 fifo size 00bfh r/w 112h?113h osd0fmt osd0 format 0000h r/w 118h?11bh osd0bdpl osd0 buffer descript or list pointer- lower base address 00000000h r/w, ro 11ch?11fh osd0bdpu osd0 buffer descript ion list pointer- upper base address 00000000h r/w 120h?122h osd1ctl output stream descriptor 1 (osd1) control 040000h r/w, ro 123h osd1sts osd1 status 00h r/wc, ro table 140. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 3 of 4) hdbar + offset mnemonic register name default access intel ? ich8 family datasheet 669 intel ? high definition audio controller registers (d27:f0) 124h?127h osd1lpib osd1 link position in buffer 00000000h ro 128h?12bh osd1cbl osd1 cyclic buffer length 00000000h r/w 12ch?12dh osd1lvi osd1 last valid index 0000h r/w 12eh?12fh osd1fifow osd1 fifo watermark 0004h r/w 130h?131h osd1fifos osd1 fifo size 00bfh r/w 132h?133h osd1fmt osd1 format 0000h r/w 138h?13bh osd1bdpl osd1 buffer descrip tor list pointer- lower base address 00000000h r/w, ro 13ch?13fh osd1bdpu osd1 buffer descripti on list pointer- upper base address 00000000h r/w 140h?142h osd2ctl output stream descriptor 2 (osd2) control 040000h r/w, ro 143h osd2sts osd2 status 00h r/wc, ro 144h?147h osd2lpib osd2 link position in buffer 00000000h ro 148h?14bh osd2cbl osd2 cyclic buffer length 00000000h r/w 14ch?14dh osd2lvi osd2 last valid index 0000h r/w 14eh?14fh osd2fifow osd2 fifo watermark 0004h r/w 150h?151h osd2fifos osd2 fifo size 00bfh r/w 152h?153h osd2fmt osd2 format 0000h r/w 158h?15bh osd2bdpl osd2 buffer descrip tor list pointer- lower base address 00000000h r/w, ro 15ch?15fh osd2bdpu osd2 buffer descripti on list pointer- upper base address 00000000h r/w 160h?162h osd3ctl output stream descriptor 3 (osd3) control 040000h r/w, ro 163h osd3sts osd3 status 00h r/wc, ro 164h?167h osd3lpib osd3 link position in buffer 00000000h ro 168h?16bh osd3cbl osd3 cyclic buffer length 00000000h r/w 16ch?16dh osd3lvi osd3 last valid index 0000h r/w 16eh?16fh osd3fifow osd3 fifo watermark 0004h r/w 170h?171h osd3fifos osd3 fifo size 00bfh r/w 172h?173h osd3fmt osd3 format 0000h r/w 178h?17bh osd3bdpl osd3 buffer descrip tor list pointer- lower base address 00000000h r/w, ro 17ch?17fh osd3bdpu osd3 buffer descripti on list pointer- upper base address 00000000h r/w table 140. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 4 of 4) hdbar + offset mnemonic register name default access intel ? high definition audio controller registers (d27:f0) 670 intel ? ich8 family datasheet 17.2.1 gcap?global capabilities register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 00h attribute: ro default value: 4401h size: 16 bits 17.2.2 vmin?minor ve rsion register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 02h attribute: ro default value: 00h size: 8 bits 17.2.3 vmaj?major version register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 03h attribute: ro default value: 01h size: 8 bits bit description 15:12 number of output stream supported ? ro. hardwired to 0100b indicating that the ich8 intel ? high definition audio contro ller supports 4 output streams. 11:8 number of input stream supported ? ro. hardwired to 0100b indicating that the ich8 intel high definition audio cont roller supports 4 input streams. 7:3 number of bidirectional stream supported ? ro. hardwired to 0 indicating that the ich8 intel high definition audio cont roller supports 0 bidirectional stream. 2 reserved. 1 number of serial data out signals ? ro. hardwired to 0 indicating that the ich8 intel high definition audio controller su pports 1 serial data output signal. 0 64-bit address supported ? ro. hardwired to 1b indicating that the ich8 intel high definition audio controller supports 64-bit addressing for bdl addresses, data buffer addressees, and comma nd buffer addresses. bit description 7:0 minor version ? ro. hardwired to 0 indicating that the intel ? ich8 supports minor revision number 00h of the intel ? high definition audio specification. bit description 7:0 major version ? ro. hardwired to 01h indicating that the intel ? ich8 supports major revision number 1 of the intel ? high definition audio specification. intel ? ich8 family datasheet 671 intel ? high definition audio controller registers (d27:f0) 17.2.4 outpay?output payloa d capability register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 04h attribute: ro default value: 003ch size: 16 bits 17.2.5 inpay?input payloa d capability register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 06h attribute: ro default value: 001dh size: 16 bits bit description 15:7 reserved. 6:0 output payload capability ? ro. hardwired to 3ch indicating 60 word payload. this field indicates the total output payload available on the link. this does not include bandwidth used for command and control. this measurement is in 16-bit word quantities per 48 mhz frame. the default link clock of 24.000 mhz (the data is double pumped) provides 1000 bits per frame, or 62. 5 words in total. 40 bits are used for command and control, leaving 60 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... ffh = 256 word payload. bit description 15:7 reserved. 6:0 input payload capability ? ro. hardwired to 1dh indicating 29 word payload. this field indicates the total output payload available on the link. this does not include bandwidth used for response. this measurement is in 16-b it word quantities per 48 mhz frame. the default link clock of 24.000 mhz provides 500 bits per frame, or 31.25 words in total. 36 bits are used for response, leaving 29 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... ffh = 256 word payload. intel ? high definition audio controller registers (d27:f0) 672 intel ? ich8 family datasheet 17.2.6 gctl?global control register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 08h attribute: r/w default value: 00000000h size: 32 bits bit description 31:9 reserved. 8 accept unsolicited response enable ? r/w. 0 = unsolicited responses from the codecs are not accepted. 1 = unsolicited response from the codecs are accepted by the controller and placed into the response input ring buffer. 7:2 reserved. 1 flush control ? r/w. writing a 1 to this bit initiates a flush. when the flush completion is received by the controller, ha rdware sets the flush status bit and clears this flush control bit. before a flush cycle is initiated, the dma position buffer must be programmed with a valid memory address by software, but the dma position buffer bit 0 needs not be set to enable the positi on reporting mechanis m. also, all streams must be stopped (the associ ated run bit must be 0). when the flush is initiated, the controller will flush the pipelines to memory to assure that the hardware is ready to transition to a d3 state. setting this bit is not a critical step in the power state transition if the content of the fifios is not critical. 0 controller reset # ? r/w. 0 = writing a 0 resets the intel high defini tion audio controller. all state machines, fifos and non-resume well memory mapped configuration registers (not pci configuration registers) in the controller will be reset. the in tel high definition audio link reset# signal will be asserted, and all other link sign als will be driven to their default values. after the hardware has completed sequencing into the reset state, it will report a 0 in this bit. software must read a 0 from this bit to verify the controller is in reset. 1 = writing a 1 causes the controller to ex it its reset state and de-assert the intel high definition audio link reset# sign al. software is resp onsible for setting/ clearing this bit such that the minimum intel high definition audio link reset# signal assertion pulse width specification is met. when the controller hardware is ready to begin operation, it will report a 1 in this bit. software must read a 1 from this bit before accessing any controller re gisters. this bit defaults to a 0 after hardware reset, therefore, software ne eds to write a 1 to this bit to begin operation. notes: 1. the corb/rirb run bits and all stream ru n bits must be verified cleared to 0 before writing a 0 to this bit in order to assure a clean re-start. 2. when setting or clearing this bit, so ftware must ensure that minimum link timing requirements (minimum rese t# assertion time, etc.) are met. 3. when this bit is 0 indicating that the co ntroller is in reset, writes to all intel high definition audio memo ry mapped registers are igno red as if the device is not present. the only exception is this register itself. the global control register is write-able as a dword, word, or byte even when crst# (this bit) is 0 if the byte enable for the byte containing the crst# bit (byte enable 0) is active. if byte enable 0 is not active, wr ites to the global control register will be ignored when crst# is 0. when crst# is 0, reads to intel high definition audio memory mapped registers will re turn their default value except for registers that are not reset with pltr st# or on a d3hot to d0 transition. intel ? ich8 family datasheet 673 intel ? high definition audio controller registers (d27:f0) 17.2.7 wakeen?wake enable register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 0ch attribute: r/w default value: 0000h size: 16 bits 17.2.8 statests?state change status register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 0eh attribute: r/wc default value: 0000h size: 16 bits bit description 15:4 reserved. 3:0 sdin wake enable flags ? r/w. these bits control which sdi signal(s) may generate a wake event. a 1b in the bit mask indicates that the associated sdin signal is enabled to generate a wake. bit 0 is used for sdi[0] bit 1 is used for sdi[1] bit 2 is used for sdi[2] bit 3 is used for sdi[3] note: these bits are in the resume well an d only cleared on a power on reset. software must not make as sumptions about the reset state of these bits and must set them appropriately. bit description 15:4 reserved. 3:0 sdin state change status flags ? r/wc. flag bits that in dicate which sdi signal(s) received a state change event. the bits are cleared by writing 1?s to them. bit 0 = sdi[0] bit 1 = sdi[1] bit 2 = sdi[2] bit 3 = sdi[3] note: these bits are in the resume well an d only cleared on a power on reset. software must not make as sumptions about the reset state of these bits and must set them appropriately. intel ? high definition audio controller registers (d27:f0) 674 intel ? ich8 family datasheet 17.2.9 gsts?global status register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 10h attribute: r/wc default value: 0000h size: 16 bits bit description 15:4 reserved. 3 (mobile only) dock mated interrupt status (dmis) ? r/w/c. a 1 indicates that the dock mating or unmating process has completed. for the docking process it indicates that dock is electrically connected and that software may detect and enumerate the docked codecs. for the undocking process it indicates that the dock is electrically isolated and that software may report to the user that physical undocking may commence. this bit gets set to a 1 by hardware when the dm bit transitions from a 0 to a 1 (docking) or from a 1 to a 0 (undocking). note that this bit is set regardless of the state of the dmie bit. software clears this bit by writing a 1 to it. writing a 0 to this bit has no affect. 3 (desktop only) reserved 2 (mobile only) dock mated (dm) ?ro . this bit effectively communicates to software that an intel ? hd audio docked codec is physic ally and electrically attached. controller hardware sets this bit to 1 afte r the docking sequence triggered by writing a 1 to the dock attach (gctl.da) bit is completed (hda_dock_rst# deassertion). this bit indicates to software that the do cked codec(s) may be discovered via the statests register and then enumerated. controller hardware sets this bit to 0 after the undocking se quence triggered by writing a 0 to the dock attach (gctl.da) bit is completed (dock_en# deasserted). this bit indicates to software that the do cked codec(s) may be physically undocked. this bit is read only. writes to this bit have no effect. 2 (desktop only) reserved 1 flush status ? r/wc. this bit is set to 1 by ha rdware to indicate that the flush cycle initiated when the flush control bit (hdbar + 08h, bit 1) was set has completed. software must write a 1 to clea r this bit before the next time the flush control bit is set to clear the bit. 0 reserved. intel ? ich8 family datasheet 675 intel ? high definition audio controller registers (d27:f0) 17.2.10 ecap?extende d capabilities (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 14h attribute: r/wo default value: 00000001h size: 32 bits 17.2.11 outstrmpay?output st ream payload capability (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 18h attribute: ro default value: 0030h size: 16 bits bit description 31:1 reserved 0 docking supported (ds) ? r/wo. a 1 indicates that intel ? ich8 supports intel ? hd audio docking. the gctl.da bit is only writab le when this ds bit is 1. intel hd audio driver software should only branch to its do cking routine when this ds bit is 1. bios may clear this bit to 0 to prohibit the intel hd audio driver software from attempting to run the docking routines. note that this bit is reset to its default value only on a pltrst#, but not on a crst# or d3 hot -to-d0 transition. bit description 15:14 output fifo padding type (opadtype) ? ro. this field indicates how the controller pads the samples in the controller 's buffer (fifo). controllers may not pad at all or may pad to byte or memory container sizes. 0h = controller pads all samples to bytes 1h = reserved 2h = controller pads to memory container size 3h = controller does not pa d and uses samples directly 13:0 output stream payload capability (outstrmpay) ? ro. this field indicates maximum number of words per frame for any single output stream . this measurement is in 16-bit word quantities per 48 khz frame. the maximum supported is 48 words (96b); therefore, a value of 30h is reported in this register. the value does not specify the number of words actually transmitted in the frame, but is the size of the data in the controller buffer (fifo) after the samples are padded as specified by opadtype. thus, to compute the supported streams, each sa mple is padded according to opadtype and then multiplied by the number of channels and samples per frame. if this computed value is larger than outstrmpay, then that stream is not supported. the value specified is not affected by striping. software must ensure that a format which would ca use more words per frame than indicated is not programmed into the output stream descriptor register. the value may be larger than the outpay register value in some cases. intel ? high definition audio controller registers (d27:f0) 676 intel ? ich8 family datasheet 17.2.12 instrmpay?input st ream payload capability (intel ? high definition audio controller?d27:f0) memory address:hdbar + 1ah attribute: ro default value: 0018h size: 16 bits bit description 15:14 input fifo padding type (ipadtype) ? ro. this field indicates how the controller pads the samples in the controller's buffer (f ifo). controllers may not pad at all or may pad to byte or memory container sizes. 0h = controller pads all samples to bytes 1h = reserved 2h = controller pads to memory container size 3h = controller does not pa d and uses sa mples directly 13:0 input stream payload capability (instrmpay) ? ro. this field indicates the maximum number of words per frame for any si ngle input stream. this measurement is in 16-bit word quantities per 48-khz frame. the maxi mum supported is 24 words (48b); therefore, a value of 18h is reported in this register. the value does not specify the number of words actually transmitted in the frame, but is the size of the data as it will be plac ed into the controller 's buffer (fifo). thus samples will be padded according to ipadty pe before being stored into controller buffer. to compute the suppo rted streams, each sample is padded according to ipadtype and then multiplied by the number of channels and samples per frame. if this computed value is larger than instrmpay th en that stream is not supported. as the inbound stream tag is not stored with the sa mples it is not included in the word count. the value may be larger than inpay register value in some cases, although values less than inpay may also be invalid due to over head. software must en sure that a format which would cause more words per frame th an indicated is not programmed into the input stream descriptor register. intel ? ich8 family datasheet 677 intel ? high definition audio controller registers (d27:f0) 17.2.13 intctl?interrupt control register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 20h attribute: r/w default value: 00000000h size: 32 bits bit description 31 global interrupt enable (gie) ? r/w. global bit to en able device interrupt generation. when set to 1, the intel ? high definition audio function is enabled to generate an interrupt. th is control is in addition to any bits in the bus specific address space, such as the interrupt enable bit in the pci configuration space. 0 = disable 1 = enable note: this bit is not affected by the d3 hot to d0 transition. 30 controller interrupt enable (cie) ? r/w. enables the general interrupt for controller functions. when set to 1, the controller generates an interrupt when the corresponding status bit gets set due to a response interrupt, a re sponse buffer overrun, and state change events. note: this bit is not affected by the d3 hot to d0 transition. 29:8 reserved 7:0 stream interrupt enable (sie) ? r/w. when set to 1, th e individual streams are enabled to generate an in terrupt when the correspondi ng status bits get set. a stream interrupt will be caused as a resu lt of a buffer with ioc = 1in the bdl entry being completed, or as a result of a fifo error (underrun or ove rrun) occurring. control over the generation of each of these source s is in the associated stream descriptor. the streams are numbered and the sie bits as signed sequentially, based on their order in the register set. bit 0: input stream 1 bit 1: input stream 2 bit 2: input stream 3 bit 3: input stream 4 bit 4: output stream 1 bit 5: output stream 2 bit 6: output stream 3 bit 7: output stream 4 intel ? high definition audio controller registers (d27:f0) 678 intel ? ich8 family datasheet 17.2.14 intsts?interrupt status register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 24h attribute: ro default value: 00000000h size: 32 bits bit description 31 global interrupt status (gis) ? ro. this bit is an or of all the interrupt status bits in this register. note: this bit is not affected by the d3 hot to d0 transition. 30 controller interrupt status (cis) ? ro. status of genera l controller interrupt. 1 = interrupt condition occurred due to a response interrupt, a response buffer overrun interrupt, or a sdin state ch ange event. the exact cause can be determined by interrogating other registers. this bit is an or of all of the stated interrupt status bits for this register. notes: 1. this bit is set regardless of the state of the corresponding interrupt enable bit, but a hardware interrupt will not be ge nerated unless the corresponding enable bit is set. 2. this bit is not affected by the d3 hot to d0 transition. 29:8 reserved 7:0 stream interrup t status (sis) ? ro. 1 = interrupt condition occurred on the corresponding stream. th is bit is an or of all of the stream?s interrupt status bits. note: these bits are set regardless of the stat e of the corresponding interrupt enable bits. the streams are numbered and the sie bits a ssigned sequentially, based on their order in the register set. bit 0: input stream 1 bit 1: input stream 2 bit 2: input stream 3 bit 3: input stream 4 bit 4: output stream 1 bit 5: output stream 2 bit 6: output stream 3 bit 7: output stream 4 intel ? ich8 family datasheet 679 intel ? high definition audio controller registers (d27:f0) 17.2.15 walclk?wall cloc k counter register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 30h attribute: ro default value: 00000000h size: 32 bits 17.2.16 ssync?stream synchronization register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 34h attribute: r/w default value: 00000000h size: 32 bits bit description 31:0 wall clock counter ? ro. this field provid es results from a 32 bit counter that is incremented on each link bclk period an d rolls over from ffff ffffh to 0000 0000h. this counter will roll over to 0 with a period of approximately 179 seconds. this counter is enabled while the bclk bit is set to 1. software uses this counter to synchronize between multiple controllers. will be reset on controller reset. bit description 31:8 reserved 7:0 stream synchronization (ssync) ? r/w. when set to 1, these bits block data from being sent on or received from the link. each bit controls the associated stream descriptor (i.e., bit 0 corresponds to th e first stream de scriptor, etc.) to synchronously start a set of dma engines, these bits are first set to 1. the run bits for the associated stream descriptors are then set to 1 to start the dma engines. when all streams are ready (fifordy =1), the associated ssync bits can all be set to 0 at the same time, and transmission or receptio n of bits to or from the link will begin together at the start of the next full link frame. to synchronously stop the streams, fist these bits are set, and then the individual run bits in the stream descripto r are cleared by software. if synchronization is not desired, these bits ma y be left as 0, and th e stream will simply begin running normally when the stream?s run bit is set. the streams are numbered and the sie bits as signed sequentially, based on their order in the register set. bit 0: input stream 1 bit 1: input stream 2 bit 2: input stream 3 bit 3: input stream 4 bit 4: output stream 1 intel ? high definition audio controller registers (d27:f0) 680 intel ? ich8 family datasheet 17.2.17 corblbase?corb lowe r base address register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 40h attribute: r/w, ro default value: 00000000h size: 32 bits 17.2.18 corbubase?corb uppe r base address register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 44h attribute: r/w default value: 00000000h size: 32 bits 17.2.19 corbwp?corb write pointer register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 48h attribute: r/w default value: 0000h size: 16 bits bit description 31:7 corb lower base address ? r/w. this field provides the lower address of the command output ring buffer, allowing the co rb base address to be assigned on any 128-b boundary. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. 6:0 corb lower base unimplemented bits ? ro. hardwired to 0. this required the corb to be allocated with 128b granularity to allow for cache line fetch optimizations. bit description 31:0 corb upper base address ? r/w. this field provides the upper 32 bits of the address of the command output ring buffer. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. bit description 15:8 reserved. 7:0 corb write pointer ? r/w. software writes the last valid corb entry offset into this field in dword granularity. the dma engine fetches commands from the corb until the read pointer matches the write pointer; su pports 256 corb entries (256x4b = 1 kb). this register field may be writte n when the dma engine is running. intel ? ich8 family datasheet 681 intel ? high definition audio controller registers (d27:f0) 17.2.20 corbrp?corb read pointer register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 4ah attribute: r/w default value: 0000h size: 16 bits 17.2.21 corbctl?corb control register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 4ch attribute: r/w default value: 00h size: 8 bits bit description 15 corb read pointer reset ? r/w. software writes a 1 to this bit to reset the corb read pointer to 0 and clear any residual pr efetched commands in the corb hardware buffer within the high definition audio contro ller. the hardware will physically update this bit to 1 when the corb pointer reset is complete. software must read a 1 to verify that the reset completed correctly. software mu st clear this bit back to 0 and read back the 0 to verify that the clear completed correctly. the corb dma engine must be stopped prior to resetting the read pointe r or else dma transfer may be corrupted. 14:8 reserved. 7:0 corb read pointer (corbrp)? ro. software reads this field to determine how many commands it can write to the corb without over-running. the value read indicates the corb read pointer offset in dword granularit y. the offset entry read from this field has been successfully fetched by the dma contro ller and may be over-w ritten by software; supports 256 corb entries (256 x 4b=1kb). this field may be read while the dma engine is running. bit description 7:2 reserved. 1 enable corb dma engine ? r/w. after software writes a 0 to this bit, the hardware may not stop immediately. the hardware will physically update the bit to 0 when the dma engine is truly stopped. software must read a 0 from th is bit to verify that the dma engine is truly stopped. 0 = dma stop 1 = dma run 0 corb memory error interrupt enable ? r/w. 0 = disable 1 = enable. the controller will generate an interrupt if the cmei status bit (hdbar + 4dh: bit 0) is set. intel ? high definition audio controller registers (d27:f0) 682 intel ? ich8 family datasheet 17.2.22 corbst?corb status register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 4dh attribute: r/wc default value: 00h size: 8 bits 17.2.23 corbsize?cor b size register intel ? high definition audio controller?d27:f0) memory address:hdbar + 4eh attribute: ro default value: 42h size: 8 bits 17.2.24 rirblbase?rirb lower base address register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 50h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 7:1 reserved. 0 corb memory error indication (cmei) ? r/wc. software can clear this bit by writing a 1 to it. however, this type of erro r leaves the audio subsystem in an un-viable state and typically required a co ntroller reset by writing a 0 to the controller reset # bit (hdbar + 08h: bit 0). 0 = error not detected. 1 = controller has detected an error in the path way between the controller and memory. this may be an ecc bit error or any other type of de tectable data error which renders the command data fetched invalid. bit description 7:4 corb size capability ? ro. hardwired to 0100b indicating that the ich8 only supports a corb size of 256 corb entries (1024b). 3:2 reserved. 1:0 corb size ? ro. hardwired to 10b which sets the corb size to 256 entries (1024b). bit description 31:7 corb lower base address ? r/w. this field provides the lower address of the response input ring buffer, allowing the ri rb base address to be assigned on any 128-b boundary. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. 6:0 rirb lower base unimplemented bits ? ro. ha rdwired to 0. this required the rirb to be allocated with 128-b granularity to allow for cache line fetch optimizations. intel ? ich8 family datasheet 683 intel ? high definition audio controller registers (d27:f0) 17.2.25 rirbubase?rirb upper base address register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 54h attribute: r/w default value: 00000000h size: 32 bits 17.2.26 rirbwp?rirb writ e pointer register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 58h attribute: r/w, ro default value: 0000h size: 16 bits bit description 31:0 rirb upper base address ? r/w. this field provides the upper 32 bits of the address of the response input ring buffer. th is register field must not be written when the dma engine is running or th e dma transfer may be corrupted. bit description 15 rirb write pointer reset ? r/w. software writes a 1 to this bit to reset the rirb write pointer to 0. the rirb dma engine mu st be stopped prior to resetting the write pointer or else dma transfer may be corrupted. note: this bit is always read as 0. 14:8 reserved. 7:0 rirb write pointer (rirbwp) ? ro. this field indicates the last valid rirb entry written by the dma controller. software reads this field to determine how many responses it can read from the rirb. the value read indi cates the rirb write pointer offset in 2 dword rirb entry units (since each rirb entry is 2 dwords lo ng); supports up to 256 rirb entries (256 x 8 b = 2 kb). this re gister field may be written when the dma engine is running. intel ? high definition audio controller registers (d27:f0) 684 intel ? ich8 family datasheet 17.2.27 rintcnt?response in terrupt count register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 5ah attribute: r/w default value: 0000h size: 16 bits 17.2.28 rirbctl?rirb control register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 5ch attribute: r/w default value: 00h size: 8 bits bit description 15:8 reserved. 31:0 n response interrupt count ? r/w. 0000 0001b = 1 response sent to rirb ........... 1111 1111b = 255 responses sent to rirb 0000 0000b = 256 responses sent to rirb the dma engine should be stopped when chan ging this field; othe rwise, an interrupt may be lost. note that each response occupies 2 dwords in the rirb. this is compared to the total number of resp onses that have been returned, as opposed to the number of frames in which there we re responses. if more than one codecs responds in one frame, th en the count is increased by the number of responses received in the frame. bit description 7:3 reserved. 2 response overrun interrupt control ? r/w. if this bit is set, the hardware will generate an interrupt when the response overrun interrupt status bit (hdbar + 5dh: bit 2) is set. 1 enable rirb dma engine ? r/w. after software writes a 0 to this bit, the hardware may not stop immediately. the hardware will physically update the bit to 0 when the dma engine is truly stopped. software must read a 0 from this bit to verify that the dma engine is truly stopped. 0 = dma stop 1 = dma run 0 response interrupt control ? r/w. 0 = disable interrupt 1 = generate an interrupt after n number of responses are sent to the rirb buffer or when an empty response slot is encountered on all sdi[x] inputs (whichever occurs first). the n counter is rese t when the interrupt is generated. intel ? ich8 family datasheet 685 intel ? high definition audio controller registers (d27:f0) 17.2.29 rirbsts?rirb status register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 5dh attribute: r/wc default value: 00h size: 8 bits 17.2.30 rirbsize?rir b size register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 5eh attribute: ro default value: 42h size: 8 bits 17.2.31 ic?immediate command register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 60h attribute: r/w default value: 00000000h size: 32 bits bit description 7:3 reserved. 2 response overrun interrupt status ? r/wc. software sets this bit to 1 when the rirb dma engine is not able to write th e incoming responses to memory before additional incoming responses overrun the in ternal fifo. when th e overrun occurs, the hardware will drop the responses which overrun the buffer. an interrupt may be generated if the response overrun interrupt control bit is set. note that this status bit is set even if an interrupt is not enabled for this event. software clears this bi t by writing a 1 to it. 1 reserved. 0 response interrupt ? r/wc. hardware sets this bit to 1 when an interrupt has been generated after n number of responses are sent to the rirb buffer or when an empty response slot is encountered on all sdi[x] inputs (whichever occu rs first). note that this status bit is set even if an in terrupt is not enabled for this event. software clears this bi t by writing a 1 to it. bit description 7:4 rirb size capability ? ro. hardwired to 0100 b indicating that th e ich8 only supports a rirb size of 256 rirb entries (2048b). 3:2 reserved. 1:0 rirb size ? ro. hardwired to 10b which sets the corb size to 256 entries (2048b). bit description 31:0 immediate command write ? r/w . the command to be sent to the codec via the immediate command mechanism is written to this register. the command stored in this register is sent out ov er the link during the next availa ble frame after a 1 is written to the icb bit (hdbar + 68h: bit 0). intel ? high definition audio controller registers (d27:f0) 686 intel ? ich8 family datasheet 17.2.32 ir?immediate response register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 64h attribute: ro default value: 00000000h size: 32 bits 17.2.33 irs?immediate comm and status register (intel ? high definition audio controller?d27:f0) memory address:hdbar + 68h attribute: r/w, r/wc default value: 0000h size: 16 bits bit description 31:0 immediate response read (irr) ? ro. this register contains th e response received from a codec resulting from a command se nt via the immediate command mechanism. if multiple codecs responded in the same time, there is no assurance as to which response will be latched. therefore, broa dcast-type commands must not be issued via the immediate command mechanism. bit description 15:2 reserved. 1 immediate result valid (irv) ? r/wc. this bit is set to 1 by hardware when a new response is latched into the immediate resp onse register (hdbar + 64). this is a status flag indicating that software may read the response from the immediate response register. software must clear this bit by writing a 1 to it before issuing a new command so that the software may determine when a new response has arrived. 0 immediate command busy (icb) ? r/w. when this bit is read as 0, it indicates that a new command may be issued using the immediate command mechanism. when this bit transitions from 0-to-1 (via software writing a 1), the controller issues the command currently stored in the imme diate command register to th e codec over the link. when the corresponding response is latched in to the immediate response register, the controller hardware sets the irv flag and clears the icb bit back to 0. note: an immediate command must not be issued while the corb/rirb mechanism is operating; otherwise, the responses conflict. this must be enforced by software. intel ? ich8 family datasheet 687 intel ? high definition audio controller registers (d27:f0) 17.2.34 dplbase?dma position lo wer base address register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 70h attribute: r/w, ro default value: 00000000h size: 32 bits 17.2.35 dpubase?dma position up per base address register (intel ? high definition au dio controller?d27:f0) memory address:hdbar + 74h attribute: r/w default value: 00000000h size: 32 bits bit description 31:7 dma position lower base address ? r/w. this field provides the lower 32 bits of the dma position buffer base a ddress. this register field mu st not be written when any dma engine is running or the dma transfer may be corrupted. this same address is used by the flush control and must be prog rammed with a valid value before the flush control bit (hdbar+08h:bit 1) is set. 6:1 dma position lower base un implemented bits ? ro. hardwired to 0 to force the 128-byte buffer alignment for cache line write optimizations. 0 dma position buffer enable ? r/w. 0 = disable. 1 = enable. controller will write the dma po sitions of each of the dma engines to the buffer in the main memory periodically (typically, once per frame). software can use this value to know what da ta in memory is valid data. bit description 31:0 dma position upper base address ? r/w. this field provid es the upper 32 bits of the dma position buffer base a ddress. this register field mu st not be written when any dma engine is running or the dma transfer may be corrupted. intel ? high definition audio controller registers (d27:f0) 688 intel ? ich8 family datasheet 17.2.36 sdctl?stream descri ptor control register (intel ? high definition audio controller?d27:f0) memory address:input stream[0 ]: hdbar + 80hattribute: r/w, ro input stream[1]: hdbar + a0h input stream[2]: hdbar + c0h input stream[3]: hdbar + e0h output stream[0]: hdbar + 100h output stream[1]: hdbar + 120h output stream[2]: hdbar + 140h output stream[3]: hdbar + 160h default value: 040000h size: 24 bits bit description 23:20 stream number ? r/w. this value reflects the ta g associated with the data being transferred on the link. when data controlled by this descriptor is sent out over the link, it will have its stream number encoded on the sync signal. when an input stream is detected on any of the sdi signals that match this value, the data samples are loaded into fifo associated with this descriptor. note: while a single sdi input may contain da ta from more than one stream number, two different sdi inputs may not be conf igured with the same stream number. 0000 = reserved 0001 = stream 1 ........ 1110 = stream 14 1111 = stream 15 19 bidirectional direction control ? ro. this bit is only meaningful for bidirectional streams; therefore, this bit is hardwired to 0. 18 traffic priority ? ro. hardwired to 1 indicati ng that all streams wi ll use vc1 if it is enabled through the pc i express* registers. 17:16 stripe control ? ro. this bit is only meaningful for input streams; therefore, this bit is hardwired to 0. 15:5 reserved 4 descriptor error interrupt enable ? r/w. 0 = disable 1 = enable. an interrupt is generated when the descriptor error status bit is set. 3 fifo error interrupt enable ? r/w. this bit controls whether the occurrence of a fifo error (overrun for input or underrun for ou tput) will cause an interrupt. if this bit is not set, bit 3in the status register will be set, but the interrupt will not occur. either way, the samples will be dropped. 2 interrupt on completion enable ? r/w. this bit controls wh ether or not an interrupt occurs when a buffer completes with the ioc bit set in its de scriptor. if this bit is not set, bit 2 in the status register will be set, but the interrupt will not occur. intel ? ich8 family datasheet 689 intel ? high definition audio controller registers (d27:f0) 1 stream run (run) ? r/w. 0 = disable. when cleared to 0, the dma engine associated with this input stream will be disabled. the hardware will report a 0 in this bit when the dma engine is actually stopped. software must read a 0 from this bi t before modifying related control registers or rest arting the dma engine. 1 = enable. when set to 1, the dma engine as sociated with this input stream will be enabled to transfer data from the fifo to the main memory. the ssync bit must also be cleared in order for the dma en gine to run. for ou tput streams, the cadence generator is reset whenever the run bit is set. 0 stream reset (srst) ? r/w. 0 = writing a 0 causes the corresponding st ream to exit reset. when the stream hardware is ready to begin operation, it wi ll report a 0 in this bit. software must read a 0 from this bit before acce ssing any of the stream registers. 1 = writing a 1 causes the corresponding stre am to be reset. the stream descriptor registers (except the srst bit itself) and fifo?s for the corresponding stream are reset. after the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. software must read a 1 from this bit to verify that the stream is in reset. the run bit must be cleare d before srst is asserted. bit description intel ? high definition audio controller registers (d27:f0) 690 intel ? ich8 family datasheet 17.2.37 sdsts?stream descri ptor status register (intel ? high definition audio controller?d27:f0) memory address:input stream[0]: hdbar + 83h attribute:r/wc, ro input stream[1]: hdbar + a3h input stream[2]: hdbar + c3h input stream[3]: hdbar + e3h output stream[0]: hdbar + 103h output stream[1]: hdbar + 123h output stream[2]: hdbar + 143h output stream[3]: hdbar + 163h default value: 00h size: 8 bits bit description 7:6 reserved. 5 fifo ready (fifordy) ? ro. for output stream s, the controller hardware will set this bit to 1 while the output dma fifo contains enough data to maintain the stream on the link. this bit defaults to 0 on reset because the fifo is cleared on a reset. for input streams, the co ntroller hardware will set this bit to 1 when a valid descriptor is loaded and the engine is ready for the run bit to be set. 4 descriptor error ? r/wc. 0 = no error 1 = serious error occurred during the fetch of a descriptor. this could be a result of a master abort, a parity or ecc error on th e bus, or any other er ror that renders the current buffer descriptor or buffer descriptor list useles s. this error is treated as a fatal stream error, as the stream cannot continue runn ing. the run bit will be cleared and the stre am will stopped. software may attempt to rest art the stream engine after addressing the cause of the error and writing a 1 to this bit to clear it. 3 fifo error ? r/wc. the bit is cleare d by writing a 1 to it. 0 = no error 1 = fifo error occurred. this bit is set even if an interrupt is not enabled. for an input stream, this indicates a fifo overrun occurring while the run bit is set. when this happens, the fifo pointers do no t increment and the incoming data is not written into the fifo, thereby being lost. for an output stream, this indicates a fifo underrun when there are still buffers to send. the hardware should not transmit anythi ng on the link for the associated stream if there is not valid data to send. 2 buffer completion interrupt status ? r/wc. 0 = last sample of buffer not processed. 1 = set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion bit is set in the command byte of the buffer descriptor. it remains active unt il software clears it by writing a 1 to it. 1:0 reserved. intel ? ich8 family datasheet 691 intel ? high definition audio controller registers (d27:f0) 17.2.38 sdlpib?stream descriptor link position in buffer register (intel ? high definition audio controller?d27:f0) memory address:input stream[0]: hdbar + 84h attribute: ro input stream[1]: hdbar + a4h input stream[2]: hdbar + c4h input stream[3]: hdbar + e4h output stream[0]: hdbar + 104h output stream[1]: hdbar + 124h output stream[2]: hdbar + 144h output stream[3]: hdbar + 164h default value: 00000000h size: 32 bits 17.2.39 sdcbl?stream de scriptor cyclic buffer length register (intel ? high definition au dio controller?d27:f0) memory address:input stream[0]: hdbar + 88h attribute: r/w input stream[1]: hdbar + a8h input stream[2]: hdbar + c8h input stream[3]: hdbar + e8h output stream[0]: hdbar + 108h output stream[1]: hdbar + 128h output stream[2]: hdbar + 148h output stream[3]: hdbar + 168h default value: 00000000h size: 32 bits bit description 31:0 link position in buffer ? ro. this field in dicates the number of bytes that have been received off the link. this register will co unt from 0 to the value in the cyclic buffer length register and then wrap to 0. bit description 31:0 cyclic buffer length ? r/w. this field indicates the number of bytes in the complete cyclic buffer. this register re presents an integer number of samples. link position in buffer will be reset when it reaches this value. software may only write to this register after global reset, controller reset, or stream reset has occurred. this value should be only modified when the run bit is 0. once the run bit has been set to enable the engine, software must not write to this register until after the next reset is asserted , or transfer may be corrupted. intel ? high definition audio controller registers (d27:f0) 692 intel ? ich8 family datasheet 17.2.40 sdlvi?stream descriptor last valid index register (intel ? high definition audio controller?d27:f0) memory address:input stream [0]: hdbar + 8ch attribute: r/w input stream[1]: hdbar + ach input stream[2]: hdbar + cch input stream[3]: hdbar + ech output stream[0]: hdbar + 10ch output stream[1]: hdbar + 12ch output stream[2]: hdbar + 14ch output stream[3]: hdbar + 16ch default value: 0000h size: 16 bits 17.2.41 sdfifow?stream descript or fifo watermark register (intel ? high definition audio controller?d27:f0) memory address:input stream [0]: hdbar + 8eh attribute: r/w input stream[1]: hdbar + aeh input stream[2]: hdbar + ceh input stream[3]: hdbar + eeh output stream[0]: hdbar + 10eh output stream[1]: hdbar + 12eh output stream[2]: hdbar + 14eh output stream[3]: hdbar + 16eh default value: 0004h size: 16 bits bit description 15:8 reserved. 7:0 last valid index ? r/w. the value written to this re gister indicates the index for the last valid buffer descript or in bdl. after the controller has processed this descriptor, it will wrap back to the first descriptor in the list and continue processing. this field must be at least 1 (i.e., there must be at least 2 valid entries in the buffer descriptor list before dm a operations can begin). this value should only modi fied when the run bit is 0. bit description 15:3 reserved. 2:0 fifo watermark (fifow) ? r/w. this field indicates the minimum number of bytes accumulated/free in the fifo be fore the controller will star t a fetch/eviction of data. 010 = 8b 011 = 16b 100 = 32b (default) others = unsupported notes: 1. when the bit field is programmed to an unsupported size, the hardware sets itself to the default value. 2. software must read the bit field to test if the value is supported after setting the bit field. intel ? ich8 family datasheet 693 intel ? high definition audio controller registers (d27:f0) 17.2.42 sdfifos?stream descri ptor fifo size register (intel ? high definition au dio controller?d27:f0) memory address:input stream[0]: hdbar + 90h attribute: input: ro input stream[1]: hdbar + b0h output: r/w input stream[2]: hdbar + d0h input stream[3]: hdbar + f0h output stream[0]: hdbar + 110h output stream[1]: hdbar + 130h output stream[2]: hdbar + 150h output stream[3]: hdbar + 170h default value: input stream: 0077h size: 16 bits output stream: 00bfh bit description 15:8 reserved. 7:0 fifo size ? ro (input stream), r/w (output stream). this field indicates the maximum number of bytes that co uld be fetched by the contro ller at one time. this is the maximum number of bytes that may have been dma?d into memory but not yet transmitted on the link, and is also the maximum possible value that the picb count will increase by at one time. the value in this field is diffe rent for input and output stream s. it is also dependent on the bits per samples setting for the corresponding stream. following are the values read/written from/to this register for in put and output streams, and for non-padded and padded bit formats: output stream r/w value notes: 1. all other values not listed are not supported. 2. when the output stream is programmed to an unsupported size, the hardware sets itself to the default value (bfh). 3. software must read the bit field to test if the value is supported after setting the bit field. input stream ro value note: the default value is different for input and output streams, and reflects the default state of the bits fi elds (in stream descriptor format registers) for the corresponding stream. value output streams 0fh = 16b 8, 16, 20, 24, or 32 bit output streams 1fh = 32b 8, 16, 20, 24, or 32 bit output streams 3fh = 64b 8, 16, 20, 24, or 32 bit output streams 7fh = 128b 8, 16, 20, 24, or 32 bit output streams bfh = 192b 8, 16, or 32 bit output streams ffh = 256b 20, 24 bit output streams value input streams 77h = 120b 8, 16, 32 bit input streams 9fh = 160b 20, 24 bit input streams intel ? high definition audio controller registers (d27:f0) 694 intel ? ich8 family datasheet 17.2.43 sdfmt?stream descri ptor format register (intel ? high definition audio controller?d27:f0) memory address:input stream[0]: hdbar + 92h attribute: r/w input stream[1]: hdbar + b2h input stream[2]: hdbar + d2h input stream[3]: hdbar + f2h output stream[0]: hdbar + 112h output stream[1]: hdbar + 132h output stream[2]: hdbar + 152h output stream[3]: hdbar + 172h default value: 0000h size: 16 bits bit description 15 reserved. 14 sample base rate ? r/w 0 = 48 khz 1 = 44.1 khz 13:11 sample base rate multiple ? r/w 000 = 48 khz, 44.1 khz or less 001 = x2 (96 khz, 88.2 khz, 32 khz) 010 = x3 (144 khz) 011 = x4 (192 khz, 176.4 khz) others = reserved. 10:8 sample base rate devisor ? r/w. 000 = divide by 1(48 khz, 44.1 khz) 001 = divide by 2 (24 khz, 22.05 khz) 010 = divide by 3 (16 khz, 32 khz) 011 = divide by 4 (11.025 khz) 100 = divide by 5 (9.6 khz) 101 = divide by 6 (8 khz) 110 = divide by 7 111 = divide by 8 (6 khz) 7 reserved. 6:4 bits per sample (bits) ? r/w. 000 = 8 bits. the data will be packed in memory in 8-bit containers on 16-bit boundaries 001 = 16 bits. the data will be packed in memory in 16-bit containers on 16-bit boundaries 010 = 20 bits. the data will be packed in memory in 32-bit containers on 32-bit boundaries 011 = 24 bits. the data will be packed in memory in 32-bit containers on 32-bit boundaries 100 = 32 bits. the data will be packed in memory in 32-bit containers on 32-bit boundaries others = reserved. 3:0 number of channels (chan) ? r/w. indicates number of channels in each frame of the stream. 0000 =1 0001 =2 ........ 1111 =16 intel ? ich8 family datasheet 695 intel ? high definition audio controller registers (d27:f0) 17.2.44 sdbdpl?stream descriptor b uffer descriptor list pointer lower base address register (intel ? high definition au dio controller?d27:f0) memory address:input stream[0]: hdbar + 98h attribute: r/w,ro input stream[1]: hdbar + b8h input stream[2]: hdbar + d8h input stream[3]: hdbar + f8h output stream[0]: hdbar + 118h output stream[1]: hdbar + 138h output stream[2]: hdbar + 158h output stream[3]: hdbar + 178h default value: 00000000h size: 32 bits 17.2.45 sdbdpu?stream descriptor b uffer descriptor list pointer upper base address register (intel ? high definition audio controller?d27:f0) memory address:input stream[0]: hdbar + 9ch attribute: r/w input stream[1]: hdbar + bch input stream[2]: hdbar + dch input stream[3]: hdbar + fch output stream[0]: hdbar + 11ch output stream[1]: hdbar + 13ch output stream[2]: hdbar + 15ch output stream[3]: hdbar + 17ch default value: 00000000h size: 32 bits bit description 31:7 buffer descriptor list po inter lower base address ? r/w. this field provides the lower address of the buffer desc riptor list. this value should only be modified when the run bit is 0, or dma transfer may be corrupted. 6:0 hardwired to 0 forcing al ignment on 128-b boundaries. bit description 31:0 buffer descriptor list po inter upper base address ? r/w. this field provides the upper 32-bit address of the buffer descriptor list. this value should only be modified when the run bit is 0, or dma transfer may be corrupted. intel ? high definition audio controller registers (d27:f0) 696 intel ? ich8 family datasheet intel ? ich8 family datasheet 697 pci express* configuration registers 18 pci express* configuration registers 18.1 pci express* configuration registers (pci express?d28:f0/f1/f2/f3/f4/f5) note: register address locations that are not shown in table 141 and should be treated as reserved. / table 141. pci express* configuration registers address map (pci express?d28:f0/f1/f2/f3/f4/f5) (sheet 1 of 3) offset mnemonic register name function 0?5 default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 04h ro 0bh bcc base class code 06h ro 0ch cls cache line size 00h r/w 0dh plt primary latency timer 00h ro 0eh headtyp header type 81h ro 18h?1ah bnum bus number 000000h r/w 1bh slt secondary latency timer 0h ro 1ch?1dh iobl i/o base and limit 0000h r/w, ro 1eh?1fh ssts secondary status 0000h r/wc 20h?23h mbl memory base and limit 00000000h r/w 24h?27h pmbl prefetchable memory base and limit 00010001h r/w, ro 28h?2bh pmbu32 prefetchable memory base upper 32 bits 00000000h r/w 2ch?2fh pmlu32 prefetchable memory limit upper 32 bits 00000000h r/w 34h capp capabilities list pointer 40h ro 3ch?3dh intr interru pt information see bit description r/w, ro 3eh?3fh bctrl bridge control register 0000h r/w 40h?41h clist capabilities list 8010 ro pci express* configuration registers 698 intel ? ich8 family datasheet 42h?43h xcap pci express* capabilities 0041 r/wo, ro 44h?47h dcap device capabilities 00000fe0h ro 48h?49h dctl device control 0000h r/w, ro 4ah?4bh dsts device status 0010h r/wc, ro 4ch?4fh lcap link capabilities see bit description r/w, ro, r/wo 50h?51h lctl link control 0000h r/w, wo, ro 52h?53h lsts link status see bit description ro 54h?57h slcap slot capabilities register 00000060h r/wo, ro 58h?59h slctl slot control 0000h r/w, ro 5ah?5bh slsts slot status 0000h r/wc, ro 5ch?5dh rctl root control 0000h r/w 60h?63h rsts root status 00000000h r/wc, ro 80h?81h mid message signal ed interrupt identifiers 9005h ro 82h?83h mc message signal ed interrupt message control 0000h r/w, ro 84h?87h ma message signal ed interrupt message address 00000000h r/w 88h?89h md message signal ed interrupt message data 0000h r/w 90h?91h svcap subsystem vendor capability a00dh ro 94h?97h svid subsystem vendor identification 00000000h r/wo a0h?a1h pmcap power management capability 0001h ro a2h?a3h pmc pci power mana gement capability c802h ro a4?a7h pmcs pci power management control and status 00000000h r/w, ro d8?dbh mpc miscellaneous port configuration 00110000h r/w dc?dfh smscs smi/sci status register 00000000h r/wc e1h rpdcgen root port dynamic clock gating enable (mobile only) 00h r/w e2?e3h ipws intel ? pro/wireless 3945abg status 0000h ro 100?103h vch virtual channel capability header 18010002h ro 104h?107h ? reserved ? ? 108h?10bh vcap2 virtual channe l capability 2 00000001h ro 10ch?10dh pvc port virtual channel control 0000h r/w 10eh?10fh pvs port virtua l channel status 0000h ro table 141. pci express* config uration registers address map (pci express?d28:f0/f1/f2/f3/f4/f5) (sheet 2 of 3) offset mnemonic register name function 0?5 default type intel ? ich8 family datasheet 699 pci express* configuration registers 110h?113h v0cap virtual channel 0 resource capability 00000001h ro 114?117h v0ctl virtual channel 0 resource control 800000ffh r/w, ro 11a?11bh v0sts virtual channel 0 resource status 0000h ro 11ch?143h ? reserved ? ? 144h?147h ues uncorrectable error status see bit description r/wc, ro 148h?14bh uem uncorrectable error mask 00000000h r/wo, ro 14ch?14fh uev uncorrectable error severity 00060011h ro 150h?153h ces correctable error status 00000000h r/wc 154h?157h cem correctable error mask 00000000h r/wo 158h?15bh aecc advanced error ca pabilities and control 00000000h ro 170h?173h res root error status 00000000h r/wc, ro 180h?183h rctcl root complex topology capability list 00010005h ro 184h?187h esd element self description see bit description ro 190h?193h uld upstream link description 00000001h ro 198h?19fh ulba upstream link base address see bit description ro 318h peetm pci express extended test mode register 00h ro table 141. pci express* configuration registers address map (pci express?d28:f0/f1/f2/f3/f4/f5) (sheet 3 of 3) offset mnemonic register name function 0?5 default type pci express* configuration registers 700 intel ? ich8 family datasheet 18.1.1 vid?vendor identi fication register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 18.1.2 did?device identi fication register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 02h?03h attribute: ro default value: port 1= bit description size: 16 bits port 2= bit description port 3= bit description port 4= bit description port 5= bit description port 6= bit description bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id ? ro. this is a 16-b it value assigned to the intel ? ich8 pci express controller. refer to the intel ? ich8 family specification update for the value of the revision id register. intel ? ich8 family datasheet 701 pci express* configuration registers 18.1.3 pcicmd?pci command register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 04h?05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. this bit disables pin- based intx# interrupts on enabled hot- plug and power management events. this bit has no e ffect on msi operation. 0 = internal intx# messages are generated if there is an interrupt for hot-plug or power management and msi is not enabled. 1 = internal intx# messages will not be generated. this bit does not affect inte rrupt forwarding from devices connected to the root port. assert_intx and deassert_intx messages wi ll still be forwarded to the internal interrupt controllers if this bit is set. 9 fast back to back enable (fbe) ? reserved per the pci express* base specification . 8 serr# enable (see) ? r/w. 0 = disable. 1 = enables the root port to generate an serr# message when psts.sse is set. 7 wait cycle control (wcc) ? reserved per the pci express base specification . 6 parity error response (per) ? r/w. 0 = disable. 1 = device is capable of reporting parity errors as a master on the backbone. 5 vga palette snoop (vps) ? reserved per the pci express* base specification . 4 postable memory write enable (pmwe) ? reserved per the pci express* base specification . 3 special cycle enable (sce) ? reserved per the pci express* base specification . 2 bus master enable (bme) ? r/w. 0 = disable. all cycles from the device are master aborted 1 = enable. allows the root port to forw ard cycles onto the backbone from a pci express* device. 1 memory space enable (mse) ? r/w. 0 = disable. memory cycles within the rang e specified by the memory base and limit registers are master aborted on the backbone. 1 = enable. allows memory cycles within th e range specified by the memory base and limit registers can be forwarde d to the pci express device. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disable. i/o cycles within the range spec ified by the i/o base and limit registers are master aborted on the backbone. 1 = enable. allows i/o cycles within the range specified by the i/o base and limit registers can be forwarded to the pci express device. pci express* configuration registers 702 intel ? ich8 family datasheet 18.1.4 pcists?pci status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = set when the root port receives a command or data from the backbone with a parity error. this is set even if pcimd. per (d28:f0/f1/f2/f3:04, bit 6) is not set. 14 signaled system error (sse) ? r/wc. 0 = no system error signaled. 1 = set when the root port signals a sy stem error to the internal serr# logic. 13 received master abort (rma) ? r/wc. 0 = root port has not received a completion with unsupported re quest status from the backbone. 1 = set when the root port receives a completion with unsupported request status from the backbone. 12 received target abort (rta) ? r/wc. 0 = root port has not received a completion with completer abort from the backbone. 1 = set when the root port receives a completion with completer abort from the backbone. 11 signaled target abort (sta) ? r/wc. 0 = no target abort received. 1 = set whenever the root port forwards a target abort received from the downstream device onto the backbone. 10:9 devsel# timing status (dev_sts) ? reserved per the pci express* base specification . 8 master data parity error detected (dped) ? r/wc. 0 = no data parity error received. 1 = set when the root port receives a comp letion with a data parity error on the backbone and pcimd.per (d28:f0/f 1/f2/f3:04, bit 6) is set. 7 fast back to back capable (fb2bc) ? reserved per the pci express* base specification . 6 reserved 5 66 mhz capable ? reserved per the pci express* base specification . 4 capabilities list ? ro. hardwired to 1. indi cates the presence of a capabilities list. 3 interrupt status ? ro. indicates status of hot-plug and power management interrupts on the root port that re sult in intx# message generation. 0 = interrupt is deasserted. 1 = interrupt is asserted. this bit is not set if msi is enabled. if msi is not enabled, this bit is set regardless of the state of pcicmd.interrupt disable bit (d28:f0/f1/f2/f3/f4/f5:04h:bit 10). 2:0 reserved intel ? ich8 family datasheet 703 pci express* configuration registers 18.1.5 rid?revision identification register (pci express?d28:f0/f1/f2/f3/f4/f5) offset address: 08h attribute: ro default value: see bit description size: 8 bits 18.1.6 pi?programming interface register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 09h attribute: ro default value: 00h size: 8 bits 18.1.7 scc?sub class code register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 0ah attribute: ro default value: 04h size: 8 bits 18.1.8 bcc?base clas s code register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 0bh attribute: ro default value: 06h size: 8 bits bit description 7:0 revision id ? ro. refer to the intel ? ich8 family specification update for the value of the revision id register. bit description 7:0 programming interface ? ro. 00h = no specific register level programming interface defined. bit description 7:0 sub class code (scc) ? ro. this field is determined by bit 2 of the mpc register (d28:f0-5, offset d8h, bit 2). 04h = pci-to-pci bridge. 00h = host bridge. bit description 7:0 base class code (bcc) ? ro. 06h = bridge device. pci express* configuration registers 704 intel ? ich8 family datasheet 18.1.9 cls?cache line size register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 0ch attribute: r/w default value: 00h size: 8 bits 18.1.10 plt?primary late ncy timer register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 0dh attribute: ro default value: 00h size: 8 bits 18.1.11 headtyp?header type register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 0eh attribute: ro default value: 81h size: 8 bits 18.1.12 bnum?bus nu mber register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 18?1ah attribute: r/w default value: 000000h size: 24 bits bit description 7:0 cache line size (cls) ? r/w. this is read/write but contai ns no functionality, per the pci express* base specification . bit description 7:3 latency count. reserved per the pci express* base specification. 2:0 reserved bit description 7 multi-function device ? ro. 0 = single-func tion device. 1 = multi-function device. 6:0 configuration layout? ro. this field is de termined by bit 2 of the mpc register (d28:f0-5, offset d8h, bit 2). 00h = host bridge. 01h = pci-to-pci bridge. bit description 23:16 subordinate bus number (sbbn) ? r/w. indicates the highest pci bus number below the bridge. 15:8 secondary bus number (scbn) ? r/w. indicates the bus number the port. 7:0 primary bus number (pbn) ? r/w. indicates the bus number of the backbone. intel ? ich8 family datasheet 705 pci express* configuration registers 18.1.13 slt?secondar y latency timer (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 1bh attribute: ro default value: 0h size: 8 bits 18.1.14 iobl?i/o base and limit register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 1ch?1dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 7:0 secondary latency timer ? reserved for a root port per the pci express* base specification. bit description 15:12 i/o limit address (iola) ? r/w. this field provides i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bi ts 11:0 are assumed to be padded to fffh. 11:8 i/o limit address capability (iolc) ? ro. in dicates that the bri dge does not support 32-bit i/o addressing. 7:4 i/o base address (ioba) ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 ar e assumed to be padded to 000h. 3:0 i/o base address capability (iobc) ? r/o. indicates that the bridge does not support 32-bit i/o addressing. pci express* configuration registers 706 intel ? ich8 family datasheet 18.1.15 ssts?secondary status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 1eh?1fh attribute: r/wc default value: 0000h size: 16 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no error. 1 = the port received a poisoned tlp. 14 received system error (rse) ? r/wc. 0 = no error. 1 = the port received an err_fatal or err_nonfatal message from the device. 13 received master abort (rma) ? r/wc. 0 = unsupported request not received. 1 = the port received a completion with ?u nsupported request? status from the device. 12 received target abort (rta) ? r/wc. 0 = completion abort not received. 1 = the port received a completion with ?completion abort? status from the device. 11 signaled target abort (sta) ? r/wc. 0 = completion abort not sent. 1 = the port generated a completion with ?completion abort? status to the device. 10:9 secondary devsel# timing status (sdts): reserved per pci express* base specification . 8 data parity error detected (dpd) ? r/wc. 0 = conditions belo w did not occur . 1 = set when the bctrl.pere (d28:fo/f1/f2/f3/f4/f5:3e: bit 0) is set, and either of the following two conditions occurs: ? port receives completi on marked poisoned. ? port poisons a write request to the secondary side. 7 secondary fast back to back capable (sfbc): reserved per pci express* base specification . 6 reserved 5 secondary 66 mhz capable (sc66): reserved per pci express* base specification . 4:0 reserved intel ? ich8 family datasheet 707 pci express* configuration registers 18.1.16 mbl?memory base and limit register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 20h?23h attribute: r/w default value: 00000000h size: 32 bits accesses that are within the ranges specified in this register will be sent to the attached device if cmd.mse (d28:f0/f1/f2/f3/f4/f5:04:bit 1) is set. accesses from the attached device that are outside the ranges specified will be forwarded to the backbone if cmd.bme (d28:f0/f1/f2/f3/f4/f5:04:bit 2) is set. the comparison performed is mb ad[31:20] ml. 18.1.17 pmbl?prefetchable memory base and limit register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 24h?27h attribute: r/w, ro default value: 00010001h size: 32 bits accesses that are within the ranges specified in this register will be sent to the device if cmd.mse (d28:f0/f1/f2/f3/f4/f5;04, bit 1) is set. accesses from the device that are outside the ranges specified will be forwarded to the backbone if cmd.bme (d28:f0/f1/ f2/f3/f4/f5;04, bit 2) is set. the comparison performed is pmbu32:pmb ad[63:32]:ad[31:20] pmlu32:pml. bit description 31:20 memory limit (ml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the upper 1- mb aligned value of the range. 19:16 reserved 15:4 memory base (mb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1- mb aligned value of the range. 3:0 reserved bit description 31:20 prefetchable memory limit (pml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine th e upper 1-mb aligned value of the range. 19:16 64-bit indicator (i64l) ? ro. in dicates support for 64-bit addressing 15:4 prefetchable memory base (pmb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine th e lower 1-mb aligned value of the range. 3:0 64-bit indicator (i64b) ? ro. indi cates support for 64-bit addressing pci express* configuration registers 708 intel ? ich8 family datasheet 18.1.18 pmbu32?prefetchable memory base upper 32 bits register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 28h?2bh attribute: r/w default value: 00000000h size: 32 bits 18.1.19 pmlu32?prefetchable memory limit upper 32 bits register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 2ch?2fh attribute: r/w default value: 00000000h size: 32 bits 18.1.20 capp?capabilities list pointer register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 34h attribute: r0 default value: 40h size: 8 bits bit description 31:0 prefetchable memory base upper portion (pmbu) ? r/w. this field provides the upper 32-bits of the prefetchable address base. bit description 31:0 prefetchable memory limit upper portion (pmlu) ? r/w. this field provides the upper 32-bits of the prefetchable address limit. bit description 7:0 capabilities pointer (ptr) ? ro. this field indicates th at the pointer for the first entry in the capabilities list is at 40h in configuration space. intel ? ich8 family datasheet 709 pci express* configuration registers 18.1.21 intr?interrupt information register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 3ch?3dh attribute: r/w, ro default value: see bit description size: 16 bits 18.1.22 bctrl?bridge control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 3eh?3fh attribute: r/w default value: 0000h size: 16 bits bit description 15:8 interrupt pin (ipin) ? ro. this field indicates the in terrupt pin driven by the root port. at reset, this register takes on the following values , which reflect the reset state of the d28ip register in chipset configuration space: note: the value that is programmed into d28ip is always reflected in this register. 7:0 interrupt line (iline) ? r/w. default = 00h. software written value to indicate which interrupt line (v ector) the interrupt is connected to. no hardware action is taken on this register. port reset value 1 d28ip.p1ip 2 d28ip.p2ip 3 d28ip.p3ip 4 d28ip.p4ip 5 d28ip.p5ip 6 d28ip.p6ip bit description 15:12 reserved 11 discard timer serr# enable (dtse): reserved per pci express* base specification, revision 1.0a 10 discard timer status (dts): reserved per pci express* base specification, revision 1.0a. 9 secondary discard timer (sdt): reserved per pci express* base specification, revision 1.0a. 8 primary discard timer (pdt): reserved per pci express* base specification, revision 1.0a. 7 fast back to back enable (fbe): reserved per pci express* base specification, revision 1.0a. 6 secondary bus reset (sbr) ? r/w. triggers a hot rese t on the pci express* port. 5 master abort mode (mam): reserved per express specification. 4 vga 16-bit decode (v16) ? r/w. 0 = vga range is enabled. 1 = the i/o aliases of the vga range (see bc trl:ve definition belo w), are not enabled, and only the base i/o ranges can be decoded pci express* configuration registers 710 intel ? ich8 family datasheet 18.1.23 clist?capabilities list register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 40?41h attribute: ro default value: 8010h size: 16 bits 18.1.24 xcap?pci express* capabilities register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 42h?43h attribute: r/wo, ro default value: 0041h size: 16 bits 3 vga enable (ve) ? r/w. 0 = disable. the ranges below will not be cl aimed off the backbone by the root port. 1 = enable. the following ranges will be cl aimed off the backbone by the root port: ? memory ranges a0000h?bffffh ? i/o ranges 3b0h ? 3bbh and 3c0h ? 3dfh, and a ll aliases of bits 15:10 in any combination of 1s 2 isa enable (ie) ? r/w. this bit only applies to i/ o addresses that are enabled by the i/o base and i/o limit registers and ar e in the first 64 kb of pci i/o space. 0 = disable. the root port will not block an y forwarding from the ba ckbone as described below. 1 = enable. the root port will block any forw arding from the backbone to the device of i/o transactions addressing the last 768 bytes in each 1-kb block (offsets 100h to 3ffh). 1 serr# enable (se) ? r/w. 0 = disable. the messages de scribed below are not forwarded to the backbone. 1 = enable. err_cor, err_nonfatal, an d err_fatal messages received are forwarded to the backbone. 0 parity error response enable (pere) ? r/w. when set, 0 = disable. poisoned write tlps and completi ons indicating poisoned tlps will not set the ssts.dpd (d28:f0/f1/f2/f3/f4/f5:1e, bit 8). 1 = enable. poisoned write tlps and completi ons indicating poisoned tlps will set the ssts.dpd (d28:f0/f1/f2/f3/f4/f5:1e, bit 8). bit description bit description 15:8 next capability (next) ? ro. value of 80h indicates the location of the next pointer. 7:0 capability id (cid) ? ro. indicates this is a pci express* capability. bit description 15:14 reserved 13:9 interrupt message number (imn) ? ro. the intel ? ich8 does not have multiple msi interrupt numbers. 8 slot implemented (si) ? r/wo. this bit indicates whethe r the root port is connected to a slot. slot support is platfo rm specific. bios programs this field, and it is maintained until a platform reset. 7:4 device / port type (dt) ? ro. indicates this is a pci express* root port. 3:0 capability version (cv) ? ro. indicates pci express 1.0. intel ? ich8 family datasheet 711 pci express* configuration registers 18.1.25 dcap?device capa bilities register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 44h?47h attribute: ro default value: 00000fc0h size: 32 bits bit description 31:28 reserved 27:26 captured slot power limit scale (csps) ? ro. not supported. 25:18 captured slot power limit value (cspv) ? ro. not supported. 17:16 reserved 15 role based error reporting (rber) ? ro. this bit indicates that this device implements the functionality de fined in the error reporting ecn as required by the pci express 1.1 spec. 14 power indicator present (pip) ? ro. this bit indicates no power indicator is present on the root port. 13 attention indicator present (aip) ? ro. this bit indicates no attention indicator is present on the root port. 12 attention button present (abp) ? ro. this bit indicates no attention button is present on the root port. 11:9 endpoint l1 acceptable latency (e1al) ? ro. this bit indicates more than 4 s. this field essentially has no meaning for r oot ports since root po rts are not endpoints. 8:6 endpoint l0 acceptable latency (e0al) ? ro. this bit indicates more than 64 s. this field essentially has no meaning for r oot ports since root po rts are not endpoints. 5 extended tag field supported (etfs) ? ro. this bit indicate s that 8-bit tag fields are supported. 4:3 phantom functions supported (pfs) ? ro. no phantom functions supported. 2:0 max payload size supported (mps) ? ro. this field in dicates the maximum payload size supported is 128b. pci express* configuration registers 712 intel ? ich8 family datasheet 18.1.26 dctl?device control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 48h?49h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15 reserved 14:12 max read request size (mrrs) ? ro. hardwired to 0. 11 enable no snoop (ens) ? ro. not supported. the root port will never issue non- snoop requests. 10 aux power pm enable (apme) ? r/w. the os will set th is bit to 1 if the device connected has detected aux power. it has no effect on the root port otherwise. 9 phantom functions enable (pfe) ? ro. not supported. 8 extended tag field enable (etfe) ? ro. not supported. 7:5 max payload size (mps) ? r/w. the root port only supports 128-b payloads, regardless of the programming of this field. 4 enable relaxed ordering (ero) ? ro. not supported. 3 unsupported request reporting enable (ure) ? r/w. 0 = disable. the root port will ig nore unsupported request errors. 1 = enable. allows signalin g err_nonfatal, err_fatal, or err_cor to the root control register when detecting an un masked unsupported request (ur). an err_cor is signaled when a unmasked ad visory non-fatal ur is received. an err_fatal, err_or nonfatal, is sent to the root control register when an uncorrectable non-advisory ur is rece ived with the severity set by the uncorrectable error severity register. 2 fatal error reporting enable (fee) ? r/w. 0 = disable. the root port will ignore fatal errors. 1 = enables signaling of err_fatal to the root control register due to internally detected errors or error mess ages received across the li nk. other bits also control the full scope of related error reporting. 1 non-fatal error reporting enable (nfe) ? r/w. 0 = disable. the root port wi ll ignore non-fatal errors. 1 = enables signaling of err_nonfatal to th e root control register due to internally detected errors or error mess ages received across the li nk. other bits also control the full scope of related error reporting. 0 correctable error reporting enable (cee) ? r/w. 0 = disable. the root port will ignore correctable errors. 1 = enables signaling of err_corr to the root control register due to internally detected errors or error mess ages received across the li nk. other bits also control the full scope of related error reporting. intel ? ich8 family datasheet 713 pci express* configuration registers 18.1.27 dsts?device status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 4ah?4bh attribute: r/wc, ro default value: 0010h size: 16 bits 18.1.28 lcap?link capabilities register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 4ch ? 4fh attribute: r/wo, ro default value: see bit description size: 32 bits bit description 15:6 reserved 5 transactions pending (tdp) ? ro. this bit has no mean ing for the root port since only one transaction may be pending to the intel ? ich8, so a read of this bit cannot occur until it has already returned to 0. 4 aux power detected (apd) ? ro. the root port contains aux power for wakeup. 3 unsupported request detected (urd) ? r/wc. indicates an unsupported request was detected. 2 fatal error detected (fed) ? r/wc. indicates a fatal error was detected. 0 = fatal error has not occurred. 1 = a fatal error occurred from a data link prot ocol error, link training error, buffer overflow, or malformed tlp. 1 non-fatal error detected (nfed) ? r/wc. indicates a non- fatal error was detected. 0 = non-fatal error has not occurred. 1 = a non-fatal error occurred from a po isoned tlp, unexpected completions, unsupported requ ests, completer abort, or completer timeout. 0 correctable error detected (ced) ? r/wc. indicates a correctable error was detected. 0 = correctable error has not occurred. 1 = the port received an internal correct able error from receiver errors / framing errors, tlp crc error, dllp crc error, replay num rollover, replay timeout. bit description 31:24 port number (pn) ? ro. this field indicates the port number for the root port. this value is different for each implemented port: 23:21 reserved 20 link active reporting capable (larc) ? ro. ha rdwired to 1 to indica te that this port supports the optional capability of report ing the dl_active state of the data link control and management state machine. function port # value of pn field d28:f0 1 01h d28:f1 2 02h d28:f2 3 03h d28:f3 4 04h d28:f4 5 05h d28:f5 6 06h pci express* configuration registers 714 intel ? ich8 family datasheet 19:18 reserved 17:15 l1 exit latency (el1) ? ro. set to 010b to indicate an exit latency of 2 s to 4 s. 14:12 l0s exit latency (el0) ? ro. this field indicates as exit latency based upon common-clock configuration. note: lclt.ccc is at d28:f0/f 1/f2/f3/f4/f5:50h:bit 6 11:10 active state link pm support (apms) ? r/wo. this field indicates what level of active state link power management is supported on the root port. 9:4 maximum link width (mlw) ? ro. for the root ports, several values can be taken, based upon the value of the chipset config register field rpc.pc1 (chipset config registers:offset 0224h:bits1:0) for ports 1-4 and rpc.pc2 (chipset config registers:offset 0224h:bits1:0) for ports 5 and 6 3:0 maximum link speed (mls) ? ro. set to 1h to indicate the link speed is 2.5 gb/s. bit description lclt . ccc v a l ue o f el0 (th ese bit s ) 0 mpc.ucel (d28:f0/f1/f2/ f3:d8h:bits20:18) 1 mpc.ccel (d28:f0/f1/f2/ f3:d8h:bits17:15) bits definition 00b neither l0s nor l1 are supported 01b l0s entry supported 10b l1 entry supported 11b both l0s and l1 entry supported value of mlw field port # rpc.pc1=00b rpc.pc1=11b 1 01h 04h 2 01h 01h 3 01h 01h 4 01h 01h port # rpc.pc2=00b rpc.pc2=11b 5 01h n/a 6 01h n/a intel ? ich8 family datasheet 715 pci express* configuration registers 18.1.29 lctl?link control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 50h-51h attribute: r/w, wo, ro default value: 0000h size: 16 bits bit description 15:8 reserved 7 extended synch (es) ? r/w. 0 = extended synch disabled. 1 = forces extended transmission of fts ordered sets in fts and extra ts2 at exit from l1 prior to entering l0. 6 common clock configuration (ccc) ? r/w. 0 = the ich8 and device are not using a common reference clock. 1 = the ich8 and device are operating wi th a distributed comm on reference clock. 5 retrain link (rl) ? wo. 0 = this bit always returns 0 when read. 1 = the root port will train its downstream link. note: software uses lsts.lt (d28:f0/f1/f2/f3/f4/f5:52, bit 11) to check the status of training. 4 link disable (ld) ? r/w. 0 = enabled. 1 = the root port will disable the link. 3 read completion boundary control (rcbc) ? ro. this bit indicates the read completion boundary is 64 bytes. 2 reserved 1:0 active state link pm control (apmc) ? r/w. this field indi cates whether the root port should enter l0s or l1 or both. bits definition 00b disabled 01b l0s entry is enabled 10b l1 entry is enabled 11b l0s and l1 entry enabled pci express* configuration registers 716 intel ? ich8 family datasheet 18.1.30 lsts?link status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 52h?53h attribute: ro default value: see bit description size: 16 bits bit description 15:14 reserved 13 data link layer active (dlla) ? ro. default value is 0b. 0 = data link control and management stat e machine is not in the dl_active state 1 = data link control and management st ate machine is in the dl_active state 12 slot clock configuration (scc) ? ro. se t to 1b to indicate that the intel ? ich8 uses the same reference clock as on the platform and does not generate its own clock. 11 link training (lt) ? ro. default value is 0b. 0 = link training completed. 1 = link training is occurring. 10 link training error (lte ) ? ro. not supported. set value is 0b. 9:4 negotiated link width (nlw) ? ro. this field indicates the negotiated width of the given pci express* link. the co ntents of this nlw field is undefined if the link has not successfully trained. note: 000001b = x1 link width, 000010b =x2 linkwidth (not supported), 000100b = x4 linkwidth 3:0 link speed (ls) ? ro. this field indicates the nego tiated link speed of the given pci express* link. 01h = link is 2.5 gb/s. port # possible values 1 000001b, 000010b, 000100b 2 000001b 3 000001b 4 000001b 5 000001b, 000010b 6 000001b intel ? ich8 family datasheet 717 pci express* configuration registers 18.1.31 slcap?slot capa bilities register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 54h ? 57h attribute: r/wo, ro default value: 00000060h size: 32 bits bit description 31:19 physical slot number (psn) ? r/wo. this is a value that is unique to the slot number. bios sets this field and it remains set until a platform reset. 18:17 reserved 16:15 slot power limit scale (sls) ? r/wo. this field specifies the scale used for the slot power limit value. bios sets this field and it remains set until a platform reset. 14:7 slot power limit value (slv) ? r/wo. specifies the upper limit (in conjunction with sls value), on the upper limit on power suppl ied by the slot. the two values together indicate the amount of power in watts allowe d for the slot. bios sets this field and it remains set until a platform reset. 6 hot plug capable (hpc) ? ro. 1 = hot-plug is supported. 5 hot plug surprise (hps) ? ro. 1 = device may be removed from the slot without prior notification. 4 power indicator present (pip) ? ro. 0 = power indicator led is not present for this slot. 3 attention indicator present (aip) ? ro. 0 = attention indicator led is not present for this slot. 2 mrl sensor present (msp) ? ro. 0 = mrl sensor is not present. 1 power controller present (pcp) ? ro. 0 = power controller is not implemented for this slot. 0 attention button present (abp) ? ro. 0 = attention button is not implemented for this slot. pci express* configuration registers 718 intel ? ich8 family datasheet 18.1.32 slctl?slot control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 58h ? 59h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:13 reserved 12 link active changed enable (lace) ? r/w. when set, this field enables generation of a hot plug interrupt when the data link layer link active field (d28:f0/f1/f2/f3/f4/ f5:52h:bit 13) is changed. 0 = disable. 1 = enable. 11 reserved 10 power controller control (pcc) ? ro.this bit has no meaning for module based hot-plug. 9:8 power indicator control (pic) ? r/w. when read, the cu rrent state of the power indicator is returned. when written, the appropriate power_indicator_* messages are sent. defined encodings are: 7:6 attention indicator control (aic) ? r/w. when read, th e current state of the attention indicator is returned. when writ ten, the appropriate attention_indicator_* messages are sent. defined encodings are: 5 hot plug interrupt enable (hpe) ? r/w. 0 = disable. hot plug interrupts based on hot-plug events is disabled. 1 = enables generation of a hot-plug interrupt on enabled hot-plug events. 4 command completed interrupt enable (cce) ? r/w. 0 = disable. hot plug interrupts based on command completions is disabled. 1 = enables the generation of a hot-plug interrupt when a command is completed by the hot-plug controller. 3 presence detect changed enable (pde) ? r/w. 0 = hot plug interrupts based on presen ce detect logic changes is disabled. 1 = enables the generation of a hot-plug interrupt or wake message when the presence detect logic changes state. bits definition 00b reserved 01b on 10b blink 11b off bits definition 00b reserved 01b on 10b blink 11b off intel ? ich8 family datasheet 719 pci express* configuration registers 18.1.33 slsts?slot status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 5ah ? 5bh attribute: r/wc, ro default value: 0000h size: 16 bits 2 mrl sensor changed enable (mse) ? r/w. mse not supported. 1 power fault detected enable (pfe) ? r/w. pfe not supported. 0 attention button pressed enable (abe) ? r/w. when set, enables the generation of a hot-plug interrupt when the attention button is pressed. 0 = disable. hot plug interrupts based on the attention button being pressed is disabled. 1 = enables the generation of a hot-plug interrupt when the at tention button is pressed. bit description bit description 15:9 reserved 8 link active state changed (lasc) ? r/wc. this bit is set when the value reported in data link layer link active field of th e link status register (d28:f0/f1/f2/f3/f4/ f5:52h:bit 13) is changed. in response to a data link layer state changed event, software must read data link layer link ac tive field of the link status register to determine if the link is active before initia ting configuration cycles to the hot plugged device. 0 = no change. 1 = change 7 reserved 6 presence detect state (pds) ? ro. if xcap.si (d28:f0/f1/f2/f3/f4/f5:42h:bit 8) is set (indicating that this root po rt spawns a slot), then this bit: 0 = slot is empty. 1 = slot has a device connected. otherwise, if xcap.si is cleared, this bit is always set to 1. 5 mrl sensor state (ms) ? reserved as the mrl sensor is not implemented. 4 command completed (cc) ? r/wc. 0 = issued command not completed. 1 = the hot-plug controller completed an is sued command. this is set when the last message of a command is sent and indicates that software can write a new command to the slot controller. 3 presence detect changed (pdc) ? r/wc. 0 = no change in the pds bit. 1 = the pds bit changed states. 2 mrl sensor changed (msc) ? reserved as the mrl sensor is not implemented. 1 power fault detected (pfd) ? reserved as a power controller is not implemented. 0 attention button pressed (abp) ? r/wc. 0 = the attention button has not been pressed. 1 = the attention bu tton is pressed. pci express* configuration registers 720 intel ? ich8 family datasheet 18.1.34 rctl?root control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 5ch ? 5dh attribute: r/w default value: 0000h size: 16 bits 18.1.35 rsts?root status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 60h ? 63h attribute: r/wc, ro default value: 00000000h size: 32 bits bit description 15:4 reserved 3 pme interrupt enable (pie) ? r/w. 0 = disable. interrupt generation disabled. 1 = interrupt generation en abled when pcists.inerrupt status (d28:f0/f1/f2/f3/f4/ f5:60h, bit 16) is in a set state (either due to a 0-to-1 transition, or due to this bit being set with rsts.is already set). 2 system error on fatal error enable (sfe) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be genera ted, assuming cmd.see (d28:f0/f1/f2/f3/f4/f5:04, bit 8) is set, if a fatal error is reported by any of the devices in the hierarchy of this root port, including fatal errors in this root port. 1 system error on non-fatal error enable (sne) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be genera ted, assuming cmd.see (d28:f0/f1/f2/f3/f4/f5:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the hierarchy of this root port, including non-fa tal errors in this root port. 0 system error on correctable error enable (sce) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be genera ted, assuming cmd.see (d28:f0/f1/f2/f3/f4/f5:04, bit 8) if a correctable error is reported by an y of the devices in the hierarchy of this root port, including correctable errors in this root port. bit description 31:18 reserved 17 pme pending (pp) ? ro. 0 = when the original pme is cleared by softwa re, it will be set ag ain, the requestor id will be updated, and th is bit will be cleared. 1 = another pme is pending when the pme status bit is set. 16 pme status (ps) ? r/wc. 0 = pme was not asserted. 1 = pme was asserted by the requestor id in rid. subsequent p mes are kept pending until this bit is cleared. 15:0 pme requestor id (rid) ? ro. this field indicates the pci requestor id of the last pme requestor. valid on ly when ps is set. intel ? ich8 family datasheet 721 pci express* configuration registers 18.1.36 mid?message signaled in terrupt identifi ers register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 80h?81h attribute: ro default value: 9005h size: 16 bits 18.1.37 mc?message signaled inte rrupt message control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 82?83h attribute: r/w, ro default value: 0000h size: 16 bits 18.1.38 ma?message signaled interrupt message address register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 84h ? 87h attribute: r/w default value: 00000000h size: 32 bits bit description 15:8 next pointer (next) ? ro. indicates the location of the next pointer in the list. 7:0 capability id (cid) ? ro. capabilities id indicates msi. bit description 15:8 reserved 7 64 bit address capable (c64) ? ro. capable of generating a 32-bit message only. 6:4 multiple message enable (mme) ? r/w. these bits are r/w for software compatibility, but only one message is ever sent by the root port. 3:1 multiple message capable (mmc) ? ro. only one message is required. 0 msi enable (msie) ? r/w. 0 = disabled. 1 = msi is enabled and traditional interrupt pins are not used to generate interrupts. note: cmd.bme (d28:f0/f1/f2/f3/f4/f5:04h:bit 2) must be set for an msi to be generated. if cmd.bme is clea red, and this bit is set, no interrupts (not even pin based) are generated. bit description 31:2 address (addr) ? r/w. this field provides the lowe r 32 bits of the system specified message address, al ways dw aligned. 1:0 reserved pci express* configuration registers 722 intel ? ich8 family datasheet 18.1.39 md?message signaled in terrupt message data register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 88h ? 89h attribute: r/w default value: 0000h size: 16 bits 18.1.40 svcap?subsystem vend or capability register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 90h ? 91h attribute: ro default value: a00dh size: 16 bits 18.1.41 svid?subsystem vendor identification register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 94h ? 97h attribute: r/wo default value: 00000000h size: 32 bits 18.1.42 pmcap?power management capability register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: a0h ? a1h attribute: ro default value: 0001h size: 16 bits bit description 15:0 data (data) ? r/w. this field is programmed by system software if msi is enabled. its content is driven onto the lower word (pci ad[15:0]) during the data phase of the msi memory write transaction. bit description 15:8 next capability (next) ? ro. indicates the location of the next pointer in the list. 7:0 capability identifier (cid) ? ro. value of 0dh indicates this is a pci bridge subsystem vendor capability. bit description 31:16 subsystem identifier (sid) ? r/wo. indicates the subsys tem as identified by the vendor. this field is write once and is locked down until a bridge reset occurs (not the pci bus reset). 15:0 subsystem vendor identifier (svid) ? r/wo. indicates the manufacturer of the subsystem. this field is write once and is locked down until a bridge rese t occurs (not the pci bus reset). bit description 15:8 next capability (next) ? ro. indicates this is the last item in the list. 7:0 capability identifier (cid) ? ro. value of 01h indicates this is a pci power management capability. intel ? ich8 family datasheet 723 pci express* configuration registers 18.1.43 pmc?pci power manageme nt capabilities register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: a2h ? a3h attribute: ro default value: c802h size: 16 bits bit description 15:11 pme_support (pmes) ? ro. indicates pm e# is supported for states d0, d3 hot and d3 cold . the root port does not generate pme#, but reporting that it does is necessary for some legacy operating systems to enable pme# in devices connected behind this root port. 10 d2_support (d2s) ? ro. the d2 state is not supported. 9 d1_support (d1s) ? ro the d1 state is not supported. 8:6 aux_current (ac) ? ro. reports 375 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi) ? ro. indicates that no device-specific initialization is required. 4 reserved 3 pme clock (pmec) ? ro. indicates that pci clock is not required to generate pme#. 2:0 version (vs) ? ro. indicates support for revision 1.1 of the pci power management specification . pci express* configuration registers 724 intel ? ich8 family datasheet 18.1.44 pmcs?pci power mana gement control and status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: a4h ? a7h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 31:24 reserved 23 bus power / clock control enable (bpce) ? reserved per pci express* base specification, revision 1.0a . 22 b2/b3 support (b23s) ? reserved per pci express* base specification, revision 1.0a . 21:16 reserved 15 pme status (pmes) ? ro. 0 = pme not received. 1 = pme was received on the downstream link. 14:9 reserved 8 pme enable (pmee) ? r/w. the root port takes no acti on on this bit, but it must be r/w for some legacy operating systems to enable pme# on devices connected to this root port. this bit is sticky and resides in the resume well. the reset for this bit is rsmrst# which is not asserted du ring a warm reset. 0 = disable 1 = enable 7:2 reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the root port and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state note: when in the d3 hot state, the controller?s config uration space is available, but the i/o and memory spaces are not. type 1 configuration cycles are also not accepted. interrupts are not required to be blocked as software will disable interrupts prior to placing the port into d3 hot . if software attempts to write a ?10? or ?01? to these bits, the write will be ignored. intel ? ich8 family datasheet 725 pci express* configuration registers 18.1.45 mpc?miscellaneous port configuration register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: d8h ? dbh attribute: r/w, ro default value: 08110000h size: 32 bits bit description 31 power management sc i enable (pmce) ? r/w. 0 = disable. sci generation based on a power management event is disabled. 1 = enables the root port to generate sc i whenever a power management event is detected. 30 hot plug sci enable (hpce) ? r/w. 0 = disable. sci generation based on a hot-plug event is disabled. 1 = enables the root port to generate sc i whenever a hot-plug event is detected. 29 link hold off (lho): when set, the port will not take any tlp. this is used during loopback mode to fill up the downstream queue. 28 address translator enable (ate): used to enable address tr anslation via the at bits in this register during loopback mode. 27 lane reversal (lr) ? ro. this register reads the setting of the sataled# strap. 0 = pci express lanes 0?3 are reversed. 1 = no lane reversal (default). notes: 1. the port configuration straps must be set such that port 1 is configured as a x4 port using lanes 0?3 when lane reversal is enabled. x2 lane reversal is not supported. 2. this register is only valid on port 1. 26 invalid receive bus number check enable (irbnce): when set, the receive transaction layer will signal an error if th e bus number of a memory request does not fall within the range between scbn and sbbn . if this check is en abled and the request is a memory write, it is treated as an unsu pported request. if this check is enabled and the request is a non-posted memory read requ est, the request is considered a malformed tlp and a fatal error. messages, io, configuration, and completion s are never checked for valid bus number. 25 invalid receive range check enable (irrce): when set, the receive transaction layer will treat the tlp as an unsupported request error if the address range of a memory request does not outside the range between prefetchable and non-prefetchable base and limit. messages, i/o, configuration, and comple tions are never checked for valid address ranges. 24 bme receive check enable (bmerce): when set, the receive transaction layer will treat the tlp as an unsupported request erro r if a memory read or write request is received and the bus master enable bit is not set. messages, i/o, configuration, and co mpletions are never checked for bme. 23:21 reserved 20:18 unique clock exit latency (ucel) ? r/w. this value represents the l0s exit latency for unique-clock configurations (lctl.ccc = 0) (d 28:f0/f1/f2/f3/f4/ f5:offset 50h:bit 6). it defaults to 512 ns to less than 1 s, bu t may be overridden by bios. pci express* configuration registers 726 intel ? ich8 family datasheet 17:15 common clock exit latency (ccel) ? r/w. this value represents the l0s exit latency for common-clock configuratio ns (lctl.ccc = 1) (d28:f0/f1/f2/f3/f4/ f5:offset 50h:bit 6). it defaults to 128 ns to less than 256 ns, but may be overridden by bios. 14:8 reserved 7 port i/oxapic enable (pae) ? r/w. 0 = hole is disabled. 1 = a range is opened through the bri dge for the following memory addresses: 6:3 reserved 2 bridge type (bt) ? ro. this register can be used to modify the base class and header type fields from the de fault pci-to-pci bridge to a host bridge. having the root port appear as a host bridge is us eful in some server configurations. 0 = the root port bridge type is a pci- to-pci bridge, header sub-class = 04h, and header type = type 1. 1 = the root port bridge type is a pci- to-pci bridge, header sub-class = 00h, and header type = type 0. 1 hot plug smi enable (hpme) ? r/w. 0 = disable. smi generation based on a hot-plug event is disabled. 1 = enables the root port to generate sm i whenever a hot-plug event is detected. 0 power management smi enable (pmme) ? r/w. 0 = disable. smi generation based on a power management event is disabled. 1 = enables the root port to generate sm i whenever a power management event is detected. bit description port # address 1 fec1_0000h ? fec1_7fffh 2 fec1_8000h ? fec1_ffffh 3 fec2_0000h ? fec2_7fffh 4 fec2_8000h ? fec2_ffffh 5 fec3_0000h ? fec3_7fffh 6 fec3_8000h ? fec3_ffffh intel ? ich8 family datasheet 727 pci express* configuration registers 18.1.46 smscs?smi/sci status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: dch ? dfh attribute: r/wc default value: 00000000h size: 32 bits bit description 31 power management sci status (pmcs) ? r/wc. this bit is set if the pme control logic needs to generate an in terrupt, and this inte rrupt has been routed to generate an sci. 30 hot plug sci status (hpcs) ? r/wc. this bit is set if the hot-plug controller needs to generate an interrupt, and has this in terrupt been routed to generate an sci. 29:5 reserved 4 hot plug link active state changed smi status (hplas) ? r/wc. this bit is set when slsts.lasc (d28:f0/f1/f2/f3/f4/f5:5a, bit 8) transitions from 0-to-1, and mpc.hpme (d28:f0/f1/f2/f3/f4/f5:d8, bit 1) is set. when this bit is set, an smi# will be generated. 3 hot plug command completed smi status (hpccm) ? r/wc. this bit is set when slsts.cc (d28:f0/f1/f2/f3/f4/f5:5a, bit 4) transitions from 0-to-1, and mpc.hpme (d28:f0/f1/f2/f3/f4/f5:d8, bit 1) is set. when this bit is set, an smi# will be generated. 2 hot plug attention butt on smi status (hpabm) ? r/wc. this bit is set when slsts.abp (d28:f0/f1/f2/f3/f4/f5:5a, bit 0) transitions from 0-to-1, and mpc.hpme (d28:f0/f1/f2/f3/f4/f5:d8, bit 1) is set. when this bit is set, an smi# will be generated. 1 hot plug presence detect smi status (hppdm) ? r/wc. this bit is set when slsts.pdc (d28:f0/f1/f2/f3/f4/f5:5a, bit 3) transitions from 0-to-1, and mpc.hpme (d28:f0/f1/f2/f3/f4/f5:d8, bit 1) is set. when this bit is set, an smi# will be generated. 0 power management smi status (pmms) ? r/wc. this bit is set when rsts.ps (d28:f0/f1/f2/f3/f4/f5:60, bit 16) transitions from 0-to-1, and mpc.pmme (d28:f0/ f1/f2/f3/f4/f5:d8, bit 1) is set. pci express* configuration registers 728 intel ? ich8 family datasheet 18.1.47 rpdcgen?root port dy namic clock gating enable (pci express-d28:f0/f1/f2 /f3/f4/f5) (mobile only) address offset: e1h attribute: r/w default value: 00h size: 8-bits 18.1.48 ipws?intel ? pro/wireless 3945abg status (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: e2h?e3h attribute: ro default value: 0007h size: 16 bits bits description 7:4 reserved. ro 3 shared resource dynamic link cl ock gating enable (srdlcgen) ? rw. 1 = enables dynamic clock gating on the root port shared resource link clock domain. 0 = disables dynamic clock gating of the shared resource link clock domain. only the value from port 1 is used for ports 1?4. only the value from port 5 is used for ports 5-6. 2 shared resource dynamic backbone clock gate enable (srdbcgen) ? rw. 1 = enables dynamic clock gating on the r oot port shared reso urce backbone clock domain. 0 = disables dynamic clock ga ting of the shared resour ce backbone clock domain. only the value from port 1 is used for ports 1?4. only the value from port 5 is used for ports 5-6. 1 root port dynamic link cloc k gate enable (rpdlcgen) ? rw. 1 = enables dynamic clock gating on the root port link clock domain. 0 = disables dynamic cloc k gating of the root port link clock domain. 0 root port dynamic backbone cl ock gate enable (rpdbcgen) ? rw. 1 = enables dynamic clock gating on th e root port backbone clock domain. 0 = disables dynamic clock gating of the root port backbone clock domain. bit description 15 intel pro/wireless 3945abg status (ipwstat) ? ro. this bit is set if the link has trained to l0 in intel pro/wireless 3945abg mode. 14:0 reserved intel ? ich8 family datasheet 729 pci express* configuration registers 18.1.49 vch?virtual channel ca pability header register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 100h ? 103h attribute: ro default value: 18010002h size: 32 bits 18.1.50 vcap2?virtual channe l capability 2 register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 108h ? 10bh attribute: ro default value: 00000001h size: 32 bits 18.1.51 pvc?port virtual channel control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 10ch ? 10dh attribute: r/w default value: 0000h size: 16 bits 18.1.52 pvs ? port virtual channel status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 10eh ? 10fh attribute: ro default value: 0000h size: 16 bits bit description 31:20 next capability offset (nco) ? ro. indicates the next item in the list. 19:16 capability version (cv) ? ro. indicates this is version 1 of the capability structure by the pci sig. 15:0 capability id (cid) ? ro. indicates this is the virtual channel capability item. bit description 31:24 vc arbitration table offset (ato) ? ro. indicates that no table is present for vc arbitration since it is fixed. 23:0 reserved. bit description 15:4 reserved. 3:1 vc arbitration select (as) ? r/w. indicates which vc should be programmed in the vc arbitration table. the root port takes no action on the setting of this field since there is no arbitration table. 0 load vc arbitration table (lat) ? r/w. indicates that the table programmed should be loaded into the vc arbitration ta ble. this bit always returns 0 when read. bit description 15:1 reserved. 0 vc arbitration table status (vas) ? ro. indicates the coherency status of the vc arbitration table when it is be ing updated. this fi eld is always 0 in the root port since there is no vc arbitration table. pci express* configuration registers 730 intel ? ich8 family datasheet 18.1.53 v0cap ? virtual channel 0 resource capability register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 110h ? 113h attribute: ro default value: 00000001h size: 32 bits bit description 31:24 port arbitration table offset (at) ? ro. this vc implements no po rt arbitration table since the arbitration is fixed. 23 reserved. 22:16 maximum time slots (mts) ? ro. this vc im plements fixed arbitration, and therefore this field is not used. 15 reject snoop transactions (rts) ? ro. this vc must be able to take snoopable transactions. 14 advanced packet switching (aps) ? ro. this vc is capable of all transactions, not just advanced packet switching transactions. 13:8 reserved. 7:0 port arbitration capability (pac) ? ro. in dicates that this vc uses fixed port arbitration. intel ? ich8 family datasheet 731 pci express* configuration registers 18.1.54 v0ctl ? virtual channel 0 resource control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 114h ? 117h attribute: r/w, ro default value: 800000ffh size: 32 bits 18.1.55 v0sts ? virtual channel 0 resource status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 11ah ? 11bh attribute: ro default value: 0000h size: 16 bits bit description 31 virtual channel enable (en) ? ro. always set to 1. virtual channel 0 cannot be disabled. 30:27 reserved. 26:24 virtual channel identifier (vcid) ? ro. in dicates the id to use fo r this virtual channel. 23:20 reserved. 19:17 port arbitration select (pas) ? r/w. indica tes which port table is being programmed. the root complex takes no action on this se tting since the arbitration is fixed and there is no arbitration table. 16 load port arbitration table (lat) ? ro. the r oot port does not implement an arbitration table for this virtual channel. 15:8 reserved. 7:1 transaction class / virtual channel map (tvm) ? r/w. this field indicates which transaction classes are mapped to this virtual channel. when a bit is set, this transaction class is mapped to the virtual channel. 0 reserved. transaction class 0 must always mapped to vc0. bit transaction class 7 transaction class 7 6 transaction class 6 5 transaction class 5 4 transaction class 4 3 transaction class 3 2 transaction class 2 1 transaction class 1 0 transaction class 0 bit description 15:2 reserved. 1 vc negotiation pending (np) ? ro. 0 = negotiation is not pending. 1 = indicates the virtual channel is stil l being negotiated wi th ingress ports. 0 port arbitration tables status (ats). there is no port arbitration table for this vc, so this bit is reserved as 0. pci express* configuration registers 732 intel ? ich8 family datasheet 18.1.56 ues ? uncorrectable error status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 144h ? 147h attribute: r/wc, ro default value: 00000000000x0xxx 0x0x0000000x0000b size: 32 bits this register maintains its state through a platform reset. it loses its state upon suspend. bit description 31:21 reserved 20 unsupported request error status (ure) ? r/wc. 0 = unsupported requ est not received. 1 = unsupported requ est was received. 19 ecrc error status (ee) ? ro. ecrc is not supported. 18 malformed tlp status (mt) ? r/wc. 0 = malformed tlp not received. 1 = malformed tlp was received. 17 receiver overflow status (ro) ? r/wc. 0 = no receiver overflow. 1 = receiver overflow occurred. 16 unexpected completion status (uc) ? r/wc. 0 = unexpected completion not received. 1 = unexpected completion was received. 15 completion abort status (ca) ? r/wc. 0 = completer abort not received. 1 = completer abort was received. 14 completion timeout status (ct) ? r/wc. indicates a completion timed out. this bit is set if completion timeout is enabled an d a completion is not returned between 40 and 50 ms. 13 flow control protocol error status (fcpe) ? ro. flow control protocol errors not supported. 12 poisoned tlp status (pt) ? r/wc. 0 = poisoned tlp not received. 1 = poisoned tlp was received. 11:5 reserved 4 data link protocol error status (dlpe) ? r/wc. 0 = no data link protocol error. 1 = data link protocol error occurred. 3:1 reserved 0 training error status (te) ? ro. training errors not supported. intel ? ich8 family datasheet 733 pci express* configuration registers 18.1.57 uem ? uncorrec table error mask (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 148h ? 14bh attribute: r/wo, ro default value: 00000000h size: 32 bits when set, the corresponding error in the ue s register is masked, and the logged error will cause no action. when cleared, the corresponding error is enabled. bit description 31:21 reserved 20 unsupported request error mask (ure) ? r/wo. 0 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5:144) is masked. 19 ecrc error mask (ee) ? ro. ecrc is not supported. 18 malformed tlp mask (mt) ? r/wo. 0 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5:144) is masked. 17 receiver overflow mask (ro) ? r/wo. 0 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5:144) is masked. 16 unexpected completion mask (uc) ? r/wo. 0 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5:144) is masked. 15 completion abort mask (ca) ? r/wo. 0 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is enabled. 1 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is masked. 14 completion timeout mask (ct) ? r/wo. 0 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5:144) is masked. 13 flow control protocol error mask (fcpe) ? ro. flow control pr otocol errors not supported. 12 poisoned tlp mask (pt) ? r/wo. 0 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5:144) is masked. 11:5 reserved 4 data link protocol error mask (dlpe) ? r/wo. 0 = the corresponding error in the ues regist er (d28:f0/f1/f2/f3/f4/f5:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5:144) is masked. 3:1 reserved 0 training error mask (te) ? ro. training errors not supported pci express* configuration registers 734 intel ? ich8 family datasheet 18.1.58 uev ? uncorrecta ble error severity (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 14ch ? 14fh attribute: ro default value: 00060011h size: 32 bits bit description 31:21 reserved 20 unsupported request error severity (ure) ? ro. 0 = error considered no n-fatal. (default) 1 = error is fatal. 19 ecrc error severity (ee) ? ro. ecrc is not supported. 18 malformed tlp severity (mt) ? ro. 0 = error considered non-fatal. 1 = error is fatal. (default) 17 receiver overflow severity (ro) ? ro. 0 = error considered non-fatal. 1 = error is fatal. (default) 16 unexpected completion severity (uc) ? ro. 0 = error considered no n-fatal. (default) 1 = error is fatal. 15 completion abort severity (ca) ? ro. 0 = error considered no n-fatal. (default) 1 = error is fatal. 14 completion timeout severity (ct) ? ro. 0 = error considered no n-fatal. (default) 1 = error is fatal. 13 flow control protocol error severity (fcpe) ? ro. flow control protocol errors not supported. 12 poisoned tlp severity (pt) ? ro. 0 = error considered no n-fatal. (default) 1 = error is fatal. 11:5 reserved 4 data link protocol error severity (dlpe) ? ro. 0 = error considered non-fatal. 1 = error is fatal. (default) 3:1 reserved 0 training error severity (te) ? ro. te is not supported. intel ? ich8 family datasheet 735 pci express* configuration registers 18.1.59 ces ? correctable error status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 150h ? 153h attribute: r/wc default value: 00000000h size: 32 bits bit description 31:14 reserved 13 advisory non-fatal error status (anfes) ? r/wc. 0 = advisory non-fatal error did not occur. 1 = advisory non-fatal error did occur. 12 replay timer timeout status (rtt) ? r/wc. 0 = no replay timer time out. 1 = replay timer timed out occurred. 11:9 reserved 8 replay number rollover status (rnr) ? r/wc. 0 = replay number did not roll over. 1 = replay number rolled over. 7 bad dllp status (bd) ? r/wc. 0 = bad dllp not received. 1 = bad dllp was received. 6 bad tlp status (bt) ? r/wc. 0 = bad tlp not received. 1 = bad tlp was received. 5:1 reserved 0 receiver error status (re) ? r/wc. 0 = receiver error did not occurred. 1 = receiver error occurred. pci express* configuration registers 736 intel ? ich8 family datasheet 18.1.60 cem ? correctable error mask register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 154h ? 157h attribute: r/wo default value: 00000000h size: 32 bits when set, the corresponding error in the ce s register is masked, and the logged error will cause no action. when cleared, the corresponding error is enabled. 18.1.61 aecc ? advanced error ca pabilities and control register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 158h ? 15bh attribute: ro default value: 00000000h size: 32 bits bit description 31:14 reserved 13 advisory non-fatal error mask (anfem) ? r/wo. 0 = does not mask advisory non-fatal errors. 1 = masks advisory non-fatal errors from (a ) signaling err_cor to the device control register and (b) updating the unco rrectable error status register. this register is set by defa ult to enable compatibility wi th software that does not comprehend role-based error reporting. 12 replay timer timeout mask (rtt) ? r/wo. mask for replay timer timeout. 11:9 reserved 8 replay number rollover mask (rnr) ? r/wo. mask for replay number rollover. 7 bad dllp mask (bd) ? r/wo. mask for bad dllp reception. 6 bad tlp mask (bt) ? r/wo. mask for bad tlp reception. 5:1 reserved 0 receiver error mask (re) ? r/wo. mask for receiver errors. bit description 31:9 reserved 8 ecrc check enable (ece) ? ro. ecrc is not supported. 7 ecrc check capable (ecc) ? ro. ecrc is not supported. 6 ecrc generation enable (ege) ? ro. ecrc is not supported. 5 ecrc generation capable (egc) ? ro. ecrc is not supported. 4:0 first error pointer (fep) ? ro. intel ? ich8 family datasheet 737 pci express* configuration registers 18.1.62 res ? root erro r status register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 170h ? 173h attribute: r/wc, ro default value: 00000000h size: 32 bits 18.1.63 rctcl ? root complex topology capability list register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 180 ? 183h attribute: ro default value: 00010005h size: 32 bits bit description 31:27 advanced error interrupt message number (aemn) ? ro. there is only one error interrupt allocated. 26:4 reserved 3 multiple err_fatal/nonfatal received (menr) ? ro. for intel ? ich8, only one error will be captured. 2 err_fatal/nonfatal received (enr) ? r/wc. 0 = no error message received. 1 = either a fatal or a non-fata l error message is received. 1 multiple err_cor received (mcr) ? ro. for ich8, only one error will be captured. 0 err_cor received (cr) ? r/wc. 0 = no error message received. 1 = a correctable error message is received. bit description 31:20 next capability (next) ? ro. indicates the next item in the list, in this case, end of list. 19:16 capability version (cv) ? ro. indicates the version of the capability structure. 15:0 capability id (cid) ? ro. indicates this is a root complex topology capability. pci express* configuration registers 738 intel ? ich8 family datasheet 18.1.64 esd ? element self description register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 184h ? 187h attribute: ro default value: see description size: 32 bits 18.1.65 uld ? upstream link description register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 190h ? 193h attribute: ro default value: 00000001h size: 32 bits bit description 31:24 port number (pn) ? ro. this field indicate the ingr ess port number for the root port. there is a different value per port: 23:16 component id (cid) ? ro. this field returns the valu e of the esd.cid field (chipset config space: offset 0104h:bits 23:16) of the chip configuration section, that is programmed by platform bios, since the root port is in the sa me component as the rcrb. 15:8 number of link entries (nle) ? ro. (default value is 01h) indicates one link entry (corresponding to the rcrb). 7:4 reserved. 3:0 element type (et) ? ro. (default value is 0h) indicates that the element type is a root port. port # value 1 01h 2 02h 3 03h 4 04h 5 05h 6 06h bit description 31:24 target port number (pn) ? ro. indicates the po rt number of the rcrb. 23:16 target component id (tcid) ? ro. this field returns th e value of the esd.cid field (chipset configuration space: offset 0104h, bits 23:16) of the chip configuration section, that is programmed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved. 1 link type (lt) ? ro. indicates that the link points to the intel ? ich8 rcrb. 0 link valid (lv) ? ro. indicates that this link entry is valid. intel ? ich8 family datasheet 739 pci express* configuration registers 18.1.66 ulba ? upstream link base address register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 198h ? 19fh attribute: ro default value: see description size: 64 bits 18.1.67 peetm ? pci ex press* extended te st mode register (pci express?d28:f0/f1/f2/f3/f4/f5) address offset: 318h attribute: ro default value: see description size: 8 bits bit description 63:32 base address upper (bau) ? ro. the rcrb of the intel ? ich8 is in 32-bit space. 31:0 base address lower (bal) ? ro. this field matches the rcba register (d31:f0:offset f0h) va lue in the lpc bridge. bit description 7:3 reserved 2 scrambler bypass mode (bau) ? r/w. 0 = normal operation. scrambler and descrambler are used. 1 = bypasses the data scrambler in the transmit direction and the data de-scrambler in the receive direction. note: this functionality intended for debug/testing only. note: if bypassing scrambler with ic h8 root port 1 in x4 configuration, each ich8 root port must have this bit set. 1:0 reserved pci express* configuration registers 740 intel ? ich8 family datasheet intel ? ich8 family datasheet 741 high precision event timer registers 19 high precision event timer registers the timer registers are memory-mapped in a non-indexed scheme. this allows the processor to directly access each register without having to use an index register. the timer register space is 1024 bytes. the registers are generally aligned on 64-bit boundaries to simplify implementation with ia64 processors. there are four possible memory address ranges beginning at 1) fed0_0000h, 2) fed0_1000h, 3) fed0_2000h., 4) fed0_4000h. the choice of address range will be selected by configuration bits in the high precision timer configuration register (chipset configuration registers:offset 3404h). behavioral rules: 1. software must not attempt to read or write across register boundaries. for example, a 32-bit access should be to offs et x0h, x4h, x8h, or xch. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0ah, 0bh, 0dh, 0eh, or 0fh. any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. however, these accesse s should not result in system hangs. 64-bit accesses can only be to x0h and must not cross 64-bit boundaries. 2. software should not write to read only registers. 3. software should not expect any partic ular or consistent value when reading reserved registers or bits. 19.1 memory-mapped registers table 142. memory-mapped re gisters (sheet 1 of 2) offset mnemonic register default type 000?007h gcap_id general capabilities and identification 0429b17f8 086a201h ro 008?00fh ? reserved ? ? 010?017h gen_conf general configuration 0000h r/w 018?01fh ? reserved ? ? 020?027h gintr_sta general interrupt status 00000000 00000000h r/wc, r/w 028?0efh ? reserved ? ? 0f0?0f7h main_cnt main counter value n/a r/w 0f8?0ffh ? reserved ? ? 100?107h tim0_conf timer 0 configuration and capabilities n/a r/w, ro 108?10fh tim0_comp timer 0 comparator value n/a r/w 110?11fh ? reserved ? ? 120?127h tim1_conf timer 1 configuration and capabilities n/a r/w, ro 128?12fh tim1_comp timer 1 comparator value n/a r/w 130?13fh ? reserved ? ? high precision event timer registers 742 intel ? ich8 family datasheet notes: 1. reads to reserved registers or bits will return a value of 0. 2. software must not at tempt locks to the memory-mapped i/o ranges for high precision event timers. if attempted, the lock is not honored, wh ich means potential deadlock conditions may occur. 19.1.1 gcap_id?general capabilities and identification register address offset: 00h attribute: ro default value: 0429b17f8086a201h size: 64 bits 140?147h tim2_conf timer 2 configuration and capabilities n/a r/w, ro 148?14fh tim2_comp timer 2 comparator value n/a r/w 150?15fh ? reserved ? ? 160?3ffh ? reserved ? ? table 142. memory-mapped re gisters (sheet 2 of 2) offset mnemonic register default type bit description 63:32 main counter tick period (counter_clk_p er_cap) ? ro. this field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). this will return 0429b17f when read. this indicates a period of 69841279 fs (69.841279 ns). 31:16 vendor id capability (vendor_id_cap) ? ro . this is a 16-bit value assigned to intel. 15 legacy replacement rout capable (leg_r t_cap) ? ro. hardwired to 1. legacy replacement interrupt rout option is supported. 14 reserved. this bit returns 0 when read. 13 counter size capability (count_size_cap) ? ro. hardwired to 1. counter is 64-bit wide. 12:8 number of timer capability (num_tim_cap) ? ro. this field indicates the number of timers in this block. 02h = three timers. 7:0 revision identification (rev_id) ? ro. this indicates which revision of the function is implemented. default value will be 01h. intel ? ich8 family datasheet 743 high precision event timer registers 19.1.2 gen_conf?general configuration register address offset: 010h attribute: r/w default value: 00000000 00000000h size: 64 bits 19.1.3 gintr_sta?general in terrupt status register address offset: 020h attribute: r/w, r/wc default value: 00000000 00000000h size: 64 bits . bit description 63:2 reserved. these bits return 0 when read. 1 legacy replacement rout (leg_rt_cnf) ? r/w. if the enable_cnf bit and the leg_rt_cnf bit are both set, then the interrupts will be routed as follows: ? timer 0 is routed to irq0 in 8259 or irq2 in the i/o apic ? timer 1 is routed to irq8 in 8259 or irq8 in the i/o apic ? timer 2-n is routed as per the routing in the timer n config registers. ? if the legacy replacement rout bit is set, the in dividual routing bits for timers 0 and 1 (apic) will have no impact. ? if the legacy replacement rout bit is not set, th e individual routing bits for each of the timers are used. ? this bit will default to 0. bios can set it to 1 to enable the legacy replacement routing, or 0 to disable the legacy replacement routing. 0 overall enable (enable_cnf) ? r/w. this bit must be set to enable any of the timers to generate interrupts. if this bit is 0, then the main counter will halt (will not increment) and no inte rrupts will be caused by any of these timers. for level-triggered interrupts, if an interrupt is pending when the enable_cnf bit is changed from 1 to 0, the interrupt status indications (in the various txx_int_sts bits) will not be cleared. software must write to the txx_in t_sts bits to clear the interrupts. note: this bit will default to 0. bios can set it to 1 or 0. bit description 63:3 reserved. these bits wi ll return 0 when read. 2 timer 2 interrupt act ive (t02_int_sts) ? r/w. same functionality as timer 0. 1 timer 1 interrupt act ive (t01_int_sts) ? r/w. same functionality as timer 0. 0 timer 0 interrupt act ive (t00_int_sts) ? r/wc. the functionality of this bit depends on whether the edge or level-triggered mode is used for this timer. (default = 0). if set to level-triggered mode: this bit will be set by hardware if the corre sponding timer interrupt is active. once the bit is set, it can be cleared by software writ ing a 1 to the same bit position. writes of 0 to this bit will have no effect. if set to edge-triggered mode: this bit should be ignored by software. software should always write 0 to this bit. note: defaults to 0. in edge tri ggered mode, this bit will al ways read as 0 and writes will have no effect. high precision event timer registers 744 intel ? ich8 family datasheet 19.1.4 main_cnt?main counter value register address offset: 0f0h attribute: r/w default value: n/a size: 64 bits . 19.1.5 timn_conf?timer n configuration and capabilities register address offset: timer 0: 100?107h, attribute: ro, r/w timer 1: 120?127h, timer 2: 140?147h default value: n/a size: 64 bits note: the letter n can be 0, 1, or 2, referring to timer 0, 1 or 2. bit description 63:0 counter value (counter_val[63:0]) ? r/w. reads return the current value of the counter. writes load the new value to the counter. notes: 1. writes to this register should only be done while the counter is halted. 2. reads to this register return th e current value of the main counter. 3. 32-bit counters will always return 0 for the upper 32-bits of this register. 4. if 32-bit software attempts to read a 64-bit counter, it should first halt the counter. since this delays the interrupts for all of the timers , this should be done only if the consequences are un derstood. it is strongly recommended that 32-bit software only oper ate the timer in 32-bit mode. 5. reads to this register are monotonic. no two consecutive reads return the same value. the second of two reads always returns a larger value (unless the timer has rolled over to 0). bit description 63:56 reserved. these bits will return 0 when read. 55:52, 43 timer interrupt rout capabi lity (timern_int_rout_cap) ? ro. timer 0, 1:bits 52, 53, 54, and 55 in this field (corresponding to irq 20, 21, 22, and 23) have a value of 1. writ es will have no effect. timer 2:bits 43, 52, 53, 54, and 55 in this field (corresponding to irq 11, 20, 21, 22, and 23) have a value of 1. writes will have no effect. note: if irq 11 is used for hpet #2, software should ensure irq 11 is not shared with any other devices to assure the proper operation of hpet #2. 51:44, 42:14 reserved . these bits return 0 when read. 13:9 interrupt rout (timern_int_rout_cnf) ? r/w. this 5-bit field indicates the routing for the interrupt to the i/o (x) apic. software writes to this field to select which interrupt in the i/o (x) wi ll be used for this timer?s interrupt. if the value is not supported by this particular timer, then the value read back will not match what is written. the software must only write valid values. notes: 1. if the legacy replacement rout bit is set, then timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. 2. timer 0,1: software is responsible to ma ke sure it programs a valid value (20, 21, 22, or 23) for this field. the ich8 logic does not check the validity of the value written. 3. timer 2: software is responsible to ma ke sure it programs a valid value (11, 20, 21, 22, or 23) for this field. the ic h8 logic does not check the validity of the value written. intel ? ich8 family datasheet 745 high precision event timer registers note: reads or writes to unimpleme nted timers should not be attempted. read from any unimplemented registers will re turn an undetermined value. 8 timer n 32-bit mode (timern_32mode_cnf) ? r/w or ro. software can set this bit to force a 64-bit timer to behave as a 32-bit timer. timer 0: bit is read/write (default to 0). 0 = 64 bit; 1 = 32 bit timers 1, 2: hardwired to 0. writes have no effect (since thes e two timers are 32- bits). note: when this bit is set to ?1?, the hardware counter will do a 32-bit operation on comparator match and ro llovers, thus the uppe r 32-bit of the timer 0 comparator value register is ignored. th e upper 32-bit of the main counter is not involved in any rollover from lo wer 32-bit of the main counter and becomes all zeros. 7 reserved. this bit returns 0 when read. 6 timer n value set (timern_val_set_cnf) ? r/w. software uses this bit only for timer 0 if it has been set to periodic mo de. by writing this bit to a 1, the software is then allowed to directly set the timer?s accumulator. software does not have to write this bit back to 1 (it automatically clears). software should not write a 1 to this bit position if the timer is set to non-periodic mode. note: this bit will return 0 when read. writes will only have an effect for timer 0 if it is set to periodic mode. writes will have no effect for timers 1 and 2. 5 timer n size (timern_size_cap) ? ro. this read only field indicates the size of the timer. timer 0: value is 1 (64-bits). timers 1, 2: value is 0 (32-bits). 4 periodic interrupt capa ble (timern_per_int_cap) ? ro. if this bit is 1, the hardware supports a periodic mo de for this timer?s interrupt. timer 0: hardwired to 1 (suppo rts the periodic interrupt). timers 1, 2: hardwired to 0 (doe s not support periodic interrupt). 3 timer n type (timern_type_cnf) ? r/w or ro. timer 0: bit is read/write. 0 = disable timer to generate periodic interrupt; 1 = enable timer to genera te a periodic interrupt. timers 1, 2: hardwired to 0. writes have no affect. 2 timer n interrupt enable (timern_int_enb_cnf) ? r/w. this bi t must be set to enable timer n to cause an interrupt when it times out. 1 = enable. 0 = disable (default). the timer can still co unt and generate appr opriate status bits, but will not cause an interrupt. 1 timer interrupt type (timern_int_type_cnf) ? r/w. 0 = the timer interrupt is edge triggered. this means that an edge-type interrupt is generated. if another in terrupt occurs, an other edge will be generated. 1 = the timer interrupt is level triggered. this means that a leve l-triggered interrupt is generated. the interrupt will be held active until it is cleared by writing to the bit in the general interrupt status register . if another interrupt occurs before the interrupt is cleared, the in terrupt will remain active. 0 reserved . these bits will return 0 when read. bit description high precision event timer registers 746 intel ? ich8 family datasheet 19.1.6 timn_comp?timer n co mparator value register address offset: timer 0: 108h?10fh, timer 1: 128h?12fh, timer 2: 148h?14fh attribute: r/w default value: n/a size: 64 bit bit description 63:0 timer compare value ? r/w. reads to this register return the current value of the comparator timers 0, 1, or 2 are config ured to non-periodic mode: writes to this register load the value against which the main counter should be compared for this timer. ? when the main counter equals the value last written to this regi ster, the corresponding interrupt can be generated (if so enabled). ? the value in this register does not change based on the interrupt being generated. timer 0 is configured to periodic mode: ? when the main counter equals the value last written to this regi ster, the corresponding interrupt can be generated (if so enabled). ? a fter the main counter equals the value in this register, the value in this register is increased by the value last written to the register. for example, if the value written to the register is 00000123h, then 1. an interrupt will be generated when the main counter reaches 00000123h. 2. the value in this register will then be adjusted by the hardware to 00000246h. 3. another interrupt will be generate d when the main counter reaches 00000246h 4. the value in this register will then be adjusted by the hardware to 00000369h ? as each periodic interrupt oc curs, the value in this register will increment. when the incremented value is greater than the maximum value possible for this register (ffffffffh for a 32-bit timer or ffffffffffffffffh for a 64-bit timer), the value will wrap around through 0. for example, if the current value in a 32-bit timer is ffff0000h and the last value writte n to this register is 20000, then after the next interrupt the valu e will change to 00010000h default value for each timer is all 1s for th e bits that are implemented. for example, a 32-bit timer has a default value of 00000000ffffffffh. a 64-bit timer has a default value of ffffffffffffffffh. intel ? ich8 family datasheet 747 serial peripheral interface (spi) 20 serial peripheral interface (spi) the serial peripheral interface resides in memory-mapped space. this function contains registers that allow for the setup and programming of devices that reside on the spi interface. note: all registers in this function (including me mory-mapped registers) must be addressable in byte, word, and dword quantities. the software must always make register accesses on natural boundaries (i.e., dword accesses must be on dword boundaries; word accesses on word boundaries, etc.) in ad dition, the memory-mapped register space must not be accessed with the lock semantic exclusive-access mechanism. if software attempts exclusive-access mechanisms to the spi memory-mapped space, the results are undefined. 20.1 serial peripheral interface memory-mapped configuration registers the spi host interface registers are memo ry-mapped in the rcrb chipset register space with a base address (spibar) of 302 0h and are located within the range of 3020h to 30ffh. the individual registers are then accessible at spibar + offset as indicated in table 143 . these memory mapped registers must be accessed in byte, word, or dword quantities. table 143. serial peripheral inte rface (spi) register address map (spi memory mapped configuratio n registers) (sheet 1 of 2) spibar + offset mnemonic register name default access 00h?03h bfpr bios flash primary region 00000000h ro 04h?05h hsfs hardware sequencing flash status 0000h ro, r/wc, r/wl 06h?07h hsfc hardware sequencing flash control 0000h r/w, r/ws 08h?0bh faddr flash address 00000000h r/w 0ch?0fh ? reserved 00000000h ? 10h?13h fdata0 flash data 0 00000000h r/w 14h?4fh fdatan flash data n 00000000h r/w 50h?53h fracc flash region access permissions 00000000h ro, r/wl 54h?57h freg0 flash region 0 00000000h ro 58h?5bh freg1 flash region 1 00000000h ro 5ch?5f freg2 flash region 2 00000000h ro 60h?63h freg3 flash region 3 00000000h ro 64h?73h ? reserved ? ? 74h?77h fpr0 flash protected range 0 00000000h r/wl serial peripheral interface (spi) 748 intel ? ich8 family datasheet 20.1.1 bfpr?bios flash pr imary region register ( spi memory mapped configuration registers ) memory address:spibar + 00h attribute: ro default value: 00000000h size: 32 bits 78h?7bh fpr1 flash protected range 1 00000000h r/wl 7ch?7fh fpr2 flash protected range 2 00000000h r/wl 80?83h fpr3 flash protected range 3 00000000h r/wl 84h?87h fpr4 flash protected range 4 00000000h r/wl 88h?8fh ? reserved ? ? 90h ssfs software sequencing flash status 0000h ro, r/wc 91h?93h ssfc software sequencing flash control 0000h r/w 94h?95h preop prefix opcode configuration 0000h r/wl 96h?97h optype opcode type configuration 0000h r/w 98h?9fh opmenu opcode menu configuration 00000000 00000000h r/w b0h?b3h fdoc flash descriptor observability control 00000000h r/w b4h?b7h fdod flash descriptor observability data 00000000h ro b8h?dfh ? reserved ? ? c1h?c4h vscc vendor specific component capabilities 00000000h ro, r/wl table 143. serial peripheral inte rface (spi) register address map (spi memory mapped configuration register s) (sheet 2 of 2) spibar + offset mnemonic register name default access bit description 31:29 reserved 28:16 bios flash primary re gion limit (prl) ? ro. this field specifies address bits 24:12 for the primary region limit. the value in this register loaded from the contents in the flash descriptor.flreg 1.region limit. 15:13 reserved 12:0 bios flash primary region base (prb) ? ro. this field specifies address bits 24:12 for the primary region base the value in this register is load ed from the contents in the flash descriptor.flreg1.region base. intel ? ich8 family datasheet 749 serial peripheral interface (spi) 20.1.2 hsfs?hardware sequencing flash status register ( spi memory mapped co nfiguration registers ) memory address:spibar + 04h attribute: ro, r/wc, r/wl default value: 0000h size: 16 bits bit description 15 flash configuration lock-down (flockdn) ? r/w/l. when set to 1, the flash program registers that are locked down by this flockdn bit cannot be written. once set to 1, this bit can only be cleared by a hardware reset. hardware reset is initiated by one of the following resets: ? global reset (when the host and the me partitions are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. 14 flash descriptor valid (fdv)? ro. this bit is set to a 1 if the flash controller read the correct flash descriptor signature. if the flash descriptor valid bit is not 1, software cannot use the hardware sequencing registers, but must use the software sequencing registers. any attempt to use the hardware sequencing registers will result in the fcerr bit being set. 13 flash descriptor override pin-strap status (fdopss) ? ro: this bi t reflects the value the flash descriptor override pin-strap. 0 = the flash descriptor override strap is set 1 = no override 12:6 reserved 5 spi cycle in progress (scip)? ro. hardware sets this bi t when software sets the flash cycle go (fgo) bit in the hardware se quencing flash control register. this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can dete rmine when read data is valid and/or when it is safe to begin programming the next command. software must only program the next command when this bit is 0. 4:3 block/sector eras e size (berase) ? ro. this field identifies the erasable sector size for all flash components. valid bit settings: 00 = 256 byte 01 = 4 kb 10 = reserved for future use 11 = 64 kb 2 access error log (ael) ? r/w/c. hardware sets this bit to a 1 when an attempt was made to access the bios region using the di rect access method or an access to the bios program registers that violated the security restrictions. this bit is simply a log of an access security violatio n. this bit is cleared by software writing a 1. 1 flash cycle error (fcerr) ? r/w/c. hardware sets this bit to 1 when an program register access is blocked to the flash due to one of the protection policies or when any of the programmed cycle registers is wr itten while a programmed access is already in progress. this bit remains asserted until cleared by so ftware writing a 1 or until hardware reset occurs. software must clear this bit before setting the flash cycle go bit in this register. hardware reset is initiated by one of the following resets: ? global reset (when the host and the me partitions are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. serial peripheral interface (spi) 750 intel ? ich8 family datasheet 20.1.3 hsfc?hardware sequencing flash control register ( spi memory mapped configuration registers ) memory address:spibar + 06h attribute: r/w, r/ws default value: 0000h size: 16 bits 0 flash cycle done (fdone) ? r/w/c. the ich8 sets this bit to 1 when the spi cycle completes after software previously set the fgo bit. this bit re mains asserted until cleared by software writing a 1 or hardware reset. when this bit is set and the spi smi# enable bit is set, an internal signal is asserted to the sm i# generation block. software must make sure this bit is cleared prior to enabling the spi smi# assertion for a new programmed access. hardware reset is initiated by one of the fo llowing resets: ? global reset (when the host and the me partitio ns are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. bit description bit description 15 flash spi smi# enable (fsmie): ? r/w. when set to 1, the spi asserts an smi# request whenever the flash cycle done bit is 1. 14 reserved 13:8 flash data byte count (fdbc): ? r/w. this field specifie s the number of bytes to shift in or out during the data portion of the spi cycle. the contents of this register are 0?s based with 0b representing 1 byte and 111111b representing 64 bytes. the number of bytes transferred is the va lue of this field plus 1. this field is ignored for the block erase command. 7:3 reserved 2:1 flash cycle (fcycle) . ? r/w. this field defines the flash spi cycle type generated to the flash when the fgo bit is set as defined below: 00 = read (1 up to 64 bytes by setting fdbc) 01 = reserved 10 = write (1 up to 64 bytes by setting fdbc) 11 = block erase 0 flash cycle go (fgo): ? r/w/s. a write to this register with a 1 in this bit initiates a request to the flash spi arbiter to start a cy cle. this register is cleared by hardware when the cycle is granted by the spi arbiter to run the cycle on the spi bus. when the cycle is complete, the fdone bit is set. software is forbidden to write to any regist er in the hsflctl register between the fgo bit getting set and the fdone bi t being cleared. any attempt to violate this rule will be ignored by hardware. hardware allows other bits in this register to be progra mmed for the same transaction when writing this bit to 1. this saves an additional memory write. this bit always returns 0 on reads. intel ? ich8 family datasheet 751 serial peripheral interface (spi) 20.1.4 faddr?flash address register ( spi memory mapped co nfiguration registers ) memory address:spibar + 08h attribute: r/w default value: 00000000h size: 32 bits 20.1.5 fdata0?flash data 0 register ( spi memory mapped co nfiguration registers ) memory address:spibar + 10h attribute: r/w default value: 00000000h size: 32 bits 20.1.6 fdatan?flash da ta [n] register ( spi memory mapped co nfiguration registers ) memory address:spibar + 14h attribute: r/w spibar + 18h spibar + 1ch spibar + 20h spibar + 24h spibar + 28h spibar + 2ch spibar + 30h spibar + 34h spibar + 38h spibar + 3ch spibar + 40h spibar + 44h spibar + 48h spibar + 4ch default value: 00000000h size: 32 bits bit description 31:25 reserved 24:0 flash linear address (fla): ? r/w. the fla is the starting byte linear address of a spi read or write cycle or an address within a block for the block erase command. the flash linear address must fall within a regi on for which bios has access permissions. hardware must convert the fla into a flash physical address (fpa) before running this cycle on the spi bus. bit description 31:0 flash data 0 (fd0): ? r/w. this field is shifted ou t as the spi data on the master- out slave-in data pin during th e data portion of the spi cycle. this register also shifts in the data from th e master-in slave-out pin into this register during the data portion of the spi cycle. the data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant byte, msb to lsb, etc. specifically, the shift order on spi in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-?8-23-22-?16-31?24 bit 24 is the last bit shifted out/in. there are no alignment assumptions; byte 0 always represents the value specif ied by the cycle address. note that the data in this register may be modified by the hardware during any programmed spi transaction. direct memory re ads do not modify the contents of this register. bit description 31:0 flash data n (fd[n]): ? r/w. similar definition as flash data 0. however, this register does not be gin shifting until fd[n-1] has completely shifted in/out. serial peripheral interface (spi) 752 intel ? ich8 family datasheet 20.1.7 frap?flash regions access permissions register ( spi memory mapped configuration registers ) memory address:spibar + 50h attribute: ro, r/wl default value: 00000202h size: 32 bits 20.1.8 freg0?flash region 0 (f lash descriptor) register ( spi memory mapped configuration registers ) memory address:spibar + 54h attribute: ro default value: 00000000h size: 32 bits bit description 31:24 bios master write access grant (bmwag) : ? r/wl. each bit [31:29] corresponds to master[7:0]. bios can grant one or more masters write access to the bios region 1 overriding the permissions in the flash descriptor. master[1] is host cpu/bios, master[2] is me, master[3] is host cpu/gbe. master[0] and master[7:4] are reserved. the contents of this register are locked by the flockdn bit. 23:16 bios master read access grant (bmrag) : ? r/wl. each bit [28:16] corresponds to master[7:0]. bios can grant one or more masters read access to the bios region 1 overriding the read permissi ons in the flash descriptor. master[1] is host cpu/bios, master[2] is me, master[3] is host cpu/gbe. master[0] and master[7:4] are reserved. the contents of this register are locked by the flockdn bit 15:8 bios region write access (brwa) : ? ro. each bit [15:8] corresponds to regions [7:0]. if the bit is set, this master can er ase and write that part icular region through register accesses. the contents of this register are that of the flash descriptor. flash master 1 master region write access or a particular master has granted bios write permissions in their master write access grant register or the fl ash descriptor security override strap is set. 7:0 bios region read access (brra) : ? ro. each bit [7:0] corresponds to regions [7:0]. if the bit is set, this master can re ad that particular re gion through register accesses. the contents of this register are that of the flash descriptor.flash master 1.master region write access or a part icular master has granted bios read permissions in their master read access grant register or the fl ash descriptor security override strap is set. bit description 31:29 reserved 28:16 region limit (rl): ? ro. this field specifies addres s bits 24:12 for the region 0 limit. the value in this register is load ed from the contents in the flash descriptor.flreg0.region limit 15:13 reserved 12:0 region base (rb) / flash descript or base address region (fdbar): ? ro. this field specifies addr ess bits 24:12 for the region 0 base. the value in this register is load ed from the contents in the flash descriptor.flreg0.region base intel ? ich8 family datasheet 753 serial peripheral interface (spi) 20.1.9 freg1?flash region 1 (bios descriptor) register ( spi memory mapped co nfiguration registers ) memory address:spibar + 58h attribute: ro default value: 00000000h size: 32 bits 20.1.10 freg2?flash regi on 2 (me) register ( spi memory mapped co nfiguration registers ) memory address:spibar + 5ch attribute: ro default value: 00000000h size: 32 bits bit description 31:29 reserved 28:16 region limit (rl): ? ro. this field specifies addre ss bits 24:12 for the region 1 limit. the value in this register is load ed from the contents in the flash descriptor.flreg1. region limit. 15:13 reserved 12:0 region base (rb): ? ro. this field specifies addr ess bits 24:12 for the region 1 base. the value in this register is load ed from the contents in the flash descriptor.flreg1.region base. bit description 31:29 reserved 28:16 region limit (rl): ? ro. this field specifies addre ss bits 24:12 for the region 2 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 2.region limit. 15:13 reserved 12:0 region base (rb): ? ro. this field specifies addres s bits 24:12 for the region 2 base the value in this register is load ed from the contents in the flash descriptor.flreg2.region base. serial peripheral interface (spi) 754 intel ? ich8 family datasheet 20.1.11 freg3?flash regi on 3 (gbe) register ( spi memory mapped configuration registers ) memory address:spibar + 60h attribute: ro default value: 00000000h size: 32 bits 20.1.12 pr0?protected range 0 register ( spi memory mapped configuration registers ) memory address:spibar + 74h attribute: r/wl default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31:29 reserved 28:16 region limit (rl): ? ro. this field specifies addres s bits 24:12 for the region 3 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 3.region limit. 15:13 reserved 12:0 region base (rb): ? ro. this specifies address bits 24:12 for the region 3 base the value in this register is load ed from the contents in the flash descriptor.flreg3.region base. bit description 31 write protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and th at writes and erases directed to addresses between them (inclusive) must be blocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fiel ds are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range. intel ? ich8 family datasheet 755 serial peripheral interface (spi) 20.1.13 pr1?protected range 1 register ( spi memory mapped co nfiguration registers ) memory address:spibar + 78h attribute: r/wl default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. 20.1.14 pr2?protected range 2 register ( spi memory mapped co nfiguration registers ) memory address:spibar + 7ch attribute: r/wl default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31 write protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fields are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11: 0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range. bit description 31 write protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fields are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11: 0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range. serial peripheral interface (spi) 756 intel ? ich8 family datasheet 20.1.15 pr3?protected range 3 register ( spi memory mapped configuration registers ) memory address:spibar + 80h attribute: r/wl default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. 20.1.16 pr4?protected range 4 register ( spi memory mapped configuration registers ) memory address:spibar + 84h attribute: r/wl default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31 write protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and th at writes and erases directed to addresses between them (inclusive) must be blocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fiel ds are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range. bit description 31 write protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are va lid and that writes and erases directed to a ddresses between them (inclusive) must be bl ocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be bl ocked by hardware. the base and li mit fields are ig nored when this bit is cleared. 14:13 reserved 12:0 protected range base: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by th is protected range. intel ? ich8 family datasheet 757 serial peripheral interface (spi) 20.1.17 ssfs?software sequenci ng flash status register ( spi memory mapped co nfiguration registers ) memory address:spibar + 90h attribute: ro, r/wc default value: 00h size: 8 bits note: the software sequencing control and status registers are reserved if the hardware sequencing control and status registers are used. bit description 7:5 reserved 4 access error log (ael): ? ro. this bit reflects the value of the hardware sequencing status ael register. 3 flash cycle error (fcerr): ? r/wc. hardware sets this bit to 1 when a programmed access is blocked from running on the spi interface due to on e of the protection policies or when any of the programmed cycle register s is written while a programmed access is already in progress. this bit remains asserted until cleared by software writing a 1 or hardware reset. hardware reset is initiated by one of the following resets: ? global reset (when the host and the me partitions are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. 2 cycle done status: ? r/wc. the ich8 sets this bit to 1 when the spi cycle completes (i.e., scip bit is 0) after soft ware sets the go bit. this bi t remains asserted until cleared by software writing a 1 or hardware reset. wh en this bit is set and the spi smi# enable bit is set, an internal signal is asserted to the smi# gene ration block. software must make sure this bit is cleared prior to enabling the spi smi# assertion for a new programmed access. hardware reset is initiated by one of the following resets: ? global reset (when the host and the me partitions are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. 1 reserved 0 spi cycle in progress (scip): ? ro. hardware sets this bit when software sets the spi cycle go bit in the comman d register. this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. software must only program the next command when this bit is 0. serial peripheral interface (spi) 758 intel ? ich8 family datasheet 20.1.18 ssfc?software sequenci ng flash control register ( spi memory mapped configuration registers ) memory address:spibar + 91h attribute: r/w default value: 000000h size: 24 bits bit description 23:19 reserved 18:16 spi cycle frequency (scf): ? r/w. 000 = 20 mhz 001 = 33 mhz software should program this register to se t the frequency of the cycle that is to be run. 15 spi smi# enable (sme): ? r/w. when set to 1, the spi asserts an smi# request whenever the cycle done status bit is 1. 14 data cycle (ds): ? r/w. when set to 1, there is data that corresponds to this transaction. when 0, no data is delivered for this cycle, and the dbc and data fields themselves are don?t cares 13:8 data byte count (dbc): ? r/w. this field specifies the number of bytes to shift in or out during the data portion of the spi cycl e. the valid settings (in decimal) are any value from 0 to 63. the number of bytes transf erred is the value of this field plus 1. note that when this field is 00_0000b, then there is 1 byte to transfer and that 11_1111b means there are 64 bytes to transfer. 7 reserved 6:4 cycle opcode pointer (cop): ? r/w. this field selects one of the programmed opcodes in the opcode menu to be used as the spi command/opcode. in the case of an atomic cycle sequence, this determines the second command. ? r/w. 3 sequence prefix opcode pointer (spop): ? r/w. this field selects one of the two programmed prefix opcodes for use when performing an atomic cycle sequence. a value of 0 points to the opcode in the least significant byte of the prefix opcodes register. by making this programmable, th e ich8 supports flash devices that have different opcodes for enabling writes to the data space vs. status register. 2 atomic cycle sequence (acs): ? r/w. when set to 1 along with the scgo assertion, the ich8 will execute a sequence of commands on the spi interface without allowing the lan component to arbitrate and interleave cycles. the sequence is composed of: ? atomic sequence prefix command (8-bit opcode only) ? primary command specified below by so ftware (can include address and data) ? polling the flash status register (opcode 05h) until bit 0 becomes 0b. the spi cycle in progress bit remains set an d the cycle done status bit remains unset until the busy bit in the flas h status register returns 0. 1 spi cycle go (scgo): ? r/ws. this bit always returns 0 on reads. however, a write to this register with a ?1? in this bit starts the spi cycle defined by the other bits of this register. the ?spi cycle in progress? (scip) bit gets set by this action. hardware must ignore writes to this bit while the cycle in progress bit is set. hardware allows other bits in this register to be progra mmed for the same transaction when writing this bit to 1. this saves an additional memory write. 0 reserved intel ? ich8 family datasheet 759 serial peripheral interface (spi) 20.1.19 preop?prefix opcode configuration register ( spi memory mapped co nfiguration registers ) memory address:spibar + 94h attribute: r/wl default value: 0000h size: 16 bits note: this register is not writable when the flash configuration lock-down bit (spibar + 04h:15) is set. 20.1.20 optype?opcode type configuration register ( spi memory mapped co nfiguration registers ) memory address:spibar + 96h attribute: r/w default value: 0000h size: 16 bits entries in this register correspond to the entries in the opcode menu configuration register. note: the definition below only provides write protection for opcodes that have addresses associated with them. therefore, any erase or write opcodes that do not use an address should be avoided (for example, ?chip erase? and ?auto-address increment byte program?) note: this register is not writable when the spi configuration lock-down bit (spibar + 00h:15) is set. bit description 15:8 prefix opcode 1 ? r/w. software programs an spi opco de into this field that is permitted to run as the first comm and in an atomic cycle sequence. 7:0 prefix opcode 0 ? r/w. software programs an spi opco de into this field that is permitted to run as the first comm and in an atomic cycle sequence. bit description 15:14 opcode type 7 ? r/w. see the descriptio n for bits 1:0 13:12 opcode type 6 ? r/w. see the descriptio n for bits 1:0 11:10 opcode type 5 ? r/w. see the descriptio n for bits 1:0 9:8 opcode type 4 ? r/w. see the descriptio n for bits 1:0 7:6 opcode type 3 ? r/w. see the descriptio n for bits 1:0 5:4 opcode type 2 ? r/w. see the descriptio n for bits 1:0 3:2 opcode type 1 ? r/w. see the descriptio n for bits 1:0 1:0 opcode type 0 ? r/w. this field specifies informat ion about the corresponding opcode 0. this information allows the hardwa re to 1) know whether to use the address field and 2) provide bios and shared flash pr otection capabilities. the encoding of the two bits is: 00 = no address associated with this opcode; read cycle type 01 = no address associated with this opcode; write cycle type 10 = address required; read cycle type 11 = address required; write cycle type serial peripheral interface (spi) 760 intel ? ich8 family datasheet 20.1.21 opmenu?opcode menu configuration register ( spi memory mapped configuration registers ) memory address:spibar + 98h attribute: r/w default value: 0000000000000000h size: 64 bits eight entries are available in this register to give bios a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. this keeps the hardware flexible enough to operate with a wide variety of spi devices. note: it is recommended that bios avoid progra mming write enable op codes in this menu. malicious software could then perform writes and erases to the spi flash without using the atomic cycle mechanism. this could cause functional failures in a shared flash environment. write enable opcodes should on ly be programmed in the prefix opcodes. this register is not writable when the spi configuration lock-down bit (spibar + 00h:15) is set. bit description 63:56 allowable opcode 7 ? r/w. see the description for bits 7:0 55:48 allowable opcode 6 ? r/w. see the description for bits 7:0 47:40 allowable opcode 5 ? r/w. see the description for bits 7:0 39:32 allowable opcode 4 ? r/w. see the description for bits 7:0 31:24 allowable opcode 3 ? r/w. see the description for bits 7:0 23:16 allowable opcode 2 ? r/w. see the description for bits 7:0 15:8 allowable opcode 1 ? r/w. see the description for bits 7:0 7:0 allowable opcode 0 ? r/w. software programs an spi opcode into this field for use when initiating spi commands through the control register. intel ? ich8 family datasheet 761 serial peripheral interface (spi) 20.1.22 fdoc?flash descriptor ob servability control register ( spi memory mapped co nfiguration registers ) memory address:spibar + b0h attribute: r/w default value: 00000000h size: 32 bits note: this register that can be used to observe the contents of the flash descriptor that is stored in the ich8 flash controller. 20.1.23 fdod?flash descriptor ob servability data register ( spi memory mapped co nfiguration registers ) memory address:spibar + b4h attribute: ro default value: 00000000h size: 32 bits note: this register that can be used to observe the contents of the flash descriptor that is stored in the ich8 flash controller. bit description 31:15 reserved 14:12 flash descriptor section select (fdss) : ? r/w. this field selects which section within the loaded flash descriptor to observe. 000 = flash signature and descriptor map 001 = component 010 = region 011 = master 100 = ich8 soft straps 111 = reserved 11:2 flash descriptor section index (fdsi): ? r/w. this field selects the dw offset within the flash descript or section to observe. 1:0 reserved bit description 31:0 flash descriptor section data (fdsd): ? ro. this field returns the dw of data to observe as selected in the flash descriptor observability control. serial peripheral interface (spi) 762 intel ? ich8 family datasheet 20.1.24 vscc?vendor specific comp onent capabiliti es register ( spi memory mapped configuration registers ) memory address:spibar + c1h attribute: ro, r/wl default value: 00000000h size: 32 bits bit description 23 vendor component lock (vcl): ? r/w: 0 = the lock bit is not set 1 = the vendor component lock bit is set. this register locks itself when set. 22:16 reserved 15:8 erase opcode (eo) ? r/w: this register is pr ogrammed with the flash erase instruction opcode required by the vendor?s flash component. note: if there is more than one component, both components must use the same erase opcode. this register is locked by the vendor component lock (vcl) bit. 7:4 reserved 3 write status required (wsr) ? r/w 0 = no enable write to the status register ( 50h) opcode is required to write to the spi flash status register(s) prior to write or erase to remove spi flash protection. 1 = enable write to the status register (50h) opcode is required to write to the spi flash status register(s) prior to write or erase to remove spi flash protection. note: if there is more than one component, both components must use the same write status required setting. spi protec tion is removed by writing 00h to spi flash status register(s). 2 write granularity (wg) ? r/w: 0 = 1 byte 1 = 64 byte this register is locked by the vendor component lock (vcl) bit. note: if more than one flash component exists, this field must be set to the lowest common write granularity of th e different flash components. 1:0 block/sector erase size (bses)? r/w: this field identifies the erasable sector size for all flash components. 00 = 256 byte 01 = 4 kb 10 =reserved for future use 11 = 64 kb this register is locked by the vendor component lock (vcl) bit. note: if supporting more than one flash compon ent, all flash comp onents must have identical block/sector erase sizes. this register is locked by the vendor component lock (vcl) bit. hardware takes no action based on the valu e of this register. th e contents of this register are to be used only by softwa re and can be read in the hsfsts.berase register in both the bios and the gbe program registers. intel ? ich8 family datasheet 763 serial peripheral interface (spi) 20.2 flash descriptor registers the following sections describe the data st ructure of the flash descriptor on the spi device. these are not registers within the ich8. 20.2.1 flash descriptor content 20.2.1.1 flvalsig?flash valid signature register (flash descriptor memory ma pped configuration registers) memory address:fdbar + 000h size: 32 bits 20.2.1.2 flmap0?flash map 0 register (flash descriptor memory ma pped configuration registers) memory address:fdbar + 004h size: 32 bits bits description 31:0h flash valid signature: this field identifies the flash descriptor sector as valid. if the contents at this location contain 0ff0a55ah, then the flash descriptor is considered valid and it will operate in descriptor mode, else it will operate in non-descriptor mode. bits description 31:27 reserved 26:24 number of regions (nr): this field identifies the total number of flash regions. this number is 0?s based, so a setting of all 0s in dicates that the only flash region is region 0, the flash desc riptor region. 23:16 flash region base address (frba): this identifies addres s bits [11:4] for the region portion of the fl ash descriptor. bits [24:12] and bits [3:0] are 0. for validation purposes, th e recommended frba is: 04h 15:10 reserved 9:8 number of components (nc) : this field identifies the total number of flash components. each supported flash compon ent requires a separate chip select 00 = 1 component 01 = 2 components all other settings = reserved 7:0 flash component base address (fcba) : this identifies address bits [11:4] for the component portion of the flash descriptor. bits [24:12] and bits [3:0] are 0. for validation purposes, th e recommended fcba is: 01h. serial peripheral interface (spi) 764 intel ? ich8 family datasheet 20.2.1.3 flmap1?flash map 1 register (flash descriptor memory ma pped configuration registers) memory address:fdbar + 008h size: 32 bits 20.2.1.4 flmap2?flash map 2 register (flash descriptor memory ma pped configuration registers) memory address:fdbar + 00ch size: 32 bits bits description 31:24 ich8 strap length (isl): this field identifies the 1?s based number of dwords of ich8 straps to be read, up to 255 dws (1 kb) maximum. a setting of all 0s indicates there are no ich8 dw straps. 23:16 flash ich8 strap base address (fisba): this field identifies a ddress bits [11:4] for the ich8 strap portion of the flash descri ptor. bits [24:12] and bits [3:0] are 0. for validation purposes, th e recommended fisba is: 10h 15:11 reserved 10:8 number of masters (nm): this field identifies the total number of flash regions. this number is 0?s based. 7:0 flash master base address (fmba): this identifies addre ss bits [11:4] for the master portion of the flash descriptor. bits [24:12] and bits [3:0] are 0. for validation purposes, th e recommended fmba is: 06h bits description 31:16 reserved 15:8 mch strap length (msl): this field identifies the 1s ba sed number of dwords of mch straps to be read, up to 255 dws (1 kb) ma ximum. a setting of all 0s indicates there are no mch dw straps. 7:0 flash mch strap base address (fmsba): this identifies addres s bits [11:4] for the mch strap portion of the flash descript or. bits [24:12] and bits [3:0] are 0. for validation purposes, th e recommended fmsba is: 20h intel ? ich8 family datasheet 765 serial peripheral interface (spi) 20.2.2 flash descriptor component section the following section of the flash descriptor is used to identify the different flash components and their capabilities. 20.2.2.1 flcomp?flash components register (flash descriptor memory ma pped configuration registers) memory address:fcba + 000h size: 32 bits bits description 31:30 reserved 29:27 read id and read status clock frequency: 000 = 20 mhz 001 = 33 mhz all other settings: reserved note: if more than one flash component exists, this field must be set to the lowest common frequency of the di fferent flash components. 26:24 write and erase clock frequency: 000 = 20 mhz 001 = 33 mhz all other settings: reserved note: if more than one flash component exists, this field must be set to the lowest common frequency of the di fferent flash components. 23:21 fast read clock frequency : this field identifies the freq uency that can be used with the fast read instruction. this field is un defined if the fast read support field is 0. 000 = 20 mhz 001 = 33 mhz all other settings = reserved note: if more than one flash component exists, this field must be set to the lowest common frequency of the di fferent flash components. 20 fast read support: 0 = fast read is not supported 1 =fast read is supported if the fast read support bit is a '1' and a de vice issues a direct re ad or issues a read command from the hardware se quencer and the length is greater than 4 bytes, then the spi flash instruction should be "fast read". if the fast read support is a '0' or the length is 1-4 bytes, then the spi flash instruction should be "read". reads to the flash descriptor always use the read comman d independent of the setting of this bit. note: if more than one flash component exists, th is field can only be set to '1' if both components support fast read. 19:17 read clock frequency: 000 = 20 mhz all other settings = reserved note: if more than one flash component exists, this field must be set to the lowest common frequency of the di fferent flash components. serial peripheral interface (spi) 766 intel ? ich8 family datasheet 20.2.2.2 flill?flash invalid instructions register (flash descriptor memory ma pped configuration registers) memory address:fcba + 004h size: 32 bits 16:06 reserved 5:3 component 2 density: this field identifies the size of the 2nd flash component. if there is not 2nd flash component, the contents of this field are undefined. valid bit settings: 000 = 512 kb 001 = 1 mb 010 = 2 mb 011 = 4 mb 100 = 8 mb 101 = 16 mb 111 = reserved 2:0 component 1 density: this field identifies the size of the 1st or only flash component. valid bit settings: 000 = 512 kb 001 = 1 mb 010 = 2 mb 011 = 4 mb 100 = 8 mb 101 = 16 mb 111 = reserved this field is defaulted to "101b" (16mb) after reset. in non-descriptor mode, only one flash component is supported and all access es to flash will be to this component. bits description bits description 31:24 invalid instruction 3: see de finition of invalid instruction 0 23:16 invalid instruction 2: see de finition of invalid instruction 0 15:8 invalid instruction 1: see defi nition of invalid instruction 0 7:0 invalid instruction 0: op-code for an invalid instruction in the that the flash controller should protect against instructions such as ch ip erase. this byte should be set to 0 if there are no invalid instructions to protect against for this field. op-codes programmed in the software sequencing opcode menu configuration and prefix-opcode configuration are not allowed to use any of the invalid instructions listed in this register. intel ? ich8 family datasheet 767 serial peripheral interface (spi) 20.2.3 flash descriptor region section the following section of the flash descriptor is used to identify the different flash regions flash regions: ? if a particular region is not using spi flash, the particular region should be disabled by setting the region base to all 1's, and the region limit to all 0's (base is higher than the limit) ? for each region except flreg0, the flas h controller must have a default region base of fffh and the region limit to 000h within the flash controller in case the number of regions specifies that a region is not used. 20.2.3.1 flreg0?flash region 0 (flash descriptor) register (flash descriptor memory ma pped configuration registers) memory address:frba + 000h size: 32 bits 20.2.3.2 flreg1?flash region 1 (bios) register (flash descriptor memory ma pped configuration registers) memory address:frba + 004h size: 32 bits bits description 31:29 reserved 28:16 region limit: this field specifies address bits 24:12 for the region limit. 15:13 reserved 12:0 region base: this specifies address bits 24:12 for the region base. bits description 31:29 reserved 28:16 region limit: this field specifie s address bits 24:12 for the region limit. 15:13 reserved 12:0 region base: this specifies address bits 24:12 for the region base. note: if the bios region is not used, the region base must be programmed to 1fffh and the region limit to 0000h to disable the region. serial peripheral interface (spi) 768 intel ? ich8 family datasheet 20.2.3.3 flreg2?flash region 2 (me) register (flash descriptor memory ma pped configuration registers) memory address:frba + 008h size: 32 bits 20.2.3.4 flreg3?flash region 3 (gbe) register (flash descriptor memory ma pped configuration registers) memory address:frba + 00ch size: 32 bits bits description 31:29 reserved 28:16 region limit: this field specifies address bits 24:12 for the region limit. 15:13 reserved 12:0 region base: this field specifies address bi ts 24:12 for the region base. note: if the bios region is not used, the re gion base must be programmed to 1fffh and the region limit to 0000h to disable the region. bits description 31:29 reserved 28:16 region limit: this field specifie s address bits 24:12 for the region limit. note: the maximum region limit is 128kb above the region base. 15:13 reserved 12:0 region base: this field specifie s address bits 24:12 for the region base. note: if the bios region is not used, the regi on base must be pr ogrammed to 1fffh and the region limit to 0000h to disable the region. intel ? ich8 family datasheet 769 serial peripheral interface (spi) 20.2.4 flash descriptor master section 20.2.4.1 flmstr1?flash master 1 (host processor/ bios) memory address:fmba + 000h size: 32 bits 20.2.4.2 flmstr2?flash master 2 (me) memory address:fmba + 004h size: 32 bits bits description 31:28 reserved, must be zero 27 gbe master region write access : if the bit is set, this master can erase and write that particular region th rough register accesses. 26 me master region write access : if the bit is set, this master can erase and write that particular region th rough register accesses. 25 host cpu/bios master region write access : if the bit is set, this master can erase and write that particular regi on through register accesses. bit 25 is a don?t care as the primary master always has read/write permissions to it?s primary region 24 flash descriptor master region write access : if the bit is set, this master can erase and write that particular re gion through register accesses. 23:20 reserved, must be zero 19 gbe master region read access : if the bit is set, this master can read that particular region thro ugh register accesses. 18 me master region read access : if the bit is set, this master can read that particular region through register accesses. 17 host cpu/bios master region read access : if the bit is set, this master can read that particular region th rough register accesses. bit 17 is a don?t care as the primary master always has read/write permissions to it?s primary region 16 flash descriptor master region read access : if the bit is set, this master can read that particular region th rough register accesses. 15:0 requester id : this is the requester id of the ho st cpu. this must be set to 0000h. bits description 31:28 reserved, must be zero 27 gbe master region write access : if the bit is set, this master can erase and write that particular region through register accesses. 26 me master region write access : if the bit is set, this master can erase and write that particular region through register accesses. bit 26 is a don?t care as the primary master always has read/write permissions to it?s primary region 25 host cpu/bios master region write access : if the bit is set, this master can erase and write that partic ular region through register accesses. 24 flash descriptor master region write access : if the bit is set, this master can erase and write that particular re gion through regi ster accesses. 23:20 reserved, must be zero serial peripheral interface (spi) 770 intel ? ich8 family datasheet 20.2.4.3 flmstr3?flash master 3 (gbe) memory address:fmba + 008h size: 32 bits 19 gbe master region read access : if the bit is set, this master can read that particular region through re gister accesses. 18 me master region read access : if the bit is set, this master can read that particular region through re gister accesses. bit 18 is a don?t care as the primary master always has read/write permissions to it?s primary region 17 host cpu/bios master region read access : if the bit is set, this master can read that particular region through register accesses. 16 flash descriptor master region read access : if the bit is set, this master can read that particular region through register accesses. 15:0 requester id : this is the requester id of th e me. this must be set to 0000h. bits description bits description 31:28 reserved, must be zero 27 gbe master region write access : if the bit is set, this master can erase and write that particular region through register accesses. bit 27 is a don?t care as the primary master always has read/write permissions to it?s primary region 26 me master region write access : if the bit is set, this master can erase and write that particular region through register accesses. 25 host cpu/bios master region write access : if the bit is set, this master can erase and write that partic ular region through register accesses. 24 flash descriptor master region write access : if the bit is set, this master can erase and write that particular re gion through regi ster accesses. 23:20 reserved, must be zero 19 gbe master region read access : if the bit is set, this master can read that particular region thro ugh register accesses. bit 19 is a don?t care as the primary master always has read/write permissions to it?s primary region 18 me master region read access : if the bit is set, this master can read that particular region through register accesses. 17 host cpu/bios master region read access : if the bit is set, this master can read that particular region through register accesses. 16 flash descriptor master region read access : if the bit is set, this master can read that particular region through register accesses. 15:0 requester id : this is the requester id of the gbe. this must be set to 0218h. intel ? ich8 family datasheet 771 serial peripheral interface (spi) 20.2.5 flash descriptor strap the following section of the flash descriptor is used to store strapping information. the default value represents the internal strap signal value that is used if there is no valid spi flash. 20.2.5.1 strp0?strap 0 register (flash descriptor memory ma pped configuration registers) memory address:fisba + 000h size: 32 bits bits default description 31:25 0000000b me smbus addr[6:0] (asd2): this field sets the 7-bit address for the intel amt smbus controller 2. 24 0 reserved 23 1 me smbus 2 select (mesm2sel): 0 = management engine smbus controller 2 is connected to the smbus pins 1 = management engine smbus controller 2 is connected to the smlink pins 22 0 spi cs1# or lan phy power control (spics1_lanphypc_sel) 0 = spi_cs1# is used for spi chip select 1 = spi_cs1# is used for lan phy power control function note: when configured as lan phy powe r control function bit 21=0 and bit 20=1 of the strap 0 register is an invalid configuration. the lan phy power control function configur es the ich8 signal used as an output. 21:20 00b gpio12 select (gpio12_sel) 00 = gpio12 01 = lan phy power control function (native output) 11 = glan_dock# (native input) 10 = invalid configuration note: when configured for lan phy power control function, bit 22 of the strap 0 register must be set to 0. the lan phy power control function configures the ich8 signal used as an output. 19 0 integrated gbe or pci expr ess select (glan_pcie_sel): 0 = pcie port 6 is used for pci express 1 = pcie port 6 is used for integrated glan note: if the gigabit platform lan connected device is not used, this bit may be set to 0. 18:16 0 reserved 15 0 bmc mode (bmcmode): this field is only valid when tcomode bit 7 is set to 1. 0 = not bmc mode. supports intel ? active management technology or asf. intel amt smbus controller 1 is connected to smbus. 1 = bmc mode. intel amt smbus cont roller 1 is connected to smlink. 14:8 0000000b me smbus addr[6:0] (asd): this field sets the 7- bit address for the intel amt smbus controller 1. serial peripheral interface (spi) 772 intel ? ich8 family datasheet notes: ich8m supports 3 tco modes. 1. legacy tco mode: selection through strap0 bit 7 2. advanced tco pro-active mode: selection through strap0 bit 7 and bit15=0 3. advanced tco bmc mode: selection through strap0 bit 7 and bit15=1 20.2.5.2 strp1?strap 1 register (flash descriptor memory ma pped configuration registers) memory address:fmsba + 000h size: 32 bits 7 0 tco mode (tcomode): this field configures the location of the tco slave and also enables/disables the intel amt smbus controller 1. 0 = legacy/compatible mode: in this mode the tco slave is multiplexed onto the smlink pins. the intel am t smbus controller 1 is disabled. 1 = advanced tco mode: in this mode the tco slave is multiplexed onto the smbus pins. the intel amt smbus controller 1 is enabled. the intel amt smbus controller 1 configur ation is set by bmcmode bit 15. the value of this strap is reflected in bit 1 of the smbus auxiliary status ( section 16.2.11 : aux_sts ? auxiliary status register (smbus: d31:f3: smbase + 0ch, bit 1). 6:1 0 reserved 0 1 me disable (me_disable): 0 = me is enabled 1 = me is disabled note: this bit and bit 0 of section 20.2.5.2 (fmsba+000h) must be set to 1 to disable management engine on the platform. bits default description bits default description 31:1 0 reserved 0 1 me disable b(mdb): 0 = me is enabled 1 = me is disabled note: this bit and bit 0 of section 20.2.5.1 (fmsba+000h) must be set to 1 in order to disable me on the platform. intel ? ich8 family datasheet 773 serial peripheral interface (spi) 20.2.5.3 flumap1?flash upper map 1 memory address:efch attribute: default value: 00ffh size: 32 bits note: if vtl and vtba values are ff then firmware will assume there are no entries in vscc table. 20.2.5.4 jid0?jedec-id 0 register memory address:vtba + 000h attribute: default value: size: 32 bits 20.2.5.5 vscc0?vendor specific component capabilities 0 memory address:vtba + 004h attribute: default value: size: 32 bits bits default description 31:16 0 reserved 15:8 1 vscc table length (vtl) : identifies the 1?s based number of dwords contained in the vscc table. each sp i component entry in the table is 2 dwords long. 7:0 1 vscc table base address (vtba) : this identifies address bits [11:4] for the vscc table portion of the flash desc riptor. bits [24:12] and bits [3:0] are 0. bits description 31:24 reserved 23:16 spi component device id 1 : this identifies the second by te of the device id of the spi flash component. this is the third byte returned by the read jedec-id command (opcode 9fh). 15:8 spi component device id 0: this identifies the first byte of the de vice id of the spi flash component. this is the second byte returned by the re ad jedec-id command (opcode 9fh). 7:0 spi component vendor id: this identifies the one byte vendor id of the spi flash component. this is the first byte return ed by the read jedec-id command (opcode 9fh). bits description 31:17 reserved 17 write enable on write to status (wews) : 0 = no write enable (06h) command is requ ired to write to the status register 1 = write enable (06h) is requ ired to the write status register prior to write and erase to remove any protection. note: if there is more than one component, both components must use the same write enable on to write to the stat us register on the spi flash. serial peripheral interface (spi) 774 intel ? ich8 family datasheet 20.2.5.6 jid0?jedec-id n register memory address:vtba + (n*8)h attribute: default value: size: 32 bits 15:8 erase opcode (eo): this register is programed with the flash erase instruction opcode required by this vendors flash component. note: if there is more than one component, both components must use the same erase opcode. 7:4 reserved 3 write status required (wsr): 0 = no enable write to the status register ( 50h) opcode is required to write to the spi flash status register(s) prior to write or erase to remove spi flash protection. 1 = enable write to the status register (50h) opcode is required to write to the spi flash status register(s) prior to write or erase to remove spi flash protection. note: if there is more than one co mponent, both components must use the same write status required setting. spi protection is removed by writing 00h to spi flash status register(s). 2 write granularity (wg): 0 = 1 byte 1 = 64 byte all other settings: reserved note: if more than one flash comp onent exists, this field must be set to the lowest common write granularity of th e different flash components. 1:0 block/sector erase size (bes) : this field identifies the er asable sector size for all flash components. valid bit settings: 00 = 256 byte 01 = 4 kb 10 = reserved for future use 11 = 64kb note: if supporting more than on e flash component, all flas h components must have identical block/ sector erase sizes. bits description bits description 31:24 reserved 23:16 spi component device id 1 : this identifies the second by te of the device id of the spi flash component. this is the third byte returned by the re ad jedec-id command (opcode 9fh). 15:8 spi component device id 0: this identifies the first byte of the device id of the spi flash component. this is the second byte returned by the read jedec-id command (opcode 9fh). 7:0 spi component vendor id: this identifies the one byte vendor id of the spi flash component. this is the first byte return ed by the read jedec-id command (opcode 9fh). intel ? ich8 family datasheet 775 serial peripheral interface (spi) 20.2.5.7 vscc0n?vendor specif ic component capabilities n memory address:vtba + 004h + (n*8) attribute: default value: size: 32 bits note: ?n? is an integer denoting the number of table entries. bits description 31:17 reserved 16 write enable on write status (wews) : 0 = no write enable (06h) opcode is required to write to the spi flash status register(s). 1 = write enable (06h) opcode is required to writ e to the spi flash status register(s) prior to write and erase to remove spi flash protection. note: if there is more than one component, both components must use the same write enable on to write to the stat us register on the spi flash. 15:8 erase opcode (eo): this register is programed with the flash erase instruction opcode required by this vendors flash component. note: if there is more than one component, both components must use the same erase opcode. 7:4 reserved 3 write status required (wsr): 0 = no requirement to write to the write status register prior to a write 1 = enable status register write (50h) command is required to write to the write status register note: if there is more than one component, both components must use the same write status required. uses 50h to enable a write to the write status register 2 write granularity (wg): 0 = 1 byte 1 = 64 byte all other settings = reserved note: if more than one flash comp onent exists, this field must be set to the lowest common write granularity of th e different flash components. 1:0 block/sector erase size (bes) : this field identifies the er asable sector size for all flash components. valid bit settings: 00 = 256 byte 01 = 4 kb 10 = reserved for future use 11 = 64 kb note: if supporting more than on e flash component, all flas h components must have identical block/ sector erase sizes. serial peripheral interface (spi) 776 intel ? ich8 family datasheet 20.2.5.8 oem section memory address:f00h attribute: default value: size: 256 bytes 256 bytes are reserved at the top of th e flash descriptor for use by oem. the information stored by the oem can only be written during the manufacturing process as the flash descriptor read/write permissions must be set to read only when the computer leaves the manufacturing floor. the ich flash controller does not read this information. ffh is suggested to reduce programming time. 20.3 gbe spi flash program registers the gbe flash registers are memory-mapped with a base address glbar found in the gbe lan register chapter device 25: function 0: offset 18h. (mbarc register). the individual registers are then accessibl e at glbar + offset as indicated in table 144 . these memory-mapped registers must be acce ssed in byte, word, or dword quantities. table 144. gigabit lan spi flash program register address map (gbe lan memory mapped configuration registers) glbar + offset mnemonic register name default access 00h?03h glfpr gigabit lan flash primary region 00000000h ro 04h?05h hsfs hardware sequencing flash status 0000h ro, r/w, r/wl 06h?07h hsfc hardware sequencing flash control 0000h r/w, r/ws 08h?0bh faddr flash address 00000000h r/w 0ch?0fh ? reserved 00000000h ? 10h?13h fdata0 flash data 0 00000000h r/w 14h?4fh ?d reserved 00000000h ? 50h?53h fracc flash region access permissions 00000000h ro, r/wl 54h?57h freg0 flash region 0 00000000h ro 58h?5bh freg1 flash region 1 00000000h ro 5ch?5f freg2 flash region 2 00000000h ro 60h?63h freg3 flash region 3 00000000h ro 64h?73h ? reserved for future flash regions ? ? 74h?77h fpr0 flash protected range 0 00000000h r/wl 78h?7bh fpr1 flash protected range 1 00000000h r/wl 7ch?8fh reserved reserved 90h ssfs software sequencing flash status 0000h ro, r/wc 91h?93h ssfc software sequencing flash control 0000h r/w 94h?95h preop prefix opcode configuration 0000h r/wl 96h?97h optype opcode type configuration 0000h r/w 98h?9fh opmenu opcode menu configuration 00000000h r/w a0h?dfh ? reserved ? ? intel ? ich8 family datasheet 777 serial peripheral interface (spi) 20.3.1 glfpr?gigabit lan flas h primary region register ( gbe lan memory mapped configuration registers ) memory address:glbar + 00h attribute: ro default value: 00000000h size: 32 bits bit description 31:29 reserved 28:16 gbe flash primary re gion limit (prl):? ro. this field specifies address bits 24:12 for the primary region limit. the value in this register loaded from the contents in the flash descriptor.flreg 3.region limit 15:13 reserved 12:0 gbe flash primary re gion base (prb) ? ro. this field specif ies address bits 24:12 for the primary region base the value in this register is load ed from the contents in the flash descriptor.flreg3.region base serial peripheral interface (spi) 778 intel ? ich8 family datasheet 20.3.2 hsfs?hardware sequenci ng flash status register ( gbe lan memory mapped configuration registers ) memory address:glbar + 04h attribute: ro, r/wc, r/wl default value: 0000h size: 16 bits bit description 15 flash configuration lock-down (flockdn) ? r/w/l. when set to 1, those flash program registers that are locked down by this flockdn bit cannot be written. once set to 1, this bit can only be cleared by a hardware reset. hardware reset is initiated by one of the fo llowing resets: ? global reset (when the host and the me partitio ns are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. 14 flash descriptor valid (fdv)? ro. this bit is set to a 1 if the flash controller read the correct flash de scriptor signature. if the flash descriptor valid bit is not 1, software ca nnot use the hardware sequencing registers, but must use the software sequencing registers. any attempt to use the hardware sequencing registers will result in the fcerr bit being set. 13 flash descriptor override pin strap status (fdopss)? ro. this bit reflects the value the flash descriptor override pin-strap. 1 = no override 0 = the flash descriptor override strap is set 12:6 reserved 5 spi cycle in progress (scip)? ro. hardware sets this bi t when software sets the flash cycle go (fgo) bit in the hardware se quencing flash contro l register. this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can dete rmine when read data is valid and/or when it is safe to begin progra mming the next command. soft ware must only program the next command when this bit is 0. 4:3 block/sector eras e size (berase) ? ro. this field identifies the erasable sector size for all flash components. valid bit settings: 00 = 256 byte 01 = 4 kb 10 = reserved for future use 11 = 64 kb 2 access error log (ael) ? r/w/c. hardware sets this bit to a 1 when an attempt was made to access the bios regi on using the direct access method or an access to the bios program registers that violated the security restrictions. this bit is simply a log of an access security violat ion. this bit is cleared by software writing a 1. intel ? ich8 family datasheet 779 serial peripheral interface (spi) 20.3.3 hsfc?hardware sequencing flash control register ( gbe lan memory mapped configuration registers ) memory address:glbar + 06h attribute: r/w, r/ws default value: 0000h size: 16 bits 1 flash cycle error (fcerr) ? r/w/c. hardware sets this bit to 1 when an program register access is blocked to the flash due to one of the protection policies or when any of the programmed cycle registers is wr itten while a programmed access is already in progress. this bit remains asserted until cleared by so ftware writing a 1 or until hardware reset occurs. software must clear this bit before setting the flash cycle go bit in this register. hardware reset is initiated by one of the following resets: ? global reset (when the host and the me partitions are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. 0 flash cycle done (fdone) ? r/w/c. the ich8 sets this bit to 1 when the spi cycle completes after software previously set the fgo bit. this bit re mains asserted until cleared by software writing a 1 or hardware reset. when this bit is set and the spi smi# enable bit is set, an in ternal signal is asserted to the smi# generation block. software must make sure this bit is cleared prior to enabli ng the spi smi# assertion for a new programmed access. hardware reset is initiated by one of the following resets: ? global reset (when the host and the me partitions are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. bit description bit description 15:10 reserved 9:8 flash data byte count (fdbc): ? r/w. this field specifies the number of bytes to shift in or out during the data portion of the spi cycle. the content?s of this register are 0?s based with 0b representing 1 byte and 11b representing 4 bytes. the number of bytes transferred is the valu e of this field plus 1. this field is ignored for the block erase command. serial peripheral interface (spi) 780 intel ? ich8 family datasheet 20.3.4 faddr?flash address register ( gbe lan memory mapped configuration registers ) memory address:glbar + 08h attribute: r/w default value: 00000000h size: 32 bits 20.3.5 fdata0?flash data 0 register ( gbe lan memory mapped configuration registers ) memory address:glbar + 10h attribute: r/w default value: 00000000h size: 32 bits 7:3 reserved 2:1 flash cycle (fcycle) . ? r/w. this field defines the flash spi cycle type generated to the flash when the fgo bit is set as defined below: 00 = read (1 up to 4 bytes by setting fdbc) 01 = reserved 10 = write (1 up to 4 bytes by setting fdbc) 11 = block erase 0 flash cycle go (fgo): ? r/w/s. a write to this register with a ?1? in this bit initiates a request to the flash spi arbiter to start a cy cle. this register is cleared by hardware when the cycle is granted by the spi arbiter to run the cycle on the spi bus. when the cycle is complete, the fdone bit is set. software is forbidden to write to any regist er in the hsflctl register between the fgo bit getting set and the fdone bi t being cleared. any attempt to violate this rule will be ignored by hardware. hardware allows other bits in this register to be progra mmed for the same transaction when writing this bit to 1. this saves an additional memory write. this bit always returns 0 on reads. bit description bit description 31:25 reserved 24:0 flash linear address (fla): ? r/w. the fla is the starting byte linear address of a spi read or write cycle or an address with in a block for the bloc k erase command. the flash linear address must fall within a region for which bi os has access permissions. bit description 31:0 flash data 0 (fd0): ? r/w. this field is shifted ou t as the spi data on the master- out slave-in data pin during the data portion of the spi cycle. this register also shifts in the data from th e master-in slave-out pin into this register during the data portion of the spi cycle. the data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant by te, msb to lsb, etc. specifically, the shift order on spi in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-?8-23-22-?16-31?24 bit 24 is the last bit shifted out/in. there are no alignment assumptions; byte 0 always represents the value specified by the cycle address. note that the data in this register may be modified by the hardware during any programmed spi transaction. direct memory reads do not modify the contents of this register. intel ? ich8 family datasheet 781 serial peripheral interface (spi) 20.3.6 frap?flash regions acce ss permissions register ( gbe lan memory mapped configuration registers ) memory address:glbar + 50h attribute: ro, r/wl default value: 00000808h size: 32 bits bit description 31:28 reserved 27:25 gbe master write access grant (gmwag) : ? r/wl. each bit [27:25] corresponds to master[3:1]. gbe can grant one or more masters write access to the gbe region 3 overriding the permissions in the flash descriptor. master[1] is host cpu/bios, master[2] is me, master[3] is host cpu/gbe. the contents of this register are locked by the flockdn bit. 24:20 reserved 19:17 gbe master read access grant (gmrag) : ? r/wl. each bit [19:17] corresponds to master[3:1]. gbe can grant one or more ma sters read access to the gbe region 3 overriding the read permissi ons in the flash descriptor. master[1] is host cpu/bios, master[2] is me, master[3] is gbe. the contents of this register are locked by the flockdn bit. 16:12 reserved 11:8 gbe region write access (grwa) : ? ro. each bit [11:8] corresponds to regions [3:0]. if the bit is set, this master can er ase and write that part icular region through register accesses. the contents of this register are that of the flash descri ptor. flash master 3.master region write access or a particular master has granted gbe write permissions in their master write access grant register or the fl ash descriptor security override strap is set. 7:4 reserved 3:0 gbe region read access (grra) : ? ro. each bit [3:0] corresponds to regions [3:0]. if the bit is set, this master can re ad that particular re gion through register accesses. the contents of this register are that of the flash descri ptor. flash master 3.master region write access or a particular master has grante d gbe read permissions in their master read access grant register. serial peripheral interface (spi) 782 intel ? ich8 family datasheet 20.3.7 freg0?flash region 0 (f lash descriptor) register ( gbe lan memory mapped configuration registers ) memory address:glbar + 54h attribute: ro default value: 00000000h size: 32 bits 20.3.8 freg1?flash region 1 (bios descriptor) register ( gbe lan memory mapped configuration registers ) memory address:glbar + 58h attribute: ro default value: 00000000h size: 32 bits bit description 31:29 reserved 28:16 region limit (rl): ? ro. this field specifies addres s bits 24:12 for the region 0 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 0.region limit. 15:13 reserved 12:0 region base (rb): ? ro. this field specifies addr ess bits 24:12 for the region 0 base. the value in this register is load ed from the contents in the flash descriptor.flreg0.region base. bit description 31:29 reserved 28:16 region limit (rl): ? ro. this field specifies addres s bits 24:12 for the region 1 limit. the value in this register is load ed from the contents in the flash descriptor.flreg1.region limit 15:13 reserved 12:0 region base (rb): ? ro. this field specifies addr ess bits 24:12 for the region 1 base. the value in this register is load ed from the contents in the flash descriptor.flreg1.region base. intel ? ich8 family datasheet 783 serial peripheral interface (spi) 20.3.9 freg2?flash regi on 2 (me) register ( gbe lan memory mapped configuration registers ) memory address:glbar + 5ch attribute: ro default value: 00000000h size: 32 bits 20.3.10 freg3?flash regi on 3 (gbe) register ( gbe lan memory mapped configuration registers ) memory address:glbar + 60h attribute: ro default value: 00000000h size: 32 bits bit description 31:29 reserved 28:16 region limit (rl): ? ro. this field specifies addre ss bits 24:12 for the region 2 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 2.region limit. 15:13 reserved 12:0 region base (rb): ? ro. this field specifies addr ess bits 24:12 for the region 2 base. the value in this register is load ed from the contents in the flash descriptor.flreg2.region base. bit description 31:29 reserved 28:16 region limit (rl): ? ro. this field specifies addre ss bits 24:12 for the region 3 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 3.region limit 15:13 reserved 12:0 region base (rb): ? ro. this field specifies addr ess bits 24:12 for the region 3 base. the value in this register is load ed from the contents in the flash descriptor.flreg3.region base. serial peripheral interface (spi) 784 intel ? ich8 family datasheet 20.3.11 pr0?protected range 0 register ( gbe lan memory mapped configuration registers ) memory address:glbar + 74h attribute: r/wl default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. 20.3.12 pr1?protected range 1 register ( gbe lan memory mapped configuration registers ) memory address:glbar + 78h attribute: r/wl default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31 write protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and th at writes and erases directed to addresses between them (inclusive) must be blocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fiel ds are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range. bit description 31 write protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and th at writes and erases directed to addresses between them (inclusive) must be blocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable: ? r/wl. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fiel ds are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base: ? r/wl. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range. intel ? ich8 family datasheet 785 serial peripheral interface (spi) 20.3.13 ssfs?software sequenci ng flash status register ( gbe lan memory mapped configuration registers ) memory address:glbar + 90h attribute: ro, r/wc default value: 00h size: 8 bits note: the software sequencing control and status registers are reserved if the hardware sequencing control and status registers are used. bit description 7:5 reserved 4 access error log (ael): ? ro. this bit reflects the value of the hardware sequencing status ael register. 3 flash cycle error (fcerr): ? r/wc. hardware sets this bit to 1 when a programmed access is blocked from running on the spi inte rface due to one of the protection policies or when any of the programme d cycle registers is written while a programmed access is already in progress. this bit remains asserted until cleared by software writing a 1 or hardware reset. hardware reset is initiated by one of the following resets: ? global reset (when the host and the me partitions are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. 2 cycle done status: ? r/wc. the ich8 sets this bit to 1 when the spi cycle completes (i.e., scip bit is 0) after software sets the go bit. this bit remains asserted until cleared by software writing a 1 or hardware reset. when this bit is set and the spi smi# enable bit is set, an in ternal signal is asserted to the smi# generation block. software must make sure this bit is cleared prior to enabli ng the spi smi# assertion for a new programmed access. hardware reset is initiated by one of the following resets: ? global reset (when the host and the me partitions are both reset) - on both me-enabled and non-me systems. ? host partition reset (any time pltrst# is asserted either from a cold or a warm reset) - only on me enabled systems. 1 reserved 0 spi cycle in progress (scip): ? ro. hardware sets this bit when software sets the spi cycle go bit in the command register. this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. software must only program the next command when this bit is 0. serial peripheral interface (spi) 786 intel ? ich8 family datasheet 20.3.14 ssfc?software sequenci ng flash control register ( gbe lan memory mapped configuration registers ) memory address:glbar + 91h attribute: r/w default value: 000000h size: 24 bits bit description 23:19 reserved 18:16 spi cycle frequency (scf): ? r/w. 000 = 20 mhz 001 = 33 mhz all other values reserved software should program this register to se t the frequency of the cycle that is to be run. 15 reserved 14 data cycle (ds): ? r/w. when set to 1, there is data that corresponds to this transaction. when 0, no data is delivered for this cycle, and the dbc and data fields themselves are do not cares 13:8 data byte count (dbc): ? r/w. this field specifies the number of bytes to shift in or out during the data portion of the spi cycl e. the valid settings (in decimal) are any value from 0 to 3. the number of bytes transf erred is the value of this field plus 1. note that when this field is 00b, then there is 1 byte to transfer and that 11b means there are 4 bytes to transfer. 7 reserved 6:4 cycle opcode pointer (cop): ? r/w. this field selects one of the programmed opcodes in the opcode menu to be used as the spi command/opcode. in the case of an atomic cycle sequence, this determines the second command. 3 sequence prefix opcode pointer (spop): ? r/w. this field selects one of the two programmed prefix opcodes for use when performing an atomic cycle sequence. a value of 0 points to the opcode in the least significant byte of the prefix opcodes register. by making this programmable, th e ich8 supports flash devices that have different opcodes for enabling writes to the data space vs. status register. 2 atomic cycle sequence (acs): ? r/w. when set to 1 along with the scgo assertion, the ich8 will execute a sequence of commands on the spi interface without allowing the lan component to arbitrate and interleave cycles. the sequence is composed of: ? atomic sequence prefix command (8-bit opcode only) ? primary command specified below by so ftware (can include address and data) ? polling the flash status register (opcode 05h) until bit 0 becomes 0b. the spi cycle in progress bit remains set an d the cycle done status bit remains unset until the busy bit in the flas h status register returns 0. 1 spi cycle go (scgo): ? r/ws. this bit always returns 0 on reads. however, a write to this register with a 1 in this bit starts the spi cycle defined by the other bits of this register. the ?spi cycle in progress? (scip) bit gets set by this action. hardware must ignore writes to this bit while the cycle in progress bit is set. hardware allows other bits in this register to be progra mmed for the same transaction when writing this bit to 1. this saves an additional memory write. 0 reserved intel ? ich8 family datasheet 787 serial peripheral interface (spi) 20.3.15 preop?prefix opcode configuration register ( gbe lan memory mapped configuration registers ) memory address:glbar + 94h attribute: r/wl default value: 0000h size: 16 bits note: this register is not writable when the spi configuration lock-down bit (glbar + 00h:15) is set. 20.3.16 optype?opcode type configuration register ( gbe lan memory mapped configuration registers ) memory address:glbar + 96h attribute: r/w default value: 0000h size: 16 bits entries in this register correspond to the entries in the opcode menu configuration register. note: the definition below only provides write protection for opcodes that have addresses associated with them. therefore, any erase or write opcodes that do not use an address should be avoided (for example, ?chip erase? and ?auto-address increment byte program?). note: this register is not writable when the spi configuration lock-down bit (glbar + 00h:15) is set. bit description 15:8 prefix opcode 1 ? r/wl. software programs an spi opco de into this field that is permitted to run as the first comm and in an atomic cycle sequence. 7:0 prefix opcode 0 ? r/w. software programs an spi opco de into this field that is permitted to run as the first comm and in an atomic cycle sequence. bit description 15:14 opcode type 7 ? r/w. see the descriptio n for bits 1:0 13:12 opcode type 6 ? r/w. see the descriptio n for bits 1:0 11:10 opcode type 5 ? r/w. see the descriptio n for bits 1:0 9:8 opcode type 4 ? r/w. see the descriptio n for bits 1:0 7:6 opcode type 3 ? r/w. see the descriptio n for bits 1:0 5:4 opcode type 2 ? r/w. see the descriptio n for bits 1:0 3:2 opcode type 1 ? r/w. see the descriptio n for bits 1:0 1:0 opcode type 0 ? r/w. this field specifies informat ion about the corresponding opcode 0. this information allows the hardwa re to 1) know whether to use the address field and 2) provide bios and shared flash pr otection capabilities. the encoding of the two bits is: 00 = no address associated with this opcode; read cycle type 01 = no address associated with this opcode; write cycle type 10 = address required; read cycle type 11 = address required; write cycle type serial peripheral interface (spi) 788 intel ? ich8 family datasheet 20.3.17 opmenu?opcode menu configuration register ( gbe lan memory mapped configuration registers ) memory address:glbar + 98h attribute: r/w default value: 0000000000000000h size: 64 bits eight entries are available in this register to give gbe a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. this keeps the hardware flexible enough to operate with a wide variety of spi devices. note: it is recommended that gbe avoid programm ing write enable opcodes in this menu. malicious software could then perform writes and erases to the spi flash without using the atomic cycle mechanism. this could cause functional failures in a shared flash environment. write enable opcodes should on ly be programmed in the prefix opcodes. this register is not writable when the spi configuration lock-down bit (glbar + 00h:15) is set. bit description 63:56 allowable opcode 7 ? r/w. see the description for bits 7:0 55:48 allowable opcode 6 ? r/w. see the description for bits 7:0 47:40 allowable opcode 5 ? r/w. see the description for bits 7:0 39:32 allowable opcode 4 ? r/w. see the description for bits 7:0 31:24 allowable opcode 3 ? r/w. see the description for bits 7:0 23:16 allowable opcode 2 ? r/w. see the description for bits 7:0 15:8 allowable opcode 1 ? r/w. see the description for bits 7:0 7:0 allowable opcode 0 ? r/w. software programs an spi opcode into this field for use when initiating spi commands through the control register. intel ? ich8 family datasheet 789 thermal sensor registers (d31:f6) 21 thermal sensor registers (d31:f6) 21.1 pci bus configuration registers table 145. thermal sensor register address map (d31:f6) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification 284fh ro 04h?05h cmd command 0000h r/w, ro 06h?07h sts device status 0010h r/wc, ro 08h rid revision id 00h ro 09h pi programming interface 00h ro 0ah scc sub class code 80h ro 0bh bcc base class code 11h ro 0ch cls cache line size 00h ro 0dh lt latency timer 00h ro 0eh htype header type 00h ro 0fh bist built-in self test 00h ro 10h?13h tbar thermal base address (memory) 00000004h r/w, ro 14h?17h tbarh thermal base address high dword 00000000h ro 2ch?2dh svid subsystem vendor identifier 0000h r/wo 2eh?2fh sid subsystem identifier 0000h r/wo 34h cap_ptr capabilities pointer 50h ro 3ch intln interrupt line 00h r/w 3dh intpn interrupt pin 03h ro 40h?43h tbarb bios assigned thermal base address 00000004h r/w, ro 44h?47h tbarbh bios assigned ba high dword 00000000h r/w 50h?51h pid power management identifiers 0001h ro 52h?53h pc power management capabilities 0022h ro 54h?57h pcs power management control and status 0000h r/w, ro thermal sensor registers (d31:f6) 790 intel ? ich8 family datasheet 21.1.1 vid?vendor identification offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bit lockable: no power well: core 21.1.2 did?device identification offset address: 02h ? 03h attribute: ro default value: 284fh size: 16 bit 21.1.3 cmd?command address offset: 04h ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value as signed to intel. intel vid = 8086h bit description 15:0 device id (did) ? ro. this field indicates the de vice number assign ed by the sig. bit description 15:11 reserved 10 interrupt disable (id) ? r/w. this bit enables the device to assert an intx#. when set, the thermal logic?s intx# signal will be de-asserted. when cleared, the intx# signal may be asserted. 9 fbe (fast back to back enable) ? ro. not implemented. hardwired to 0. 8 sen (serr enable) ? ro. not implemented. hardwired to 0. 7 wcc (wait cycle control) ? ro. not implemented. hardwired to 0. 6 per (parity error response) ? ro. not implemented. hardwired to 0. 5 vps (vga palette snoop) ? ro. not implemented. hardwired to 0. 4 mwi (memory write and invalidate enable) ? ro. not implemented. hardwired to 0. 3 sce (special cycle enable) ? ro. not implemented. hardwired to 0. 2 bme (bus master enable) ? ro. not implemented. hardwired to 0. 1 memory space enable (mse) ? r/w. when set, enables memory space accesses to the thermal registers. 0 ios (i/o space) ? ro. the thermal logic does not implement i/o space; therefore, this bit is hardwired to 0. intel ? ich8 family datasheet 791 thermal sensor registers (d31:f6) 21.1.4 sts?status address offset: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits 21.1.5 rid?revision identification address offset: 08h attribute: ro default value: 00h size: 8 bits 21.1.6 pi? progra mming interface address offset: 09h attribute: ro default value: 00h size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. software clears this bit by writing a 1 to this bit location. 0 = parity did not occur. 1 = parity error occurs on the internal interface for this function, regard less of the setting of bit 6 in the command register. 14 serr# status (serrs) ? ro. not implemented. hardwired to 0. 13 received master abort (rma) ? ro. not implemented. hardwired to 0. 12 received target abort (rta) ? ro. not implemented. hardwired to 0. 11 signaled target-abort (sta) ? ro. not implemented. hardwired to 0. 10:9 devsel# timing status (devt) ? ro. does not apply. hardwired to 0. 8 master data parity error (mdpe) ? ro. not implemented. hardwired to 0. 7 fast back to back capable (fbc) ? ro. does not apply. hardwired to 0. 6 reserved 5 66 mhz capable (c66) ? ro. does not apply. hardwired to 0. 4 capabilities list exists (clist) ? ro. this bit indicates that the controller contains a capabilities pointer list. the first item is pointed to by l ooking at configuration offset 34h. 3 interrupt status (is) ? ro. this bit reflects the stat e of the intx# signal at the input of the enable/disable circuit. this bit is a 1 when the intx# is asserted. this bit is a 0 after the interrupt is cleared (independent of the state of the interrupt disable bit in the command register). 2:0 reserved bit description 7:0 revision id (rid) ? ro. this field indica tes the device specific revision identifier. bit description 7:0 programming interface (pi) ? ro. ich8 thermal logic has no standard programming interface. thermal sensor registers (d31:f6) 792 intel ? ich8 family datasheet 21.1.7 scc?sub class code address offset: 0ah attribute: ro default value: 80h size: 8 bits 21.1.8 bcc?base class code address offset: 0bh attribute: ro default value: 11h size: 8 bits 21.1.9 cls?cache line size address offset: 0ch attribute: ro default value: 00h size: 8 bits 21.1.10 lt?latency timer address offset: 0dh attribute: ro default value: 00h size: 8 bits 21.1.11 htype?header type address offset: 0eh attribute: ro default value: 00h size: 8 bits bit description 7:0 sub class code (scc) ? ro. value assigned to ich8 thermal logic. bit description 7:0 base class code (bcc) ? ro. value assigned to ich8 thermal logic. bit description 7:0 cache line size (cls) ? ro. does not apply to pci bus target-only devices. bit description 7:0 latency timer (lt) ? ro. does not apply to pci bus target-only devices. bit description 7 multi-function device (mfd) ? ro. this bit is 0 becaus e a multi-function device only needs to be marked as such in functi on 0, and the thermal registers are not in function 0. 6:0 header type (htype) ? ro. implements type 0 configuration header. intel ? ich8 family datasheet 793 thermal sensor registers (d31:f6) 21.1.12 bist?built-in self test address offset: 0fh attribute: ro default value: 00h size: 8 bits 21.1.13 tbar?thermal base address offset: 10h ? 13h attribute: r/w, ro default value: 00000004h size: 32 bits this bar creates 4 kb of memory space to signify the base address of thermal memory mapped configuration registers. this memory space is active when the command (cmd) register memory space enable (mse) bit is set and either tbar[31:12] or tbarh are programmed to a non-zero address. this bar is programmed by the operating system, and allows the os to locate the thermal registers in system memory space. 21.1.14 tbarh?thermal base high dword address offset: 14h ? 17h attribute: r/w,ro default value: 00000000h size: 32 bits this bar extension holds the high 32 bits of the 64 bit tbar. in conjunction with tbar, it creates 4 kb of memory space to sign ify the base address of thermal memory mapped configuration registers. bit description 7:0 built-in self test (bist) ? ro. not implemented. hardwired to 00h. bit description 31:12 thermal base address (tba) ? r/w. this field provides the base a ddress for the thermal logic memory mapped configuratio n registers; 4 kb are requested by hardwiring bits 11:4 to 0s. 11:4 reserved 3 prefetchable (pref) ? ro. this bit indicates that this bar is not pre-fetchable. 2:1 address range (addrng) ? ro. this field indicates th at this bar can be located anywhere in 64 bit address space. 0 space type (sptyp) ? ro. this bit indicates that this bar is located in memory space. bit description 31:0 thermal base address high (tbah) ? r/w. tbar bits 61:32. thermal sensor registers (d31:f6) 794 intel ? ich8 family datasheet 21.1.15 svid?subsystem vendor id address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits this register should be implemented for any function that could be instantiated more than once in a given system,. the svid register, in combination with the subsystem id register, enables the operating environment to distinguish one subsystem from the other(s). software (bios) will write the value to this register. after that, the value can be read, but writes to the register will have no ef fect. the write to this register should be combined with the write to the sid to create one 32-bit write. this register is not affected by d3 hot to d0 reset. 21.1.16 sid?subsystem id address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits this register should be implemented for any function that could be instantiated more than once in a given system,. the sid register, in combination with the subsystem vendor id register, make it possible for th e operating environment to distinguish one subsystem from the other(s). software (bios) will write the value to this register. then, the value can be read, but writes to the register will have no effect. th e write to this register should be combined with the write to the svid to create one 32-b it write. this register is not affected by d3 hot to d0 reset. 21.1.17 cap_ptr ?cap abilities pointer address offset: 34h attribute: ro default value: 50h size: 8 bits 21.1.18 intln?interrupt line address offset: 3ch attribute: r/w default value: 00h size: 8 bits bit description 15:0 svid (svid) ? r/wo. these r/wo bits have no ich8 functionality. bit description 15:0 sid (sid) ? r/wo. these r/wo bits have no ich8 functionality. bit description 7:0 capability pointer (cp) ? ro. this field indicates that th e first capability pointer offset is offset 50h (power management capability). bit description 7:0 interrupt line ? r/w. the ich8 hardware does not us e this field directly. it is used to communicate to software the interrupt li ne that the interrupt pin is connected to. intel ? ich8 family datasheet 795 thermal sensor registers (d31:f6) 21.1.19 intpn?interrupt pin address offset: 3dh attribute: ro default value: 03h size: 8 bits 21.1.20 tbarb?bios assigned thermal base address address offset: 40h ? 43h attribute: r/w,ro default value: 00000004h size: 32 bits this bar creates 4 kb of memory space to signify the base address of thermal memory-mapped configuration registers. this memory space is active when tbarb.sptypen is asserted. this bar is pr ogrammed by bios, and allows bios to locate the thermal registers in system me mory space. if both tbar and tbarb are programmed, then the os and bios each ha ve their own independent ?view? of the thermal registers, and must use the tsiu, tciu, and tbiu registers to denote thermal registers ownership/availability. 21.1.21 tbarbh?bios assigned thermal base high dword address offset: 44h ? 47h attribute: r/w default value: 00000000h size: 32 bits this bar extension holds the high 32 bits of the 64 bit tbarb. bit description 7:4 reserved 3:0 interrupt pin ? ro. this field reflects the value of tbd.zip in chipset configuration space. bit description 31:12 thermal base address (tba) ? r/w. this field provides th e base address for the thermal logic memory-mapped configuratio n registers; 4 kb are requested by hardwiring bits 11:4 to 0s. 11:4 reserved 3 prefetchable (pref) ? ro. this bit indicates that this bar is not pre-fetchable. 2:1 address range (addrng) ? ro. this field indicates th at this bar can be located anywhere in 64 bit address space. 0 space type enable (sptypen) ? r/w. when set to 1b by software, enables the decode of this memory bar. 0 = disable 1 = enable bit description 31:0 thermal base address high (tbah) ? r/w. this field provides tbar bits 61:32. thermal sensor registers (d31:f6) 796 intel ? ich8 family datasheet 21.1.22 pid?pci power mana gement capability id address offset: 50h ? 51h attribute: ro default value: 0001h size: 16 bits 21.1.23 pc?power management capabilities address offset: 52h ? 53h attribute: ro default value: 0022h size: 16 bits bit description 15:8 next capability (next) ? ro. this field indicates that this is the last capability structure in the list. 7:0 cap id (cap) ? ro. this field indicates that this po inter is a pci power management capability. bit description 15:11 pme_support ? ro. indicates pme# is not supported 10 d2_support ? ro. the d2 state is not supported. 9 d1_support ? ro. the d1 state is not supported. 8:6 aux_current ? ro. pme# from d3cold state is not su pported, therefore this field is 000b. 5 device specific initialization (dsi) ? ro. this bit indicates th at device-specific initialization is required. 4 reserved 3 pme clock (pmec) ? ro. does not apply. hardwired to 0. 2:0 version (vs) ? ro. this field indicates support for revision 1.2 of the pci power management specification. intel ? ich8 family datasheet 797 thermal sensor registers (d31:f6) 21.1.24 pcs?power management control and status address offset: 54h ? 57h attribute: r/w, ro default value: 0022h size: 32 bits bit description 31:24 data ? ro. does not apply. hardwired to 0s. 23 bus power/clock control enable (bpcce) ? ro. hardwired to 0. 22 b2/b3 support (b23) ? ro. does not apply. hardwired to 0. 21:16 reserved 15 pme status (pmes) ? ro. this bit is always zero sinc e this pci function does not generate pme#. 14:9 reserved 8 pme enable (pmee) ? ro. this bit is always zero since this pci function does not generate pme#. 7:4 reserved 3 no soft reset ? ro. when set to 1, this bit indicates that devices transitioning from d3hot to d0 because of powerstate comma nds do not perform an internal reset. configuration context is preserved. upon transition from d3hot to d0 initialized state, no additional operating syst em intervention is required to preserve configuration context beyond writing the powerstate bits. 2 reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the thermal controller and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state if software attempts to write a value of 10b or 01b in to this field, th e write operation must complete normally; however, the data is discarded and no state change occurs. when in the d3 hot states, the thermal controller?s co nfiguration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. when software changes this value from the d3 hot state to the d0 state, no internal warm (soft) reset is generated. thermal sensor registers (d31:f6) 798 intel ? ich8 family datasheet 21.2 thermal memory mapped configuration registers (thermal sensor - d31:f26) the base memory for these thermal memory mapped configuration registers is specified in the tbarb (d31:f6, offset 40h). the individual registers are then accessible at tbarb + offset. there are two sensors in the ich8. each sensor has a separate configuration register set. both sensors must be configured together. 21.2.1 tsxe?thermal sensor [1:0] enable offset address: sensor 0: tbarb+01h attribute: r/w sensor 1: tbarb+41h default value: 00h size: 8 bit 21.2.2 tsxs?thermal sensor[1:0] status offset address: sensor 0: tbarb+02h attribute: ro sensor 1: tbarb+42h default value: 00h size: 8 bit 21.2.3 tsxttp?thermal sensor [1 :0] catastrophic trip point offset address: sensor 0: tbarb+04h attribute: r/w sensor 1: tbarb+44h default value: 00h size: 32 bit bit description 7:0 thermal sensor enable (tse) ? r/w. bios shall always program this register to the value bah to enable the thermal sensor. all other values are reserved. bit description 7 catastrophic trip indicator (cti) ? ro. 1 = temperature is above the catastrophic setting. 0 = temperature is below the catastrophic setting. 6:0 reserved bit description 31:8 reserved 7:0 catastrophic trip point setting (ctps) ? r/w. these bits set the catastrophic trip point. bios must write a value of 0ah to offset 04h and a value of 0bh to offset 44h to set the trip point. these bits are lockable via tsxco.bit 7. intel ? ich8 family datasheet 799 thermal sensor registers (d31:f6) 21.2.4 tsxco?thermal sensor [1 :0] catastrophic lock-down offset address: sensor 0: tbarb+08h attribute: r/w sensor 1: tbarb+48h default value: 00h size: 8 bit 21.2.5 tsxpc?thermal sens or [1:0] policy control offset address: sensor 0: tbarb+0eh attribute: r/w sensor 1: tbarb+4eh default value: 00h size: 8 bit 21.2.6 tsxlock?thermal sensor [1:0] register lock control offset address: sensor 0: tbarb+83h attribute: r/w sensor 1: tbarb+c3h default value: 00h size: 8 bit bit description 7 lock bit for catastrophic (lbc) ? r/w. this bit may only be set to a 0 by a hardware reset. writing a 0 to this bit has no effect. 1 = locks the catastrophic programming interface including tsxttp.bits[7:0]. 0 = catastrophic programmin g interface is unlocked 6:0 reserved bit description 7 policy lock-down bit ? r/w. this bit may only be set to a 0 by a hardware reset. writing a 0 to this bit has no effect. 1 = prevents writes to this register. 0 = this register can be programmed and modified. note: tsxco.bit 7 and tsxlock.bit 2 must also be 1 when this bit is set to 1. 6 catastrophic power-down enable ? r/w. 0 = disable 1 = enable. power management logic unconditionally transitions to the s5 state when a catastrophic temperature is detected by the sensor. 5:0 reserved bit description 7:3 reserved 2 lock control ? r/w. this bit must be set to 1 when tsxpc.bit7 is set to 1. 1:0 reserved thermal sensor registers (d31:f6) 800 intel ? ich8 family datasheet intel ? ich8 family datasheet 801 ballout definition 22 ballout definition this chapter contains the intel ? ich8 ballout information. 22.1 ballout (desktop only) figure 18 and figure 19 show the top view ballout for the 82801hb ich8 and 82801hr ich8r and 82801hdh ich8dh and 82801hdo ich8do components. table 146 provides the ballout, organized alphabetically by signal name. note: ?**? indicates signals that are not on the ich8 base component. since sata ports 2 and 3 are not on ich8 base, the balls for the following signal names are reserved on the ich8 base component. sata2txp/sata2txn, sata2rxp/sata2rxn, sata2gp, sata3txp/sata3txn, sata3gp, and sata3rxp/sata3rxn are reserved. note: ?*? indicates signals that ar e only on the 82801hdh ich8dh ballout definition 802 intel ? ich8 family datasheet figure 18. ballout (top view ?left side) (desktop only) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a pwrbtn# v5ref_ sus pirqc# gnt0# vss vcc3_3 trdy# pirqd# req3#/ gpio54 c/be1# ad14 c/be3# ad8 ad2 a b clk48 vss fwh4/ lframe# vcc3_3 ad28 irdy# ad26 vss gnt3#/ gpio55 pciclk vss devsel# ad4 vss b c vccusbpll clpwrok ldrq1#/ gpio23 pirqa# pirqb# ad27 ad24 vcc3_3 perr# vcc3_3 ad16 c/be2# ad11 ad9 c d vcc1_5_a vss pme# vss pirqe#/ gpio2 vss ad23 ad22 par ad15 plock# vss ad19 vcc3_3 d e usbrbias# usbrbias pcirst# susclk fwh3/lad3 serr# ad31 req0# vss vcc3_3 ad21 ad18 ad17 ad10 e f ck_ pwrgd vss vccsus3_3 vss fwh1/lad1 fwh0/lad0 vss ad30 pirqh#/ gpio5 pirqf#/ gpio3 vcc3_3 ad29 ad25 ad20 f g vss usbp0n usbp0p vss vss vss sus_ stat#/ lpcpd ldrq0# fwh2/ lad2 vss pirqg#/ gpio4 vcc1_5_a vss vcc3_3 g h usbp2n usbp2p vss usbp1p usbp1n vss vss h j vss usbp3p usbp3n vss vss vccsus1_05 vccsus1_5 j k usbp5n usbp5p vss usbp4p usbp4n vss vss k l vss usbp6p usbp6n vss vss vcc1_5_a vcc1_5_a vcc1_05 vcc1_05 vss vcc1_05 l m usbp8p usbp8n vss usbp7p usbp7n vcc1_5_a vcc1_5_a vcc1_05 vss vss vss m n vss usbp9n usbp9p vss vss vccsus3_3 vccsus3_3 vss vss vss vss n p vccsus3_3 vccsus3_3 vccsus3_3 vss vcc3_3 vccsus3_3 vccsus3_3 vcc1_05 vss vss vss p r satarbias satarbias# vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vss vss vss vss r t sata5rxn sata5rxp vss vss vss vss vcc1_5_a vcc1_05 vss vss vss t u vss vss sata4txn sata4txp vcc1_5_a vcc1_5_a vcc1_5_a vcc1_05 vss vss vss u v sata5txp sata5txn vcc1_5_a vcc1_5_a vcc1_5_a vcc1_5_a vss v w vcc1_5_a vcc1_5_a vcc1_5_a sata2rxp** sata2rxn* * vcc1_5_a vcc1_5_a w y sata4rxn sata4rxp vss vss vss vcc1_5_a vcc1_5_a y aa vss vss sata2txn* * sata2txp** vcc1_5_a vcc1_5_a vcc1_5_a aa ab sata3rxn** sata3rxp** vcc1_5_a vcc1_5_a vcc1_5_a pwm0 vcc3_3 pwm2 vcc1_5_a sataled# sata0gp/ gpio21 vss vcc1_5_a vccsushda ab ac vcc1_5_a vcc1_5_a vcc1_5_a sata0rxp sata0rxn vss tach0/ gpio17 tach3/ gpio7 vss sdataout0 /gpio39 gpio18 init3_3v# vcchda hda_ sdin1 ac ad sata3txp** sata3txn** vss vss vss pwm1 vcc3_3 sata1gp/ gpio19 sata3gp* */gpio37 sata4gp vss sataclkre q#/gpio35 hda_ sdin3 oc8# ad ae vss vss sata0txp sata0txn vss tach2/ gpio6 sclock/ gpio22 vss sata5gp mch_ sync# gpio16 vcc3_3 hda_ sdin0 vss ae af sata1rxn sata1rxp vss vss tach1/ gpio1 spkr sdataout 1/gpio48 sata2gp**/ gpio36 gpio0 rcin# vcc3_3 hda_bit_c lk hda_rst# oc7#/ gpio31 af ag vss vss sata_ clkn sata_clkp vss clk14 gpio33 gpio20 serirq a20gate vss gpio34 oc6#/ gpio30 oc2#/ gpio41 ag ah sata1txp sata1txn vss vss vccsatapll sload/ gpio38 gpio32 vss thrm# hda_sync hda_ sdout hda_ sdin2 vss oc1#/ gpio40 ah 1 2 3 4 5 6 7 8 9 10 11 12 13 14 intel ? ich8 family datasheet 803 ballout definition figure 19. ballout (top view ?right side) (desktop only) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a v5ref ad1 ad3 spi_cs1# spi_clk vcccl1_05 vcccl1_5 vccglan3_3 vcc1_05 vss vccglanpll vcc glan1_5 vcc glan1_5 vss a b vcc3_3 req2#/ gpio52 vss vcc3_3 spi_miso vss cl_vref vss vcc1_05 vss vccglan1_5 vcc glan1_5 petp6/ glan_ txp petn6 / glan_txn b c gnt1#/ gpio51 req1#/ gpio50 ad7 lan_txd1 lan_rxd1 lan_txd0 spi_cs0# vss vcc1_05 glan_ compo perp6 / glan_rxp pern6 / glan_rxn vss vss c d stop# vss gnt2#/ gpio53 lan_txd2 vss lan_rxd2 spi_mosi vss vcc1_05 glan_ compi vss vss petp5 petn5 d e ad12 frame# ad6 ad0 lan_rxd0 lan_ rstsync vss glan_clk vcc1_05 vss perp5 pern5 vss vss e f vss ad13 vcclan1_05 ad5 vcclan3_3 vcccl3_3 cl_clk vss vcc1_05 vss vss vss petp4 petn4 f g vcc1_5_a c/be0# vcclan1_05 vss vcclan3_3 vcccl3_3 cl_data vcc1_05 vcc1_05 vss perp4 pern4 vss vss g h vcc1_05 vss vss vss vss petp3 petn3 h j vcc1_5_b vcc1_5_b vcc1_5_b perp3 pern3 vss vss j k vcc1_5_b vcc1_5_b vcc1_5_b vss vss petp2 petn2 k l vss vcc1_05 vcc1_05 vcc1_05 vcc1_5_b vcc1_5_b vcc1_5_b pern2 perp2 vss vss l m vss vss vss vcc1_05 vss vcc1_5_b vcc1_5_b vss vss petp1 petn1 m n vss vss vss vss vcc1_5_b vcc1_5_b vcc1_5_b pern1 perp1 vss vss n p vss vss vss vcc1_05 vss vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vss vccdmipll p r vss vss vss vss vcc1_5_b vcc1_5_b dmi_clkp dmi_clkn vcc1_5_b vcc1_5_b vcc1_5_b r t vss vss vss vcc1_05 vss vcc1_5_b vcc1_5_b vss vss dmi0txp dmi0txn t u vss vss vss vcc1_05 vcc1_5_b vcc1_5_b vcc1_5_b dmi0rxp dmi0rxn vss vss u v vss vcc1_05 vcc1_05 vcc1_05 vss vcc1_5_b vcc1_5_b vss vss dmi1txp dmi1txn v w vcc1_5_b vcc1_5_b vcc1_5_b dmi1rxp dmi1rxn vss vss w y vcc1_5_a vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b dmi2txp dmi2txn y aa intvrmen vss dmi2rxp dmi2rxn vcc1_5_b vcc1_5_b vcc1_5_b aa ab vccsus1_5 vccsus3_3 vccsus1_05 smbdata init# smi# vccsus3_3 ferr# stpclk# vss vss vss dmi3txp dmi3txn ab ac vss vrmpwrgd slp_s5# vss gpio12 vcc sus3_3 vss ignne# nmi cpuslp# dmi3rxp dmi3rxn vss vss ac ad qrt_state1*/ gpio28 tp3 sst vccsus3_3 smbclk qrt_ state0*/ gpio27 rtcrst# rsmrst# a20m# tp2 v_cpu_io vss dmi_ zcomp dmi_ ircomp ad ae oc5#/gpio29 gpio8 vss tp4 smlink0 vss gpio15 tp0 vss pwrok tp1 v_cpu_io vccdmi vccdmi ae af oc0# sys_reset# lan_rst# gpio13 vccsus3_3 alert#/ gpio10 smbalert#/ gpio11 slp_s3# pltrst# intruder# cpupwrgd/ gpio49 peci vss vcc3_3 af ag oc3# /gpio42 oc9# ri# wol_ enable/ gpio9 cl_rst# tp6 smlink1 slp_m# clgpio0/ gpio24 lan100_ slp vss vccrtc vss thrmtrip# ag ah oc4#/gpio43 vss gpio25 wake# vss tp5 linkalert# vss slp_s4# netdetect /gpio14 s4_state#/ gpio26 rtcx1 rtcx2 intr ah 15 16 17 18 19 20 21 22 23 24 25 26 27 28 804 intel ? ich8 family datasheet ballout definition table 146. ballout by signal name (desktop only) ball name ball # a20gate ag10 a20m# ad23 ad0 e18 ad1 a16 ad2 a14 ad3 a17 ad4 b13 ad5 f18 ad6 e17 ad7 c17 ad8 a13 ad9 c14 ad10 e14 ad11 c13 ad12 e15 ad13 f16 ad14 a11 ad15 d10 ad16 c11 ad17 e13 ad18 e12 ad19 d13 ad20 f14 ad21 e11 ad22 d8 ad23 d7 ad24 c7 ad25 f13 ad26 b7 ad27 c6 ad28 b5 ad29 f12 ad3 a17 ad30 f8 ad31 e7 c/be1# a10 c/be2# c12 c/be3# a12 ck_pwrgd f1 cl_clk0 f21 cl_data0 g21 cl_rst# ag19 cl_vref0 b21 clgpio0/gpio24 ag23 alert#/gpio10 af20 netdetect / gpio14 ah24 clk14 ag6 clk48 b1 clpwrok c2 cpupwrgd/ gpio49 af25 cpuslp# ac24 devsel# b12 dmi_clkn r25 dmi_clkp r24 dmi_ircomp ad28 dmi_zcomp ad27 dmi0rxn u26 dmi0rxp u25 dmi0txn t28 dmi0txp t27 dmi1rxn w26 dmi1rxp w25 dmi1txn v28 dmi1txp v27 dmi2rxn aa25 dmi2rxp aa24 dmi2txn y28 dmi2txp y27 dmi3rxn ac26 dmi3rxp ac25 dmi3txn ab28 dmi3txp ab27 ferr# ab22 frame# e16 fwh0/lad0 f6 fwh1/lad1 f5 fwh2/lad2 g9 table 146. ballout by signal name (desktop only) ball name ball # fwh3/lad3 e5 fwh4/lframe# b3 glan_clk e22 glan_compi d24 glan_compo c24 gnt0# a4 gnt1#/gpio51 c15 gnt2#/gpio53 d17 gnt3#/gpio55 b9 gpio0 af9 gpio8 ae16 gpio12 ac19 gpio13 af18 gpio15 ae21 gpio16 ae11 gpio18 ac11 gpio20 ag8 gpio25 ah17 gpio32 ah7 gpio33 ag7 gpio34 ag12 hda_bit_clk af12 hda_rst# af13 hda_sdin0 ae13 hda_sdin1 ac14 hda_sdin2 ah12 hda_sdin3 ad13 hda_sdout ah11 hda_sync ah10 ignne# ac22 init# ab19 init3_3v# ac12 intr ah28 intruder# af24 intvrmen aa22 irdy# b6 lan_rst# af17 lan_rstsync e20 lan_rxd0 e19 table 146. ballout by signal name (desktop only) ball name ball # intel ? ich8 family datasheet 805 ballout definition lan_rxd1 c19 lan_rxd2 d20 lan_txd0 c20 lan_txd1 c18 lan_txd2 d18 lan100_slp ag24 ldrq0# g8 ldrq1#/gpio23 c3 linkalert# ah21 mch_sync# ae10 nmi ac23 oc0# af15 oc1#/gpio40 ah14 oc2#/gpio41 ag14 oc3# /gpio42 ag15 oc4#/gpio43 ah15 oc5#/gpio29 ae15 oc6#/gpio30 ag13 oc7#/gpio31 af14 oc8# ad14 oc9# ag16 par d9 pciclk b10 pcirst# e3 peci af26 pern1 n25 pern2 l25 pern3 j26 pern4 g26 pern5 e26 pern6 / glan_rxn c26 perp1 n26 perp2 l26 perp3 j25 perp4 g25 perp5 e25 perp6 / glan_rxp c25 perr# c9 petn1 m28 table 146. ballout by signal name (desktop only) ball name ball # petn2 k28 petn3 h28 petn4 f28 petn5 d28 petn6 / glan_txn b28 petp1 m27 petp2 k27 petp3 h27 petp4 f27 petp5 d27 petp6/ glan_txp b27 pirqa# c4 pirqb# c5 pirqc# a3 pirqd# a8 pirqe#/gpio2 d5 pirqf#/gpio3 f10 pirqg#/gpio4 g11 pirqh#/gpio5 f9 plock# d11 pltrst# af23 pme# d3 pwm0 ab6 pwm1 ad6 pwm2 ab8 pwrbtn# a1 pwrok ae24 qrt_state0*/ gpio27 ad20 qrt_state1*/ gpio28 ad15 rcin# af10 req0# e8 req1#/gpio50 c16 req2#/gpio52 b16 req3#/gpio54 a9 ri# ag17 rsmrst# ad22 rtcrst# ad21 rtcx1 ah26 table 146. ballout by signal name (desktop only) ball name ball # rtcx2 ah27 s4_state#/ gpio26 ah25 sata_clkn ag3 sata_clkp ag4 sata0gp/gpio21 ab11 sata0rxp ac4 sata0rxn ac5 sata0txn ae4 sata0txp ae3 sata1gp/gpio19 ad8 sata1rxn af1 sata1rxp af2 sata1txn ah2 sata1txp ah1 sata2gp**/ gpio36 af8 sata2rxn** w5 sata2rxp** w4 sata2txn** aa3 sata2txp** aa4 sata3gp**/ gpio37 ad9 sata3rxn** ab1 sata3rxp** ab2 sata3txn** ad2 sata3txp** ad1 sata4gp ad10 sata4rxn y1 sata4rxp y2 sata4txn u3 sata4txp u4 sata5gp ae9 sata5rxn t1 sata5rxp t2 sata5txn v2 sata5txp v1 sataclkreq#/ gpio35 ad12 sataled# ab10 satarbias r1 table 146. ballout by signal name (desktop only) ball name ball # 806 intel ? ich8 family datasheet ballout definition satarbias# r2 sclock/gpio22 ae7 sdataout0/ gpio39 ac10 sdataout1/ gpio48 af7 serirq ag9 serr# e6 sload/gpio38 ah6 slp_m# ag22 slp_s3# af22 slp_s4# ah23 slp_s5# ac17 smbalert#/ gpio11 af21 smbclk ad19 smbdata ab18 smi# ab20 smlink0 ae19 smlink1 ag21 spi_clk a19 spi_cs0# c21 spi_cs1# a18 spi_miso b19 spi_mosi d21 spkr af6 sst ad17 stop# d15 stpclk# ab23 sus_stat#/lpcpd g7 susclk e4 sys_reset# af16 tach0/gpio17 ac7 tach1/gpio1 af5 tach2/gpio6 ae6 tach3/gpio7 ac8 thrm# ah9 thrmtrip# ag28 tp0 ae22 tp1 ae25 table 146. ballout by signal name (desktop only) ball name ball # tp2 ad24 tp3 ad16 tp4 ae18 tp5 ah20 tp6 ag20 trdy# a7 usbp0n g2 usbp0p g3 usbp1n h5 usbp1p h4 usbp2n h1 usbp2p h2 usbp3n j3 usbp3p j2 usbp4n k5 usbp4p k4 usbp5n k1 usbp5p k2 usbp6n l3 usbp6p l2 usbp7n m5 usbp7p m4 usbp8n m2 usbp8p m1 usbp9n n2 usbp9p n3 usbrbias e2 usbrbias# e1 v_cpu_io ad25 v_cpu_io ae26 v5ref a15 v5ref_sus a2 vcc1_05 a23 vcc1_05 b23 vcc1_05 c23 vcc1_05 d23 vcc1_05 e23 vcc1_05 f23 vcc1_05 g22 table 146. ballout by signal name (desktop only) ball name ball # vcc1_05 g23 vcc1_05 h22 vcc1_05 l11 vcc1_05 l12 vcc1_05 l14 vcc1_05 l16 vcc1_05 l17 vcc1_05 l18 vcc1_05 m11 vcc1_05 m18 vcc1_05 p11 vcc1_05 p18 vcc1_05 t11 vcc1_05 t18 vcc1_05 u11 vcc1_05 u18 vcc1_05 v11 vcc1_05 v12 vcc1_05 v14 vcc1_05 v16 vcc1_05 v17 vcc1_05 v18 vcc1_5_a d1 vcc1_5_a l6 vcc1_5_a l7 vcc1_5_a m6 vcc1_5_a m7 vcc1_5_a w7 vcc1_5_a y7 vcc1_5_a aa7 vcc1_5_a g12 vcc1_5_a g15 vcc1_5_a y22 vcc1_5_a ab9 vcc1_5_a ab13 vcc1_5_a t7 vcc1_5_a u5 vcc1_5_a u6 vcc1_5_a v3 table 146. ballout by signal name (desktop only) ball name ball # intel ? ich8 family datasheet 807 ballout definition vcc1_5_a v4 vcc1_5_a v5 vcc1_5_a w1 vcc1_5_a w2 vcc1_5_a w3 vcc1_5_a u7 vcc1_5_a v6 vcc1_5_a w6 vcc1_5_a y6 vcc1_5_a aa5 vcc1_5_a aa6 vcc1_5_a ab3 vcc1_5_a ab4 vcc1_5_a ab5 vcc1_5_a ac1 vcc1_5_a ac2 vcc1_5_a ac3 vcc1_5_b j22 vcc1_5_b j23 vcc1_5_b j24 vcc1_5_b k22 vcc1_5_b k23 vcc1_5_b k24 vcc1_5_b l22 vcc1_5_b l23 vcc1_5_b l24 vcc1_5_b m23 vcc1_5_b m24 vcc1_5_b n22 vcc1_5_b n23 vcc1_5_b n24 vcc1_5_b p23 vcc1_5_b p24 vcc1_5_b p25 vcc1_5_b p26 vcc1_5_b r22 vcc1_5_b r23 vcc1_5_b r26 vcc1_5_b r27 table 146. ballout by signal name (desktop only) ball name ball # vcc1_5_b r28 vcc1_5_b t23 vcc1_5_b t24 vcc1_5_b u22 vcc1_5_b u23 vcc1_5_b u24 vcc1_5_b v23 vcc1_5_b v24 vcc1_5_b w22 vcc1_5_b w23 vcc1_5_b w24 vcc1_5_b y23 vcc1_5_b y24 vcc1_5_b y25 vcc1_5_b y26 vcc1_5_b aa26 vcc1_5_b aa27 vcc1_5_b aa28 vcc_dmi ae27 vcc_dmi ae28 vcc3_3 a6 vcc3_3 b4 vcc3_3 b15 vcc3_3 b18 vcc3_3 c8 vcc3_3 c10 vcc3_3 d14 vcc3_3 e10 vcc3_3 f11 vcc3_3 g14 vcc3_3 ab7 vcc3_3 ad7 vcc3_3 ae12 vcc3_3 af11 vcc3_3 p5 vcc3_3 af28 vcccl1_05 a20 vcccl1_5 a21 vcccl3_3 f20 table 146. ballout by signal name (desktop only) ball name ball # vcccl3_3 g20 vccdmipll p28 vccglan1_5 a26 vccglan1_5 a27 vccglan1_5 b25 vccglan1_5 b26 vccglan3_3 a22 vccglanpll a25 vcchda ac13 vcclan1_05 f17 vcclan1_05 g17 vcclan3_3 f19 vcclan3_3 g19 vccrtc ag26 vccsatapll ah5 vccsus1_05 ab17 vccsus1_05 j6 vccsus1_5 j7 vccsus1_5 ab15 vccsus3_3 n6 vccsus3_3 n7 vccsus3_3 p1 vccsus3_3 p2 vccsus3_3 p3 vccsus3_3 p6 vccsus3_3 p7 vccsus3_3 r3 vccsus3_3 r4 vccsus3_3 r5 vccsus3_3 r6 vccsus3_3 r7 vccsus3_3 ab16 vccsus3_3 ab21 vccsus3_3 ac20 vccsus3_3 ad18 vccsus3_3 af19 vccsus3_3 f3 vccsushda ab14 vccusbpll c1 table 146. ballout by signal name (desktop only) ball name ball # 808 intel ? ich8 family datasheet ballout definition vrmpwrgd ac16 vss b22 vss f4 vss p4 vss af27 vss ah8 vss a5 vss a24 vss a28 vss b2 vss b8 vss b11 vss b14 vss b17 vss b20 vss b24 vss c22 vss c27 vss c28 vss d2 vss d4 vss d6 vss d12 vss d16 vss d19 vss d22 vss d25 vss d26 vss e9 vss e21 vss e24 vss e27 vss e28 vss f2 vss f7 vss f15 vss f22 vss f24 vss f25 table 146. ballout by signal name (desktop only) ball name ball # vss f26 vss g1 vss g4 vss g5 vss g6 vss g10 vss g13 vss g18 vss g24 vss g27 vss g28 vss h3 vss h6 vss h7 vss h23 vss h24 vss h25 vss h26 vss j1 vss j4 vss j5 vss j27 vss j28 vss k3 vss k6 vss k7 vss k25 vss k26 vss l1 vss l4 vss l5 vss l13 vss l15 vss l27 vss l28 vss m3 vss m12 vss m13 vss m14 table 146. ballout by signal name (desktop only) ball name ball # vss m15 vss m16 vss m17 vss m22 vss m25 vss m26 vss n1 vss n4 vss n5 vss n11 vss n12 vss n13 vss n14 vss n15 vss n16 vss n17 vss n18 vss n27 vss n28 vss p12 vss p13 vss p14 vss p15 vss p16 vss p17 vss p22 vss p27 vss r11 vss r12 vss r13 vss r14 vss r15 vss r16 vss r17 vss r18 vss t3 vss t4 vss t5 vss t6 table 146. ballout by signal name (desktop only) ball name ball # intel ? ich8 family datasheet 809 ballout definition vss t12 vss t13 vss t14 vss t15 vss t16 vss t17 vss t22 vss t25 vss t26 vss u1 vss u2 vss u12 vss u13 vss u14 vss u15 vss u16 vss u17 vss u27 vss u28 vss v7 vss v13 vss v15 vss v22 vss v25 vss v26 vss w27 vss w28 vss y3 vss y4 vss y5 vss aa1 vss aa2 vss aa23 vss ab12 vss ab24 vss ab25 vss ab26 vss ac6 vss ac9 table 146. ballout by signal name (desktop only) ball name ball # vss ac15 vss ac18 vss ac21 vss ac27 vss ac28 vss ad3 vss ad4 vss ad5 vss ad11 vss ad26 vss ae1 vss ae2 vss ae5 vss ae8 vss ae14 vss ae17 vss ae20 vss ae23 vss af3 vss af4 vss ag1 vss ag2 vss ag5 vss ag11 vss ag25 vss ag27 vss ah3 vss ah4 vss ah13 vss ah16 vss ah19 vss ah22 wake# ah18 wol_en/gpio9 ag18 table 146. ballout by signal name (desktop only) ball name ball # ballout definition 810 intel ? ich8 family datasheet 22.2 ballout (mobile only) figure 20 and figure 21 show the top view ballout for the 82801hbm ich8m and 82801hem ich8m-e components. table 147 provides the ballout, organized alphabetically by signal name. figure 20. ballout (top vi ew?left side) (mobile only) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a vss_nctf vss_nctf ad31 req0# vss ad28 perr# vcc3_3 ad17 pirqd# req3#/ gpio54 ad10 vcc1_05 ad12 a b vss_nctf vss pirqh#/ gpio5 vcc3_3 pirqb# ad15 plock# vss vcc3_3 pciclk vss ad19 vcc1_05 vss b c vccsus3_3 pwrbtn# vccsus3_3 fwh4/ lframe# pirqc# vss ad22 irdy# trdy# gnt3#/ gpio55 ad16 ad20 vcc1_05 vcc1_05 c d vccusbpll vss susclk vss vss ad30 gnt0# ad27 par ad21 ad18 vss vcc3_3 vcc1_05 d e ck_ pwrgd vss clpwrok vss fwh0/lad0 ldrq1#/ gpio23 vcc3_3 ad29 vss vcc3_3 ad24 ad26 ad25 vcc1_05 e f vcc1_5_a usbrbias# usbrbias sus_stat# fwh1/lad1 fwh3/lad3 vss pirqe#/ gpio2 pirqa# serr# vcc3_3 pirqg#/ gpio4 ad23 vcc1_05 f g vss usbp0p usbp0n v5ref_sus clk48 pcirst# pme# fwh2/ lad2 ldrq0# vss pirqf#/ gpio3 vcc1_5_a vss vcci_05 g h usbp2p usbp2n vss usbp1p usbp1n vss vcc1_5_a h j vss usbp3p usbp3n vss vss vccsus1_05 vccsus1_5 j k usbp5p usbp5n vss usbp4p usbp4n vss vss k l vss usbp6p usbp6n vss vss vcc1_5_a vcc1_5_a vcc1_05 vcc1_05 vss vcc1_05 l m usbp8p usbp8n vss usbp7p usbp7n vcc1_5_a vcc1_5_a vcc1_05 vss vss vss m n vss usbp9p usbp9n vss vss vss vccsus3_3 vss vss vss vss n p vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vcc1_05 vss vss vss p r vccsus3_3 dd9 vccsus3_3 vss vccsus3_3 vccsus3_3 vss vss vss vss r t dd3 vss dd8 dd10 dd5 dd7 v5ref vcc1_05 vss vss vss t u dd13 dd1 vss vss vss dd15 vcc3_3 vcc1_05 vss vss vss u v dd0 dd14 dd2 dd4 dd12 dd11 vcc3_3 vcc1_05 vcc1_05 vss vcc1_05 v w vcc3_3 vss diow# dior# ddreq vcc3_3 vcc3_3 w y iordy ddack# ideirq vss dcs3# dcs1# vcc3_3 y aa da1 vss vcc3_3 da0 vcc1_5_a vcc1_5_a vss aa ab vss dd6 da2 vss vss vss sata_clkn ab ac vcc1_5_a vcc1_5_a vcc1_5_a vcc1_5_a vcc1_5_a sata_clkp vcc1_5_a vcc3_3 vcc1_5_a vcc1_5_a vss vcchda thrm# vss ac ad vss vcc3_3 vss vss vss vss vcc1_5_a vcc3_3 spkr sdataout1/ gpio48 vccsushda oc6#/ gpio30 hda_sdin3 oc8# ad ae vss vss sata2txp** sata2txn** vss vss vcc1_5_a vcc3_3 vss hda_dock_ en#/gpio33 gpio20 vss hda_sdout hda_rst# ae af sata2rxp** sata2rxn** vss vss sata0rxp sata0rxn vcc1_5_a vcc3_3 sload/ gpio38 sataled# sata2gp** /gpio36 serirq a20gate vss af ag satarbias# satarbias sata1rxn sata1rxp vss vss vcc1_5_a tacho/ gpio17 clk14 sclock/ gpio22 sata3gp** /gpio37 gpio0/ bmbusy# sataclkreq# /gpio35 hda_dock _rst#/ gpio34 ag ah vss_nctf vss vss vss sata0txn sata0txp vcc1_5_a vss tach3/ gpio7 sclock/ gpio22 clkrun#/ gpio32 gpio18 vss rcin# ah aj vss_nctf vss_nctf sata1txp sata1txn vss vss vcc1_5_a tach1/ gpio1 tach2/ gpio6 vss sdataout0 /gpio39 sata0gp/ gpio21 mch_sync# dprslpvr/ gpio16 aj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 intel ? ich8 family datasheet 811 ballout definition figure 21. ballout (top view ?right side) (mobile only) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 a ad14 v5ref frame# ad8 ad6 ad3 ad5 vcccl1_5 vss vccglanpll vss vccglan1_5vccglan1_5 vss_nctf vss_nctf a b vcc3_3 ad9 vss vcc3_3 req2#/ gpio52 vss lan_rxd1 vss spi_cs0# glan_clk vccglan3_3 vccglan1_5vccglan1_5vccglan1_5 vss_nctf b c vcc3_3 stop# c/be0# gnt1#/ gpio51 ad7 lan_txd2 lan_rxd0 lan_rxd1 smlink1 vss glan_ compo vss vss petp6 / glan_txp petn6 / glan_txn c d vss devsel# ad4 vss ad2 ad0 lan_txd0 lan_ rstsync spi_mosi cl_vref0 glan_ compi perp6/ glan_rxp pern6/ glan_rxn vcc1_5_b vcc1_5_b d e c/be1# ad11 c/be3# req1#/ gpio50 ad1 lan_txd1 vss spi_cs1# vss vss vcc1_5_b vcc1_5_b vcc1_5_b petp5 petn5 e f vss c/be2# vcclan1_05 gnt2#/ gpio53 vcclan3_3 vcccl3_3 spi_miso cl_data0 cl_clk0 vcc1_5_b vcc1_5_b perp5 pern5 vss vss f g ad13 vcc1_5_a vcclan1_05 vss vcclan3_3 vcccl3_3 vcccl1_05 vss vcc1_5_b vss vss vss petp4 petn4 g h vcc1_5_b vcc1_5_b vss perp4 pern4 vss vss h j vcc1_5_b vcc1_5_b vss vss vss petp3 petn3 j k vss vcc1_5_b vcc1_5_b perp3 pern3 vss vss k l vss vcc1_05 vcc1_05 vcc1_05 vcc1_5_b vcc1_5_b vcc1_5_b vss vss petp2 petn2 l m vss vss vss vcc1_05 vss vcc1_5_b vcc1_5_b perp2 pern2 vss vss m n vss vss vss vss vcc1_5_b vcc1_5_b vcc1_5_b vss vss petp1 petn1 n p vss vss vss vcc1_05 vss vcc1_5_b vcc1_5_b perp1 pern1 vss vss p r vss vss vss vss vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vss vccdmipll r t vss vss vss vcc1_05 vcc1_5_b vcc1_5_b dmi_clkp dmi_clkn vcc1_5_b vcc1_5_b vcc1_5_b t u vss vss vss vcc1_05 vss vcc1_5_b vcc1_5_b vss vss dmi0txp dmi0txn u v vss vcc1_05 vcc1_05 vcc1_05 vcc1_5_b vcc1_5_b vcc1_5_b dmi0rxp dmi0rxn vss vss v w vcc1_5 vss vcc1_5_b vss vss dmi1txp dmi1txn w y dmi_zcomp dmi_ ircomp vcc1_5_b dmi1rxp dmi1rxn vss vss y aa tp8 stpclk# vcc1_5_b vcc1_5_b vcc1_5_b dmi2txp dmi2txn aa ab vss vss dmi2rxp dmi2rxn vcc1_5_b vcc1_5_b vcc1_5_b ab ac vccsus1_5 smlink0 vccsus3_3 glan_doc k#/gpio12 intr vccsus3_3 vccsus3_3 v_cpu_io v_cpu_io vss vss vss dmi3txp dmi3txn ac ad sys_ reset# gpio28 vss slp_s5# smbdata vss lan100_ slp intruder# nmi ferr# vccrtc dmi3rxp dmi3rxn vss vss ad ae oc3#/ gpio42 gpio8 wake# cl_clk1 smlink1 stp_pci#/ gpio15 batlow# vss pwrok init# vss dpslp# thrmtrip# vcc_dmi vcc_dmi ae af oc4#/ gpio43 vss ri# vss cl_data1 vccsus1_05 slp_s4# ac_present /gpio14 rtcrst# rtcx2 intvrmen dprstp# ignne# vss vcc3_3 af ag oc2#/ gpio41 oc1#/ gpio40 oc5#/ gpio29 stp_cpu#/ gpio25 clgpio3/ gpio9 vccsus3_3 linkalert# smbalert#/ gpio11 slp_s3# pltrst# rtcx1 a20m# rsmrst# smi# clk14 ag ah hda_ sdin2 vss hda_sdin1 oc9# vss lan_rst# energy_de tect/ gpio13 vss cl_vref1 vss /gpio27 vss s4_state#/ gpio26 vccsus3_3 vss_nctf ah aj hda_sync hda_ bit_clk hda_sdin0 oc7#/ gpio31 oc0# vrmpwrgd tp3 tp7 cl_rst# suspwrack/ alert#/ gpio10 slp_m# vccsatapll clgpio0/ gpio24 vss_nctf vss_nctf aj 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 812 intel ? ich8 family datasheet ballout definition table 147.ballout by signal name (mobile only) ball name ball # a20gate af13 a20m# ag26 ac_present/ gpio14 af22 ad0 d20 ad1 e19 ad10 a12 ad11 e16 ad12 a14 ad13 g16 ad14 a15 ad15 b6 ad16 c11 ad17 a9 ad18 d11 ad19 b12 ad2 d19 ad20 c12 ad21 d10 ad22 c7 ad23 f13 ad24 e11 ad25 e13 ad26 e12 ad27 d8 ad28 a6 ad29 e8 ad3 a20 ad30 d6 ad31 a3 ad4 d17 ad5 a21 ad6 a19 ad7 c19 ad8 a18 ad9 b16 batlow# ae21 bmbusy#/gpio0 ag12 c/be0# c17 c/be1# e15 c/be2# f16 c/be3# e17 ck_pwrgd e1 cl_clk0 f23 cl_clk1 ae18 cl_data0 f22 cl_data1 af19 cl_rst# aj23 cl_vref0 d24 cl_vref1 ah23 clgpio0/gpio24 aj27 clk14 ag9 clk48 g5 clkrun# ah11 clpwrok e3 cpupwrgd/ gpio49 ag29 da0 aa4 da1 aa1 da2 ab3 dcs1# y6 dcs3# y5 dd0 v1 dd1 u2 dd10 t4 dd11 v6 dd12 v5 dd13 u1 dd14 v2 dd15 u6 dd2 v3 dd3 t1 dd4 v4 dd5 t5 dd6 ab2 dd7 t6 dd8 t3 dd9 r2 table 147.ballout by signal name (mobile only) ball name ball # ddack# y2 ddreq w5 devsel# d16 dior# w4 diow# w3 dmi_clkn t26 dmi_clkp t25 dmi_ircomp y24 dmi_zcomp y23 dmi0rxn v27 dmi0rxp v26 dmi0txn u29 dmi0txp u28 dmi1rxn y27 dmi1rxp y26 dmi1txn w29 dmi1txp w28 dmi2rxn ab26 dmi2rxp ab25 dmi2txn aa29 dmi2txp aa28 dmi3rxn ad27 dmi3rxp ad26 dmi3txn ac29 dmi3txp ac28 dprslpvr/gpio16 aj14 dprstp# af26 dpslp# ae26 energy_detect/ gpio13 ah21 ferr# ad24 frame# a17 fwh0/lad0 e5 fwh1/lad1 f5 fwh2/lad2 g8 fwh3/lad3 f6 fwh4/lframe# c4 glan_clk b24 glan_compi d25 table 147.ballout by signal name (mobile only) ball name ball # intel ? ich8 family datasheet 813 ballout definition glan_compo c25 glan_dock#/ gpio12 ac19 gnt0# d7 gnt1#/gpio51 c18 gnt2#/gpio53 f18 gnt3#/gpio55 c10 gpio18 ah12 gpio20 ae11 gpio8 ae16 hda_bit_clk aj16 hda_dock_en#/ gpio33 ae10 hda_dock_rst#/ gpio34 ag14 hda_rst# ae14 hda_sdin0 aj17 hda_sdin1 ah17 hda_sdin2 ah15 hda_sdin3 ad13 hda_sdout ae13 hda_sync aj15 ideirq y3 ignne# af27 init# ae24 intr ac20 intruder# ad22 intvrmen af25 iordy y1 irdy# c8 lan_rst# ah20 lan_rstsync d22 lan_rxd0 c21 lan_rxd1 b21 lan_rxd2 c22 lan_txd0 d21 lan_txd1 e20 lan_txd2 c20 lan100_slp ad21 ldrq0# g9 table 147.ballout by signal name (mobile only) ball name ball # ldrq1#/gpio23 e6 linkalert# ag21 mch_sync# aj13 nmi ad23 oc0# aj19 oc1#/gpio40 ag16 oc2#/gpio41 ag15 oc3#/gpio42 ae15 oc4#/gpio43 af15 oc5#/gpio29 ag17 oc6#/gpio30 ad12 oc7#/gpio31 aj18 oc8# ad14 oc9# ah18 par d9 pciclk b10 pcirst# g6 pern1 p27 pern2 m27 pern3 k27 pern4 h27 pern5 f27 pern6/glan_rxn d27 perp1 p26 perp2 m26 perp3 k26 perp4 h26 perp5 f26 perp6/glan_rxp d26 perr# a7 petn1 n29 petn2 l29 petn3 j29 petn4 g29 petn5 e29 petn6/glan_txn c29 petp1 n28 petp2 l28 petp3 j28 table 147.ballout by signal name (mobile only) ball name ball # petp4 g28 petp5 e28 petp6/glan_txp c28 pirqa# f9 pirqb# b5 pirqc# c5 pirqd# a10 pirqe#/gpio2 f8 pirqf#/gpio3 g11 pirqg#/gpio4 f12 pirqh#/gpio5 b3 plock# b7 pltrst# ag24 pme# g7 pwrbtn# c2 pwrok ae23 gpio27 ah25 gpio28 ad16 rcin# ah14 req0# a4 req1#/gpio50 e18 req2#/gpio52 b19 req3#/gpio54 a11 ri# af17 rsmrst# ag27 rtcrst# af23 rtcx1 ag25 rtcx2 af24 s4_state#/ gpio26 ah27 sata_clkn ab7 sata_clkp ac6 sata0gp/gpio21 aj12 sata0rxn af6 sata0rxp af5 sata0txn ah5 sata0txp ah6 sata1gp/gpio19 aj10 sata1rxn ag3 table 147.ballout by signal name (mobile only) ball name ball # 814 intel ? ich8 family datasheet ballout definition sata1rxp ag4 sata1txn aj4 sata1txp aj3 sata2gp**/ gpio36 af11 sata2rxn** af2 sata2rxp** af1 sata2txn** ae4 sata2txp** ae3 gpio37 ag11 sataclkreq#/ gpio35 ag13 sataled# af10 satarbias ag2 satarbias# ag1 sclock/gpio22 ag10 sdataout0/ gpio39 aj11 sdataout1/ gpio48 ad10 serirq af12 serr# f10 sload/gpio38 af9 slp_m# aj25 slp_s3# ag23 slp_s4# af21 slp_s5# ad18 smbalert#/ gpio11 ag22 smbclk aj26 smbdata ad19 smi# ag28 smlink0 ac17 smlink1 ae19 spi_clk c23 spi_cs0# b23 spi_cs1# e22 spi_miso f21 spi_mosi d23 spkr ad9 stop# c16 table 147.ballout by signal name (mobile only) ball name ball # stp_cpu# ag18 stp_pci# ae20 stpclk# aa24 suspwrack/ alert#/gpio10 aj24 sus_stat#/ lpcpd# f4 susclk d3 sys_reset# ad15 gpio17 ag8 gpio1 aj8 gpio6 aj9 gpio7 ah9 thrm# ac13 thrmtrip# ae27 tp3 aj21 tp7 aj22 tp8 aa23 trdy# c9 usbp0n g3 usbp0p g2 usbp1n h5 usbp1p h4 usbp2n h2 usbp2p h1 usbp3n j3 usbp3p j2 usbp4n k5 usbp4p k4 usbp5n k2 usbp5p k1 usbp6n l3 usbp6p l2 usbp7n m5 usbp7p m4 usbp8n m2 usbp8p m1 usbp9n n3 usbp9p n2 usbrbias f3 table 147.ballout by signal name (mobile only) ball name ball # usbrbias# f2 v_cpu_io ac23 v_cpu_io ac24 v5ref t7 v5ref a16 v5ref_sus g4 vcc_dmi ae28 vcc_dmi ae29 vcc1_05 l11 vcc1_05 m11 vcc1_05 p11 vcc1_05 t11 vcc1_05 u11 vcc1_05 v11 vcc1_05 g14 vcc1_05 l12 vcc1_05 v12 vcc1_05 a13 vcc1_05 b13 vcc1_05 c13 vcc1_05 c14 vcc1_05 d14 vcc1_05 e14 vcc1_05 f14 vcc1_05 l14 vcc1_05 v14 vcc1_05 l16 vcc1_05 v16 vcc1_05 l17 vcc1_05 v17 vcc1_05 l18 vcc1_05 m18 vcc1_05 p18 vcc1_05 t18 vcc1_05 u18 vcc1_05 v18 vcc1_5_a w23 vcc1_5_a ac7 vcc1_5_a ae7 table 147.ballout by signal name (mobile only) ball name ball # intel ? ich8 family datasheet 815 ballout definition vcc1_5_a af7 vcc1_5_a ag7 vcc1_5_a ah7 vcc1_5_a aj7 vcc1_5_a ac1 vcc1_5_a ac2 vcc1_5_a ac3 vcc1_5_a ac9 vcc1_5_a ac10 vcc1_5_a aa5 vcc1_5_a aa6 vcc1_5_a g12 vcc1_5_a g17 vcc1_5_a ad7 vcc1_5_a f1 vcc1_5_a l6 vcc1_5_a m6 vcc1_5_a l7 vcc1_5_a m7 vcc1_5_a ac4 vcc1_5_a ac5 vcc1_5_a h7 vcc1_5_b h23 vcc1_5_b j23 vcc1_5_b l23 vcc1_5_b n23 vcc1_5_b t23 vcc1_5_b v23 vcc1_5_b f24 vcc1_5_b g24 vcc1_5_b h24 vcc1_5_b j24 vcc1_5_b k24 vcc1_5_b l24 vcc1_5_b m24 vcc1_5_b n24 vcc1_5_b p24 vcc1_5_b r24 vcc1_5_b t24 table 147.ballout by signal name (mobile only) ball name ball # vcc1_5_b u24 vcc1_5_b v24 vcc1_5_b e25 vcc1_5_b f25 vcc1_5_b k25 vcc1_5_b l25 vcc1_5_b m25 vcc1_5_b n25 vcc1_5_b p25 vcc1_5_b r25 vcc1_5_b u25 vcc1_5_b v25 vcc1_5_b w25 vcc1_5_b y25 vcc1_5_b aa25 vcc1_5_b e26 vcc1_5_b r26 vcc1_5_b aa26 vcc1_5_b e27 vcc1_5_b r27 vcc1_5_b t27 vcc1_5_b aa27 vcc1_5_b ab27 vcc1_5_b d28 vcc1_5_b t28 vcc1_5_b ab28 vcc1_5_b d29 vcc1_5_b t29 vcc1_5_b ab29 vcc3_3 w6 vcc3_3 v7 vcc3_3 d5 vcc3_3 af29 vcc3_3 ad2 vcc3_3 ad8 vcc3_3 ae8 vcc3_3 af8 vcc3_3 w1 vcc3_3 aa3 table 147.ballout by signal name (mobile only) ball name ball # vcc3_3 w7 vcc3_3 y7 vcc3_3 b4 vcc3_3 e7 vcc3_3 a8 vcc3_3 b9 vcc3_3 e10 vcc3_3 f11 vcc3_3 d13 vcc3_3 b15 vcc3_3 b18 vcc3_3 ac8 vcc3_3 u7 vcc3_3 c15 vcccl1_05 g22 vcccl1_5 a22 vcccl3_3 f20 vcccl3_3 g21 vccdmipll r29 vccglan1_5 b28 vccglan1_5 a26 vccglan1_5 b26 vccglan1_5 a27 vccglan1_5 b27 vccglan3_3 b25 vccglanpll a24 vcchda ac12 vcclan1_05 f17 vcclan1_05 g18 vcclan3_3 f19 vcclan3_3 g20 vccrtc ad25 vccsatapll aj6 vccsus1_05 j6 vccsus1_05 af20 vccsus1_5 ac16 vccsus1_5 j7 vccsus3_3 ac18 vccsus3_3 ag20 table 147.ballout by signal name (mobile only) ball name ball # 816 intel ? ich8 family datasheet ballout definition vccsus3_3 ac21 vccsus3_3 ac22 vccsus3_3 ah28 vccsus3_3 c1 vccsus3_3 p1 vccsus3_3 r1 vccsus3_3 p2 vccsus3_3 p3 vccsus3_3 r3 vccsus3_3 p4 vccsus3_3 p5 vccsus3_3 r5 vccsus3_3 p6 vccsus3_3 r6 vccsus3_3 n7 vccsus3_3 p7 vccsus3_3 c3 vccsushda ad11 vccusbpll d1 vrmpwrgd aj20 vss e23 vss d18 vss a5 vss b20 vss ab4 vss d15 vss ae25 vss ah8 vss ah10 vss b22 vss c24 vss ac14 vss ae22 vss ah2 vss ae9 vss e4 vss ah13 vss e2 vss ad6 table 147.ballout by signal name (mobile only) ball name ball # vss ad3 vss ad4 vss b14 vss c26 vss c27 vss u3 vss u4 vss u5 vss ac11 vss h6 vss g1 vss j1 vss l1 vss n1 vss ab1 vss ae1 vss b2 vss d2 vss t2 vss aa2 vss ae2 vss h3 vss k3 vss m3 vss af3 vss ah3 vss d4 vss j4 vss l4 vss n4 vss r4 vss af4 vss ah4 vss j5 vss l5 vss n5 vss ab5 vss ad5 vss ae5 table 147.ballout by signal name (mobile only) ball name ball # vss ag5 vss aj5 vss c6 vss k6 vss n6 vss ab6 vss ae6 vss ag6 vss f7 vss k7 vss aa7 vss b8 vss e9 vss g10 vss b11 vss n11 vss r11 vss d12 vss m12 vss n12 vss p12 vss r12 vss t12 vss u12 vss ae12 vss g13 vss l13 vss m13 vss n13 vss p13 vss r13 vss t13 vss u13 vss v13 vss m14 vss n14 vss p14 vss r14 vss t14 table 147.ballout by signal name (mobile only) ball name ball # intel ? ich8 family datasheet 817 ballout definition vss u14 vss af14 vss f15 vss l15 vss m15 vss n15 vss p15 vss r15 vss t15 vss u15 vss v15 vss m16 vss n16 vss p16 vss r16 vss t16 vss u16 vss af16 vss ah16 vss b17 vss m17 vss n17 vss p17 vss r17 vss t17 vss u17 vss ad17 vss n18 vss r18 vss af18 vss g19 vss ad20 vss e21 vss ah22 vss a23 vss g23 vss k23 vss m23 vss p23 table 147.ballout by signal name (mobile only) ball name ball # vss u23 vss ab23 vss e24 vss ab24 vss ah24 vss g25 vss h25 vss j25 vss ac25 vss g26 vss j26 vss l26 vss n26 vss u26 vss ac26 vss ah26 vss g27 vss j27 vss l27 vss n27 vss u27 vss ac27 vss f28 vss h28 vss k28 vss m28 vss p28 vss r28 vss v28 vss ad28 vss f29 vss h29 vss k29 vss m29 vss p29 vss v29 vss ad29 vss w2 vss y4 table 147.ballout by signal name (mobile only) ball name ball # vss w24 vss w26 vss w27 vss y28 vss y29 vss af28 vss ad1 vss a25 vss_nctf a1 vss_nctf a2 vss_nctf ah1 vss_nctf b1 vss_nctf aj1 vss_nctf aj2 vss_nctf a28 vss_nctf aj28 vss_nctf a29 vss_nctf b29 vss_nctf ah29 vss_nctf aj29 wake# ae17 wol_en/gpio9 ag19 table 147.ballout by signal name (mobile only) ball name ball # ballout definition 818 intel ? ich8 family datasheet intel ? ich8 family datasheet 819 electrical characteristics 23 electrical characteristics this chapter contains the dc and ac charac teristics for the ich8. ac timing diagrams are included. 23.1 thermal specifications refer to the intel ? i/o controller hub (ich8) thermal design guidelines document for ich8 thermal information. 23.2 absolute maximum ratings4 table 148. intel ? ich8 absolute maximum ratings parameter maximum limits voltage on any 3.3 v pin with respec t to ground -0.5 to vcc3_3 + 0.5 v voltage on any 5 v tolerant pin with respect to ground (v5ref = 5 v) -0.5 to v5ref + 0.5 v 1.05 v supply voltage with respect to vss -0.5 to 2.1 v 1.25 v supply voltage with respect to vss -0.5v to 2.1v 1.5 v supply voltage with respect to vss -0.5 to 2.1 v 3.3 v supply voltage with respect to vss -0.5 to 4.6 v 5.0 v supply voltage with respect to vss -0.5 to 5.5 v v_cpu_io supply voltage with respect to vss -0.5 to 2.1 v electrical characteristics 820 intel ? ich8 family datasheet 23.3 dc characteristics notes: 1. internal voltage regulators should power these wells inside the intel ? ich8, and the current for these ra ils are accounted for in the sourcing voltage rail curre nt requirements. 2. only the g3 state of this rail is show n to provide an estimate of battery life. 3. icc (rtc) data is taken with vccrtc at 3.0v while the system is in a mechanical off (g3) state at room temperature. 4. the current for this rail in s3 and s4/s5 as sumes that the integrated lan is running at 10/100. 5. the current for this rail was me asured with vcchda set to 3.3 v 6. the current for this rail was me asured with vccdmi set to 1.25 v 7. system configuration for these measru ments included 6 sata gen. 2 devices table 149. dc current charac teristics (desktop only) power plane maximum power consumption symbol s0 s3 s4/s5 g3 v5ref 1 ma na na na v5refsus 1 ma 1 ma 1 ma na vcc3_3 278 ma na na na vccsus3_3 177 ma 44 ma 44 ma na vcchda 5 32 ma na na na vccsushda 5 32 ma 1 ma 1 ma na vccglan3_3 1 ma na na na vccglan1_5 80 ma na na na vcclan3_3 18 ma 50 ma 50 ma na vcclan1_05 1,4 powered by vcc1_05 in s0 powered by vcclan3_3 in s3 powered by vcclan3_3 in s4/s5 na vcccl3_3 18 ma 64 ma 64 ma na vcccl1_5 1 powered by vcc1_5_a in s0 powered by vcccl3_3 in s3 powered by vcccl3_3 in s4/s5 na vcccl1_05 1 powered by vcc1_05 in s0 powered by vcccl3_3 in s3 powered by vcccl3_3 in s4/s5 na vcc1_5_a 7 1.56 a na na na vcc1_5_b 657 ma na na na vccsus1_5 1 powered by vcc1_5_a in s0 powered by vccsus3_3 in s3 powered by vccsus3_3 in s4/s5 na vcc1_05 1.13 a na na na vccsus1_05 1 powered by vcc1_05 in s0 powered by vccsus3_3 in s3 powered by vccsus3_3 in s4/s5 na vccrtc 2,3 na na na 6 ua vccdmi 6 50 ma na na na v_cpu_io 1 ma na na na vccglanpll 23 ma na na na vccusbpll 10 ma na na na vccdmipll 23 ma na na na vccsatapll 47 ma na na na intel ? ich8 family datasheet 821 electrical characteristics notes: 1. internal voltage regulators should power these wells inside the intel ? ich8m. 2. only the g3 state of this rail is show n to provide an estimate of battery life. 3. icc (rtc) data is taken with vccrtc at 3.0 v while the system is in a mechanical off (g3) state at room temperature. 4. the current for this rail in s3 and s4/s5 as sumes that the integrated lan is running at 10/100. 5. the current for this rail was measured with vcchda and vccsushda se to 1.5 v 6. the current for this rail was meas ured with vccdmi set to 1.25 v table 150. dc current char acteristics (mobile only) power plane maximum power consumption symbol s0 s3 s4/s5 g3 v5ref 1 ma na na na v5refsus 1 ma 1 ma 1 ma na vcc3_3 442 ma na na na vccsus3_3 177 ma 44 ma 44 ma na vcchda 5 32 ma na na na vccsushda 5 11 ma 1 ma 1 ma na vccglan3_3 1 ma na na na vccglan1_5 80 ma na na na vcclan3_3 19 ma 51 ma 51 ma na vcclan1_05 1,4 powered by vcc1_05 powered by vcclan3_3 powered by vcclan3_3 na vcccl3_3 19 ma 63 ma 63 ma na vcccl1_5 1 powered by vcc1_5_a powered by vcccl3_3 powered by vcccl3_3 na vcccl1_05 1 powered by vcc1_05 powered by vcccl3_3 powered by vcccl3_3 na vcc1_5_a 1.08 a na na na vcc1_5_b 657 ma na na na vccsus1_5 1 powered by vcc1_5_a powered by vccsus3_3 powered by vccsus3_3 na vcc1_05 1.13 a na na na vccsus1_05 1 powered by vcc1_05 powered by vccsus3_3 powered by vccsus3_3 na vccrtc 2,3 na na na 6 ua vccdmi 6 50 ma na na na v_cpu_io 1 ma na na na vccglanpll 23 ma na na na vccusbpll 10 ma na na na vccdmipll 23 ma na na na vccsatapll 47 ma na na na electrical characteristics 822 intel ? ich8 family datasheet table 151 to table 155 should be considered the functional operating range. table 151. dc characteristic input signal association (sheet 1 of 2) symbol associated signals v ih1 /v il1 (5v tolerant) pci signals: ad[31:0], c/be[3:0]#, devsel#, frame#, irdy#, par, perr#, plock#, req0#, req[3:1]#/gpio[54, 52, 50], serr#, stop#, trdy# interrupt signals: pirq[d:a]#, pirq[h:e]#/gpio[5:2] v ih2 /v il2 gigabit lan connect signals: glan_rx[p,n] v ih3 /v il3 clock signals: clk48 power management signals: mch_sync#, thrm#, vrmpwrgd, lan_rst#, clprwok mobile only: bmbusy#/gpio0, clkrun# sata signals: desktop: satagp[5:4], satagp[3:0]/gpio[37,36,19,21], sataclkreq#/gpio[35] mobile: satagp[2,0]/gpio[36,21], sataclkreq#/gpio[35] intel ? high definition audio signals: hda_dock_en#/gpio33 (mobile only) interrupt signals: serirq processor signals: rcin#, a20gate usb signals: oc[9:8]#, oc[7:5]#/gpio[31:29]#, oc[4:1]#/gpio[43:40], oc[0]# gpio signals: desktop: gpio [55,53,51,48,39,38,33,32,22,20,18,17,16,7,6,1,0] mobile: gpio49/cpupwrgd, gpio[55,53,51, 48,39,38,32,22,20,18,17,16, 7, 6,1] strap signals: spkr, sataled# (strap purposes only) v ih4 /v il4 clock signals: clk14, pciclk lpc/firmware hub signals: lad[3:0]/fwh[3:0], ldrq0#, ldrq1#/gpio23 pci signals: pme# spi signals: spi_cs[1:0]#, spi_miso v ih5 /v il5 smbus signals: smbclk, smbdata, smbalert#/gpio11 system manageme nt signals: smlink[1:0], linkalert# v ih6 /v il6 lan signals: glan_clk, lan_rxd[2:0] v ih7 /v il7 processor signals: ferr#, thrmtrip#, cpupwrgd/gpio49 v imin8 /v imax8 pci express* data rx signals: per[p,n][6:1] v ih9 /v il9 real time cl ock signals: rtcx1 v imin10 /v imax10 sata signals: desktop: sata[5:0]rx[p,n] mobile: sata[2:0]rx[p,n] v ih11 /v il11 i ntel ? high definition audio signals: hda_sdin[3:0], hda_dock_rst#/gpio34 (mobile only) strap signals: hda_sdout, hda_sync (strap purposes only) gpio signals : gpio34 (desktop only) note: see v il_hda /v ih_hda for high definition audio low voltage mode v ih12 /v il12 / v cross(abs) clock signals: dmi_clkn, dmi_clkp, sata_clkn, sata_clkp v ih13 /v il13 power management signals: desktop: pwrbtn#, ri#, sys_reset#, wake# mobile: batlow#, pwrbtn#, ri#, sys_reset#, wake# system management signal: alert#/gpio10, mem_led/gpio24, netdetect/gpio14, wol_en/gpio9 intel quick resume technology signals (ich8dh only): qrt_state[1:0]/ gpio[28:27] gpio signals : gpio[26:24, 15:12, 10:8] other signals: tp0 intel ? ich8 family datasheet 823 electrical characteristics v ih14 /v il14 power management signals: pwrok, rsmrst#, rtcrst# system management signals: intruder# other signals: intvrmen, lan100_slp v ih15 /v il15 (5 v tolerant) (mobile only) interrupt signal: ideirq v ih16 /v il1 (desktop only) intel ? quiet system technology: tach[3:0]/gpio[17,7,6,1] v ih17 /v il17 controller link: cl_clk0, cl_data0 mobile only: cl_clk1, cl_data1 v+/v-/v hys / v thravg /v ring (5 v tolerant) (mobile only) ide signals: dd[15:0], ddreq, iordy for ultra dma mode 4 and lower these sign als follow the dc characteristics for v ih15 / v il15 v di / v cm / v se (5 v tolerant) usb signals: usbp[9:0][p,n] (low-speed and full-speed) v hssq / v hsdsc / v hscm (5 v tolerant) usb signals: usbp[9:0][p,n] (in high-speed mode) v ih_hda / v il_hda intel ? high definition audio signals: hda_sdin[3:0], hda_dock_rst#/gpio34 (mobile only) strap signals: hda_sdout, hda_sync (strap purposes only) note: only applies when running in low voltage mode (1.5 v) v ih_sst /v il_sst sst signal: sst v ih_peci /v il_peci peci signal: peci (desktop only) table 152. dc input characteristics (sheet 1 of 3) symbol parameter min max unit notes v il1 input low voltage ?0.5 0.3(vcc3_3) v v ih1 input high voltage 0.5 (vcc3_3) v5ref + 0.5 v v il2 minimum input voltage 200 mvdiff p-p 5 v ih2 maximum input voltage 1350 mvdiff p-p 5 v il3 input low voltage ?0.5 0.8 v v ih3 input high voltage 2.0 vcc3_3 + 0.5 v v il4 input low voltage ?0.5 0.3(vcc3_3) v v ih4 input high voltage 0.5(vcc3_3) vcc3_3 + 0.5 v v il5 input low voltage ?0.5 0.8 v v ih5 input high voltage 2 .1 vccsus3_3 + 0.5 v v il6 input low voltage -0.5 0.3(vcc3_3) v v ih6 input high voltage 0.6(vcc3_3) vcc3_3 + 0.5 v table 151. dc characteri stic input signal association (sheet 2 of 2) symbol associated signals electrical characteristics 824 intel ? ich8 family datasheet v il7 input low voltage ?0.5 0.58(v_cpu_io) v v ih7 input high voltage 0.73(v_cpu_io) v_cpu_io + 0.5 v v imin8 minimum input voltage 175 mvdiff p-p 4 v imax8 maximum input voltage 1200 mvdiff p-p 4 v il9 input low voltage ?0.5 0.10 v v ih9 input high voltage 0.40 1.2 v v imin10- g en 1 i minimum input voltage - 1.5 gb/s internal sata 325 mvdiff p-p 6 v imax10- g en 1 i maximum input voltage - 1.5 gb/s internal sata 600 mvdiff p-p 6 v imin10- g en 1 m minimum input voltage - 3.0 gb/s esata 240 mvdiff p-p 6 v imax10- g en 1 m maximum input voltage - 3.0 gb/s esata 600 mvdiff p-p 6 v imin10- g en 2 i minimum input voltage - 1.5 gb/s internal sata 275 mvdiff p-p 6 v imax10- g en 2 i maximum input voltage - 1.5 gb/s internal sata 750 mvdiff p-p 6 v imin10- g en 2 m minimum input voltage - 3.0 gb/s esata 240 mvdiff p-p 6 v imax10- g en 2 m maximum input voltage - 3.0 gb/s esata 750 mvdiff p-p 6 v il11 input low voltage ?0.5 0.35(vcc3_3) v v ih11 input high voltage 0.65(vcc3_3) vcc3_3 + 0.5 v v il12 input low voltage -0.150 0.150 v v ih12 input high voltage 0.660 0.850 v v il13 input low voltage ?0.5 0.8 v v ih13 input high voltage 2.0 vccsus3_3 + 0.5 v v il14 input low voltage ?0.5 0.78 v v ih14 input high voltage 2.0 vccrtc + 0.5 v 7 v il15 input low voltage ? 0.5 0.8 v v ih15 input high voltage 2.0 v5ref + 0.5 v v il16 input low voltage 0.3(vcc3_3) v ih16 input high voltage 0.6(vcc3_3) v il17 input low voltage ? 0.3 (cl_vref - 0.085) v v ih17 input high voltage (cl_vref + 0.085) 1.2 v v cross(abs) absolute crossing point 0.250 0.550 v v+ low to high input threshold 1.5 2.0 v 9 v ? high to low input threshold 1.0 1.5 v 9 table 152. dc input charac teristics (she et 2 of 3) symbol parameter min max unit notes intel ? ich8 family datasheet 825 electrical characteristics notes: 1. v di = | usbpx[p] ? usbpx[n] | 2. includes v di range 3. applies to low-speed/high-speed usb 4. pci express mvdiff p-p = 2*|petp[x] - petn[x]| 5. glan mvdiff p-p = 2* |glan_rxp - glan_rxn| 6. sata vdiff, rx (v imax10/min10 ) is measured at the sata co nnector on the receiver side (generally, the motherboard connector), wh ere sata mvdiff p-p = 2*|sata[x]rxp ? sata[x]rxn| 7. vccrtc is the voltage applied to the vccrtc we ll of the ich8. when the system is in a g3 state, this is generally supplie d by the coin cell battery, but for s5 and greater, this is generally vccsus3_3. 8. cl_vref = 0.27 (vcccl1_5). cl_vref0 appl ies to desktop configurations. cl_vref1 applies to mobile configurations. 9. applies to ultra dma modes greater than ultra dma mode 4 10. this is an ac characteri stic that represents transi ent values for these signals v hys difference between input thresholds: (v+current value) ? (v ? current value) 320 mv 9 v thravg average of thresholds: ((v+current value) + (v ? current value))/2 1.3 1.7 v 9 v ring ac voltage at re cipient connector ? 1 6 v 9,10 v di differential input sensitivity 0.2 v 1,3 v cm differential common mo de range 0.8 2.5 v 2,3 v se single-ended receiver threshold 0.8 2.0 v 3 v hssq hs squelch detection threshold 100 150 mv 3 v hsdsc hs disconnect detection threshold 525 625 mv 3 v hscm hs data signaling common mode voltage range ?50 500 mv 3 v il_hda input low voltage 0.4(vcc_hda) v v ih_hda input high voltage 0.6(vcc_hda) v v il_sst input low voltage -0.5 0.4 v v ih_sst input high voltage 1.1 vcc + 0.5 v v il_peci (desktop only) input low voltage -0.5 0.275(v_cpu_io) v v ih_peci (desktop only) input high voltage 0.725(v_cpu_io) v_cpu_io + 0.5 v table 152. dc input characteristics (sheet 3 of 3) symbol parameter min max unit notes electrical characteristics 826 intel ? ich8 family datasheet table 153. dc characteristic output signal association (sheet 1 of 2) symbol associated signals v oh1 /v ol1 processor signals: desktop: a20m#, cpuslp#, ignne#, init#, intr, nmi, smi#, stpclk#, cpupwrgd/gpio[49] mobile: a20m#, dpslp#, ignne#, init#, intr, nmi, smi#, stpclk#, cpupwrgd/gpio[49] v oh2 /v ol2 pci signals: ad[31:0], c/be[3:0]#, devsel#, frame#, irdy#, par, perr#, plock#, serr# (1) , stop#, trdy# intel ? high definition audio signals: hda_rst#, hda_sdout, hda_sync, hda_bit_clk note: see v oh_hda /v ol_hda for high definition audio low voltage mode v oh3 /v ol3 smbus signals: smbclk (1) , smbdata (1) system management signals: smlink[1:0] (1) , linkalert#(1) gpio signals: gpio11/smbalert (1) v oh4 /v ol4 power management signals: desktop: slp_s3#, slp_s4#, slp_s5#, slp_m#, s4_state#/gpio26, susclk, sus_stat#/lpcpd, ck_pwrgd mobile: dprslpvr, slp_s3#, slp_s4#, slp_s5#, slp_m#, s4_state#/gpio26, susc lk, sus_stat/lpcpd, ck_pwrgd# gpio signals: desktop: gpio[39, 38, 37, 36, 33, 32, 21, 20, 19,18, 16, 7, 6,0] mobile:gpio[39, 38, 37, 36, 21, 20, 19,18, 7, 6,0] intel high definition audio signals: hda_dock_en#/gpio33 (mobile only) other signals: spkr interrupt signals: serirq sata signal: sataled#, sataclkreq#/gpio35, sload/gpio38, sdataout[1:0]/gpio[48,39], sdataout v oh5 /v ol5 usb signals : usbp[9:0][p,n] in low-sp eed and full-speed modes v omin6 /v omax6 pci express* data tx signals: pet[p,n][6:1] v omin7 /v omax7 sata signals: desktop: sata[5:0]tx[p,n] mobile: sata[2,0]tx[p,n] v oh8 /v ol8 lpc/firmware hub signals: lad[3:0]/fwh[3:0], lframe#/fwh[4] power management signal: pltrst# pci signals: pcirst#, gnt[3:1]#/gpio[55,53,51], gnt[0]#, pme# (1) gpio signals: desktop: gpio[54, 52, 50, 34, 23, 22, 5, 4, 3, 2, 1] mobile: gpio[54, 52, 50, 23, 22, 5, 4, 3, 2, 1] intel high definition audio signals: hda_dock_rst#/gpio34 (mobile only) spi signals: spi_cs[1:0]#, spi_mosi, spi_clk processor inte rface signal: init3_3v# (desktop only) lan signals: lan_rstsync, lan_txd[2:0] interrupt signals: pirq[h:e] #(1) /gpio[5:2] v oh9 /v ol9 power management signals: mobile: stp_cpu#, stp_pci# gpio signals: gpio[25, 15, 13, 12, 8], gpio[43:40]/ oc[4:1]#,gpio[31:29]/oc[7:5]#, gpio 9/wol_en, gpio10/ alert#gpio1 4/netdetect, gpio24/mem_led intel quick resume technology signals (ich8dh only): qrt_state[1:0] v omin10 /v omax10 gigabit lan connect signals: glan_tx[p,n] intel ? ich8 family datasheet 827 electrical characteristics note: 1. these signals are open drain. v oh11 /v ol11 ide signals (mobile only): da[2:0], dcs[3,1]#, ddack#, dd[15:0], dior#, diow# v hsoi v hsoh v hsol v chirpj v chirpk usb signals: usbp[9:0][p:n] in high-speed mode v oh_hda /v ol_hda intel ? high definition audio signals: hda_rst#, hda_sdout, hda_sync note: only applies when running in low voltage mode (1.5 v) v oh_pwm / v ol_pwm fan speed control pwm: pwm[2:0] (1) v oh_cl1 /v ol_cl1 link controller signals: cl_clk0, cl_data0 mobile only: cl_clk1, cl_data1 v oh_cl2 /v ol_cl2 link controller signals: cl_rst# v oh_sst /v ol_sst sst signal: sst v oh_peci / v ol_peci peci signal: peci (desktop only) table 153. dc characterist ic output signal assoc iation (sheet 2 of 2) symbol associated signals electrical characteristics 828 intel ? ich8 family datasheet table 154. dc output characteristics (sheet 1 of 2) symbol parameter min max unit i ol / i oh notes v ol1 output low voltage ? 0.255 v 3 ma 4 v oh1 output high voltage v_cpu_io - 0.3 ? v -3 ma v ol2 output low voltage ? 0.1(vcc3_3) v 1.5 ma v oh2 output high voltage 0.9(vcc3_3) ? v -0.5 ma v ol3 output low voltage ? 0.4 v 4 ma v oh3 output high voltage vccsus3_3 - 0.5 ? v -2 ma 1 v ol4 output low voltage ? 0.4 v 6 ma v oh4 output high voltage vcc3_3 - 0.5 ? v -2 ma v ol5 output low voltage ? 0.4 v 5 ma v oh5 output high voltage vcc3_3 ? 0.5 ? v -2 ma v omin6 minimum output voltage 800 ? mvdif fp-p 2 v omax6 maximum output voltage ? 1200 mvdif fp-p 2 v omin7- gen1i,m minimum output voltage - 1.5 gb/s internal sata and esata 400 mvdif fp-p 3 v omax7- gen1i,m maximum output voltage 1.5 gb/s internal sata and esata 600 mvdif fp-p 3 v omin7- gen2i,m minimum output voltage 3.0 gb/s internal sata and esata 400 mvdif fp-p 3 v omax7- gen2i,m maximum output voltage 3.0 gb/s internal sata and esata 700 mvdif fp-p 3 v ol8 output low voltage ? 0.1(vcc3_3) v 1.5 ma v oh8 output high voltage 0.9(vcc3_3) v -0.5 ma 1 v ol9 output low voltage ? 0.4 v 6 ma v oh9 output high voltage vccsus3_3 - 0.5 ? v -0.5 ma v omin10 minimum output voltage 750 ? mvdif fp-p 6 v omax10 maximum output voltage ? 1350 mvdif fp-p 6 v ol11 output low voltage ? 0.51 v 6 ma v oh11 output high voltage vcc3_3 ? 0.51 ? v -6 ma v hsoi hs idle level ?10.0 10.0 mv v hsoh hs data signaling high 360 440 mv v hsol hs data signaling low ?10.0 10.0 mv v chirpj chirp j level 700 1100 mv v chirpk chirp k level ?900 ?500 mv intel ? ich8 family datasheet 829 electrical characteristics notes: 1. the serr#, pirq[h:a], smbdata, smbclk , linkalert#, smlink[1:0], and pwm[2:0] signal has an open drain driver and satale d# has an open collector driver, and the v oh specification does not apply. this signal must have external pull up resistor. 2. pci express mvdiff p-p = 2*|petp[x] - petn[x]| 3. sata vdiff, tx (v omin7 /v omax7 ) is measured at the sata co nnector on the transmit side (generally, the motherboard connector), wh ere sata mvdiff p-p = 2*|sata[x]txp - sata[x]txn| 4. maximum iol for cpupwrgd is 12ma for shor t durations (<500ms per 1.5 s) and 9ma for long durations. 5. for init3_3v only, for low curre nt devices, the following applie s: vol5 max is 0.15 v at an iol5 of 2 ma. 6. glan mvdiff p-p = 2*|glan_txp ? glan_txn| v ol_hda (mobile only) output low voltage ? 0.1(vcchda) v 1.5 ma v oh_hda (mobile only) output high voltage 0.9(vcc_hda) ? v -0.5 ma v ol_pwm output low voltage ? 0.4 v 8 ma v oh_pwm output high voltage ? ? 1 v ol_cl1 output low voltage ? 0.1 v 1 ma v oh_cl1 output high voltage 0.485(vcccl1_5) ? v v ol_cl2 output low voltage ? 0.1(vcccl1_5) v 1.5 ma v oh_cl2 output high voltage 0.9(vcccl1_5) ? v -1.5 ma v ol_sst output low voltage ? 0.3 v 0.5 ma v oh_sst output high voltage 1.1 ? v -6 ma v ol_peci output low voltage ? 0.25(v_cpu_io) v 0.5 ma v oh_peci output high voltage 0 .75(v_cpu_io) ? -6 ma table 154. dc output charac teristics (she et 2 of 2) symbol parameter min max unit i ol / i oh notes electrical characteristics 830 intel ? ich8 family datasheet table 155. other dc charac teristics (she et 1 of 2) symbol parameter min nom max unit notes v_cpu_io (desktop only) processor interface 1.14 ? 1.26 v 1 v_cpu_io (mobile only) processor interface 0.945 ? 1.155 v 1 v_cpu_io (server only) processor interface 1.18 ? 1.3 v 1 v5ref ich8 core well reference voltage 4.75 5 5.25 v 1 cl_vref0, cl_vref1 controller link reference voltage 0.385 0.405 0.425 v 1 vcc3_3 i/o buffer voltage 3.135 3.3 3.465 v 1 vcc1_5_a, vcc1_5_b, vccusbpll, vccsatapll, vccdmipll vccglanpll internal logic and i/o buffer voltage 1.425 1.5 1.575 v 1 v5ref_sus suspend well reference voltage 4.75 5 5.25 v 1 vccsus3_3 suspend well i/o buffer voltage 3.135 3.3 3.465 v 1 vcc1_05 internal logic voltage 0.998 1.05 1.102 v 1 vccsus1_05 suspend well logic voltage 0.998 1.05 1.102 v 1 vccsus1_5 suspend well i/o buffer voltage 1.425 1.5 1.575 v 1 vcchda high definition audio controller core voltage 3.135 3.3 3.465 v 1 vcchda (low voltage 1.5 v) high definition audio controller low voltage mode core voltage 1.425 1.5 1.575 v 1 vcc_dmi dmi buffer voltage 1.186 ? 1.312 v same as vcc1_5_a if powered by 1.5 v. vcclan3_3 lan controller i/o buffer voltage 3.135 3.3 3.465 v 1 vcclan1_05 lan controller logic voltage 0.998 1.05 1.102 v 1 vccglan1_5 gigabit lan transmitter and receiver voltage 1.425 1.5 1.575 v 1 vccglan3_3 gigabit lan internal logic and i/o buffer voltage 3.135 3.3 3.465 v 1 vcccl3_3 controller link buffer voltage 3.135 ? 3.465 v 1 vccrtc (g3?s0) battery voltage 2 ? 3.465 v 1 vccsushda high definition audio controller suspend voltage 3.135 3.3 3.465 v 1 intel ? ich8 family datasheet 831 electrical characteristics notes: 1. the i/o buffer supply voltage is measured at the ich8 package pins. the tolerances shown in table 155 are inclusive of all noise from dc up to 20 mhz. in testing, the voltage rails should be measured with a band width limited os cilloscope that has a rolloff of 3 db/decade above 20 mhz. 2. includes clk14, clk48, glan_clk, and pciclk. vccsushda (low voltage) intel high definition audio controller low voltage mode suspend voltage 1.425 1.5 1.575 v 1 vcccl1_05 controller link logic voltage 0.998 ? 1.102 v 1 vcccl1_5 controller link logic voltage 1.425 ? 1.575 v 1 v di differential input sensitivity 0.2 ? ? v |(usbpx+,us bpx?)| v cm differential common mode range 0.8 ? 2.5 v includes v di v crs output signal crossover voltage 1.3 ? 2.0 v v se single ended rcvr threshold 0.8 ? 2.0 v i li1 ata input leakage current ?200 ? 200 a (0 v < v in < 5v) i li2 pci_3v hi-z state data line leakage ?10 ? 10 a (0 v < vin < vcc3_3) i li3 pci_5v hi-z state data line leakage ?70 ? 70 a max v in = 2.7 v min v in = 0.5 v i li4 input leakage current ? clock signals ?100 ? +100 a 2 v il tach input low voltage ? ? 0.3(vcc3_3) v ih tach input high voltage 0.6(vcc3_3) ? - c in input capacitance ? all other ? ? 12 pf f c = 1 mhz c out output capacitance ? ? 12 pf f c = 1 mhz c i/o i/o capacitance ? ? 12 pf f c = 1 mhz typical value c l xtal1 6 pf c l xtal2 6 pf table 155. other dc characteristics (sheet 2 of 2) symbol parameter min nom max unit notes electrical characteristics 832 intel ? ich8 family datasheet 23.4 ac characteristics 1 table 156. clock timings (sheet 1 of 2) sym parameter min max unit notes figure pci clock (pciclk) t1 period 30 33.3 ns 22 t2 high time 12 ? ns 22 t3 low time 12 ? ns 22 t4 rise time ? 3 ns 22 t5 fall time ? 3 ns 22 14 mhz clock (clk14) t6 period 67 70 ns 22 t7 high time 20 ? ns 22 t8 low time 20 ? ns 22 t41 rising edge rate 1.0 4.0 v/ns 5 t42 falling edge rate 1.0 4.0 v/ns 5 48 mhz clock (clk48) f clk48 operating frequency 48.00 0 ? mhz 1 t9 frequency tolerance ? 100 ppm t10 high time 7 ? ns 22 t11 low time 7 ? ns 22 t12 rise time ? 1.2 ns 22 t13 fall time ? 1.2 ns 22 smbus clock (smbclk) f smb operating frequency 10 100 khz t18 high time 4.0 50 us 2 37 t19 low time 4.7 ? us 37 t20 rise time ? 1000 ns 37 t21 fall time ? 300 ns 37 hda_bit_clk (intel ? high definition audio) fhda operating frequency 24.0 mhz frequency tolerance ? 100 ppm t26a input jitter (refer to clock chip specification) ? 300 ppm t27a high time (measured at 0.75vcc) 18.75 22.91 ns 22 t28a low time (measured at 0.35vcc) 18.75 22.91 ns 22 intel ? ich8 family datasheet 833 electrical characteristics notes: 1. the clk48 expects a 40/60% duty cycle. 2. the maximum high time (t18 max) provide a simple assured method for devices to detect bus idle conditions. 3. bitclk rise and fall times are measured from 10%vdd and 90%vdd. 4. susclk duty cycle can range from 30% minimum to 70% maximum. 5. clk14 edge rates in a system as measured from 0.8 v to 2.0 v. 6. the active frequency can be 5 mhz, 50 mhz or 62.5 mhz depe nding on the interface speed. dynamic changes of the normal op erating frequency are not allowed. sata clock (sata_clkp, sata_clkn) / dmi clock (dmi_clkp, dmi_clkn) t36 period 9.997 10.0533 ns t37 rise time 175 700 ps t38 fall time 175 700 ps tsatasl slew rate 2.5 8 v/ns suspend clock (susclk) f susclk operating frequency 32 khz 4 t39 high time 10 ? us 4 t39a low time 10 ? us 4 gigabit internet clock (glan_clk) tglanclk operating frequency 5 62.5 mhz 6 tglanhi high time 8.5 ? ns tglanlo low time 8.5 ? ns tglansl slew rate 1.0 4 v/ns fan speed controller fpwm pwm operating frequency 10 28,000 hz table 156. clock timings (sheet 2 of 2) sym parameter min max unit notes figure electrical characteristics 834 intel ? ich8 family datasheet notes: 1. refer to note 3 of table 4-4 in section 4.2.2.2 and note 2 of table 4-6 in section 4.2.3.2 of the pci local bus specification, revision 2.3 for measurement details. table 157. pci interface timing sym parameter min max units notes figure t40 ad[31:0] valid delay 2 11 ns 1 23 t41 ad[31:0] setup time to pciclk rising 7 ? ns 24 t42 ad[31:0] hold time from pciclk rising 0 ? ns 24 t43 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, devsel# valid delay from pciclk rising 2 11 ns 1 23 t44 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, idsel, devsel# output enable delay from pciclk rising 2 ? ns 27 t45 c/be[3:0]#, frame#, trdy#, irdy#, stop#, perr#, plock#, devsel#, gnt[a:b]# float delay from pciclk rising 2 28 ns 25 t46 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, setup time to pciclk rising 7 ? ns 24 t47 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, req[a:b]# hold time from pclkin rising 0 ? ns 24 t48 pcirst# low pulse width 1 ms 26 t49 gnt[3:0]# valid delay from pciclk rising 2 12 ns t50 req[3:0]# setup time to pciclk rising 12 ? ns intel ? ich8 family datasheet 835 electrical characteristics table 158. ide pio mode timings (mobile only) sym parameter mode 0 (ns) mode 1 (ns) mode 2 (ns) mode 3 (ns) mode 4 (ns) figure t60 cycle time (min) 600 383 240 180 120 28 t61 addr setup to diow#/ dior# (min) 70 50 30 30 25 28 t62 dirw#/dior# (min) 165 125 100 80 70 28 t62i diow#/dior# recovery time (min) ? ? ? 70 25 28 t63 diow# data setup (min) 60 45 30 30 20 28 t64 diow# data hold (min) 30 20 15 10 10 28 t65 dior# data setup (min) 50 35 20 20 20 28 t66 dior# data hold (min) 5 5 5 5 5 28 t66z dior# data tristate (max) 30 30 30 30 30 28 t69 diow#/dior# to address valid hold (min) 20 15 10 10 10 28 t60rd read data valid to iordy active (min) 0 0 0 0 0 28 t60a iordy setup 35 35 35 35 35 28 t60b iordy pulse width (max) 1250 1250 1250 1250 1250 28 t60c iordy assertion to release (max) 5 5 5 5 5 28 electrical characteristics 836 intel ? ich8 family datasheet table 159. ide multiword dma timings (mobile only) sym parameter mode 0 (ns) mode 1 (ns) mode 2 (ns) figure t70 cycle time (min) 480 150 120 29 t70d dior#/diow# (min) 215 80 70 29 t70e dior# data access (max) 150 60 50 29 t70f dior# data hold (min) 5 5 5 29 t70g dior#/diow# data setup (min) 100 30 20 29 t70h diow# data hold (min) 20 15 10 29 t70i ddack# to dior#/diow# setup (min) 0 0 0 29 t70j dior#/diow# to ddack# hold (min) 20 5 5 29 t70kr dior# negated pulse width (min) 50 50 25 29 t70kw diow# negated pulse width (min) 215 50 25 29 t70lr dior# to ddreq delay (max) 120 40 35 29 t70lw diow# to ddreq delay (max) 40 40 35 29 t70m dcs1#/dcs3# valid to dior#/diow# (min) 50 30 25 29 t70n dcs1#/dcs3# hold (min) 15 10 10 29 t70z ddack# to tristate (max) 20 25 25 29 table 160. ultra ata timing (mode 0, mode 1, mode 2) (sheet 1 of 3) (mobile only) sym parameter (1) mode 0 (ns) mode 1 (ns) mode 2 (ns) measuring location figure min max min max min max t80 sustained cycle time (t2cyctyp) 240 160 120 sender connector t81 cycle time (tcyc) 112 ? 73 ? 54 ? end recipient connector 31 t82 two cycle time (t2cyc) 230 ? 153 ? 115 ? sender connector 31 t83a data setup time (tds) 15 ? 10 ? 7 ? recipient connector 31 t83b recipient ic data setup time (from data valid until strobe edge) (see note 2) (tdsic) 14. 7 ? 9.7 ? 6.8 ? ich8 ball t84a data hold time (tdh) 5 ? 5 ? 5 ? recipient connector 31 intel ? ich8 family datasheet 837 electrical characteristics t84b recipient ic data hold time (from strobe edge until data may become invalid) (see note 2) (tdhic) 4.8 ? 4.8 ? 4.8 ? ich8 ball t85a data valid setup time (tdvs) 70 ? 48 ? 31 ? sender connector 31 t85b sender ic data valid setup time (from data valid until strobe edge) (see note 2) (tdvsic) 72. 9 50. 9 33. 9 ? ich8 ball t86a data valid hold time (tdvh) 6.2 ? 6.2 ? 6.2 ? sender connector 31 t86b sender ic data valid hold time (from strobe edge until data may become invalid) (see note 2) (tdvhic) 9 ? 9 ? 9 ? ich8 ball t87 limited interlock time (tli) 0 150 0 150 0 150 see note 2 33 t88 interlock time w/ minimum (tmli) 20 ? 20 ? 20 ? host connector 33 t89 envelope time (tenv) 20 70 20 70 20 70 host connector 30 t90 ready to pause time (trp) 160 ? 125 ? 100 ? recipient connector 32 t91 dmack setup/hold time (tack) 20 ? 20 ? 20 ? host connector 30 , 33 t92a crc word setup time at host (tcvs) 70 ? 48 ? 31 ? host connector t92b crc word valid hold time at sender (from dmack# negation until crc may become invalid) (see note 2) (tcvh) 6.2 ? 6.2 ? 6.2 ? host connector t93 strobe output released- to-driving to the first transition of critical timing (tzfs) 0 ? 0 ? 0 ? device connector 33 t94 data output released-to- driving until the first tunisian of critical timing (tdzfs) 70 ? 48 ? 31 ? sender connector 30 t95 unlimited interlock time (tui) 0 ? 0 ? 0 ? host connector 30 table 160. ultra ata timing (mode 0, mode 1, mode 2) (sheet 2 of 3) (mobile only) sym parameter (1) mode 0 (ns) mode 1 (ns) mode 2 (ns) measuring location figure min max min max min max electrical characteristics 838 intel ? ich8 family datasheet notes: 1. the specification symbols in parenthe ses correspond to the at attachment ? 6 with packet interface (ata/atapi ? 6) specification name. 2. see the at attachment ? 6 with packet interface (ata/atapi ? 6) specification for further details on measuring th ese timing parameters. t96a maximum time allowed for output drivers to release (from asserted or negated) (taz) ? 10 10 ? 10 see note 2 t96b minimum time for drivers to assert or negate (from released) (tzad) 0 ? 0 ? 0 ? device connector t97 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy#) (trfs) ? 75 ? 70 ? 60 sender connector 30 t98a maximum time before releasing iordy (tiordyz) ? 20 ? 20 ? 20 device connector t98b minimum time before driving iordy (see note 2) (tziordy) 0 ? 0 ? 0 ? device connector t99 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) (tss) 50 ? 50 ? 50 ? sender connector 32 table 160. ultra ata timing (mode 0, mode 1, mode 2) (sheet 3 of 3) (mobile only) sym parameter (1) mode 0 (ns) mode 1 (ns) mode 2 (ns) measuring location figure min max min max min max intel ? ich8 family datasheet 839 electrical characteristics table 161. ultra ata timing (mode 3, mode 4, mode 5) (sheet 1 of 2) (mobile only) sym parameter (1) mode 3 (ns) mode 4 (ns) mode 5 (ns) measuring location figure min max min max min max t80 sustained cy cle time (t2cyctyp) 90 60 40 sender connector t81 cycle time (tcyc) 39 ? 25 ? 16. 8 ? end recipient connector 31 t82 two cycle time (t2cyc) 86 ? 57 ? 38 ? sender connector 31 t83 data setup time (tds) 7 ? 5 ? 4.0 ? recipient connector 31 t83b recipient ic data setup time (from data valid until strobe edge) (see note 2) (tdsic) 6.8 ? 4.8 ? 2.3 ? ich8 balls t84 data hold time (tdh) 5 ? 5 ? 4.6 ? recipient connector 31 t84b recipient ic data hold time (from strobe edge until data may become invalid) (see note 2) (tdhic) 4.8 ? 4.8 ? 2.8 ? ich8 balls t85 data valid setup time (tdvs) 20 ? 6.7 ? 4.8 ? sender connector 30 31 t85b sender ic data valid setup time (from data valid until strobe edge) (see note 2) (tdvsic) 22. 6 ? 9.5 ? 6.0 ? ich8 balls t86 data valid hold time (tdvh) 6.2 ? 6.2 ? 4.8 ? sender connector 30 31 t86b sender ic data valid hold time (from strobe edge until data may become invalid) (see note 2) (tdvhic) 9.0 ? 9.0 ? 6.0 ? ich8 balls t87 limited interlock time (tli) 0 100 0 100 0 75 see note 2 33 t88 interlock time w/ minimum (tmli) 20 ? 20 ? 20 ? host connector 33 t89 envelope time (tenv) 20 55 20 55 20 50 host connector 31 t90 ready to pause time (trp) 100 ? 100 ? 85 ? recipient connector 32 t91 dmack setup/hold time (tack) 20 ? 20 ? 20 ? host connector 33 t92a crc word setup time at host (tcvs) 20 ? 6.7 ? 10 ? host connector electrical characteristics 840 intel ? ich8 family datasheet notes: 1. the specification symbols in parenthe ses correspond to the at attachment ? 6 with packet interface (ata/atapi ? 6) specification name. 2. see the at attachment ? 6 with packet interface (ata/atapi ? 6) specification for further details on measuring th ese timing parameters. t92b crc word hold time at sender crc word valid hold time at sender (from dmack# negation until crc may become invalid) (see note 2) (tcvh) 6.2 ? 6.2 ? 10. 0 ? host connector t93 strobe output released-to-driving to the first transition of critical timing (tzfs) 0 ? 0 ? 35 ? device connector 33 t94 data output released- to-driving until the first transition of critical timing (tdzfs) 20. 0 ? 6.7 ? 25 ? sender connector t95 unlimited interlock time (tui) 0 ? 0 ? 0 ? host connector t96a maximum time allowed for output drivers to release (from asserted or negated) (taz) ? 10 ? 10 ? 10 see note 2 t96b drivers to assert or negate (from released) (tzad) 0 ? 0 ? 0 ? device connector t97 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy#) (trfs) ? 60 ? 60 ? 50 sender connector t98a maximum time before releasing iordy (tiordyz) ? 20 ? 20 ? 20 device connector t98b minimum time before driving iordy (see note 2) (tziordy) 0 ? 0 ? 0 ? device connector t99 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) (tss) 50 ? 50 ? 50 ? sender connector 32 table 161. ultra ata timing (mode 3, mode 4, mode 5) (sheet 2 of 2) (mobile only) sym parameter (1) mode 3 (ns) mode 4 (ns) mode 5 (ns) measuring location figure min max min max min max intel ? ich8 family datasheet 841 electrical characteristics notes: 1. driver output resistance under steady state drive is spec?d at 28 ohms at minimum and 43 at maximum. 2. timing difference between th e differential data signals. 3. measured at crossover point of differential data signals. 4. measured at 50% swing point of data signals. 5. measured from last crossover point to 50% swin g point of data line at leading edge of eop. 6. measured from 10% to 90% of the data signal. 7. full-speed data rate has minimum of 11.97 mb/s and maximum of 12.03 mb/s. 8. low-speed data rate has a minimum of 1.48 mb/s and a maximum of 1.52 mb/s. table 162. universal serial bus timing sym parameter min max units fig notes full-speed source (note 7) t100 usbpx+, usbpx- driver rise time 4 20 ns 34 1, c l = 50 pf t101 usbpx+, usbpx- driver fall time 4 20 ns 34 1, c l = 50 pf t102 source differential driver jitter to next transition for paired transitions ?3.5 ?4 3.5 4 ns ns 35 2, 3 t103 source se0 interval of eop 160 175 ns 36 4 t104 source jitter for differential transition to se0 transition ?2 5 ns 5 t105 receiver data jitter tolerance to next transition for paired transitions ?18.5 ?9 18.5 9 ns ns 35 3 t106 eop width: must accept as eop 82 ? ns 36 4 t107 width of se0 interval during differential transition ? 14 ns low-speed source (note 8) t108 usbpx+, usbpx ? driver rise time 75 300 ns 34 1, 6 c l = 50 pf c l = 350 pf t109 usbpx+, usbpx ? driver fall time 75 300 ns 34 1,6 c l = 50 pf c l = 350 pf t110 source differential driver jitter to next transition for paired transitions ?25 ?14 25 14 ns ns 35 2, 3 t111 source se0 interval of eop 1.25 1.50 s 36 4 t112 source jitter for differential transition to se0 transition ?40 100 ns 5 t113 receiver data jitter tolerance to next transition for paired transitions ?152 ?200 152 200 ns ns 35 3 t114 eop width: must accept as eop 670 ? ns 36 4 t115 width of se0 interval during differential transition ? 210 ns electrical characteristics 842 intel ? ich8 family datasheet notes: 1. 20% ? 80% at transmitter 2. 80% ? 20% at transmitter 3. as measured from 100 mv differential cros spoints of last and first edges of burst. 4. operating data period during out-of-band burst transmissions. notes: 1. a device will timeout when any clock low exceeds this value. 2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. if a slav e device exceeds this time, it is expected to release both its clock and da ta lines and reset itself. 3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. 4. t134 has a minimum timing for i 2 c of 0 ns, while the minimum timing for smbus is 300 ns. table 163. sata interface timings sym parameter min max units figure note s ui gen i operating data period 666.43 670.23 ps ui-2 gen ii operating data period (3gb/s) 333.21 335.11 ps t120 rise time 0.15 0.41 ui 1 t121 fall time 0.15 0.41 ui 2 t122 tx differential skew ? 20 ps t123 comreset 310.4 329.6 ns 3 t124 comwake transmit spacing 103.5 109.9 ns 3 t125 oob operating data period 646.67 686.67 ns 4 table 164. smbus timing sym parameter min max units fig notes t130 bus tree time between stop and start condition 4.7 ? s 37 t131 hold time after (repeated) start condition. after this period, the firs t clock is generated. 4.0 ? s 37 t132 repeated start condition setup time 4.7 ? s 37 t133 stop condition setup time 4.0 ? s 37 t134 data hold time 0 ? ns 37 4 t135 data setup time 250 ? ns 37 t136 device time out 25 35 ms 1 t137 cumulative clock low extend time (slave device) ? 25 ms 38 2 t138 cumulative clock low extend time (master device) ? 10 ms 38 3 intel ? ich8 family datasheet 843 electrical characteristics 1 table 165. intel ? high definition audio timing sym parameter min max units fig notes t143 time duration for which hd a_sdout is valid before hda_bit_clk edge. 7 ? ns 47 t144 time duration for which hda_sdout is valid after hda_bit_clk edge. 7 ? ns 47 t145 setup time for hda_sdin[3:0] at rising edge of hda_bit_clk 15 ? ns 47 t146 hold time for hda_sdin[3:0] at rising edge of hda_bit_clk 0 ? ns 47 table 166. lpc timing sym parameter min max units fig notes t150 lad[3:0] valid delay from pciclk rising 2 11 ns 23 t151 lad[3:0] output enable delay from pciclk rising 2 ? ns 27 t152 lad[3:0] float delay from pciclk rising ? 28 ns 25 t153 lad[3:0] setup time to pciclk rising 7 ? ns 24 t154 lad[3:0] hold time from pciclk rising 0 ? ns 24 t155 ldrq[1:0]# setup time to pciclk rising 12 ? ns 24 t156 ldrq[1:0]# hold time from pciclk rising 0 ? ns 24 t157 lframe# valid delay from pciclk rising 2 12 ns 23 table 167. miscellaneous timings sym parameter min max units fig notes t160 serirq setup time to pciclk rising 7 ? ns 24 t161 serirq hold time from pciclk rising 0 ? ns 24 t162 ri#, extsmi#, gpio, usb resume pulse width 2 ? rtcclk 26 t163 spkr valid delay from osc rising ? 200 ns 23 t164 serr# active to nmi active ? 200 ns t165 ignne# inactive fro m ferr# inactive ? 230 ns electrical characteristics 844 intel ? ich8 family datasheet notes: 1. the typical clock frequency dr iven by the ich8 is 17.86 mhz. note: 1. the typical clock frequency dr iven by the ich8 is 31.25 mhz. table 168. spi timings (20 mhz) sym parameter min max units fig notes t180 serial clock frequency - 20 mhz operation 17.2 18.4 mhz 1 t182 spi clock duty cycle at the host 40% 60% ? 48 t183 tco of spi_mosi with respect to serial clock falling edge at the host -5 13 ns 48 t184 setup of spi_miso with respect to serial clock falling edge at the host 16 ? ns 48 t185 hold of spi_miso with respect to serial clock falling edge at the host 0 ? ns 48 t186 setup of spi_cs[1:0]# assertion with respect to serial clock rising at the host 30 ? ns 48 t187 hold of spi_cs[1:0]# deas sertion with respect to serial clock falling at the host 30 ? ns 48 table 169. spi timings (33 mhz) sym parameter min max units fig notes t180b serial clock frequency - 33mhz operation 30.3 32.19 mhz 1 t182b spi clock duty cycle at the host 48% 52% ? 48 t183b tco of spi_mosi with respect to serial clock falling edge at the host -5 5 ns 48 t184b setup of spi_miso with respect to serial clock falling edge at the host 8 ? ns 48 t185b hold of spi_miso with respect to serial clock falling edge at the host 0 ? ns 48 t186b setup of spi_cs[1:0]# as sertion with respect to serial clock rising at the host 30 ? ns 48 t187b hold of spi_cs[1:0]# deas sertion with respect to serial clock falling at the host 30 ? ns 48 intel ? ich8 family datasheet 845 electrical characteristics note: 1. the originator must drive a mo re restrictive time to allow fo r quantized sampling errors by a client yet still attain the minimum time less than 500s. tbit limits apply equally to tbit- a and tbit-m. ich8 is targeted on 1mbps which is 1s bit time. 2. the minimum and maximum bit times are relative to tbit defined in the timing negotiation pulse. note: 1. the originator must drive a mo re restrictive time to allow fo r quantized sampling errors by a client yet still attain the minimum time less than 500 s. t bit limits apply equally to t bit-a and t bit-m . the ich8 is targeted on 2 mhz which is 500 ns bit time. 2. the minimum and maximum bit times are relative to t bit defined in the ti ming negotiation pulse. 3. extended trace lengths may appear as additional nodes. table 170. sst timings (desktop only) sym parameter min max units fig notes tbit bit time (overall time evident on sst) bit time driven by an originator 0.495 0.495 500 250 s s 39 1 tbit,jitter bit time jitter between adjacent bits in an sst message header or data bytes after timing has been negotiated ? ? % tbit,drift change in bit time across a sst address or sst message bits as driven by the originator. this limit only applies across tbit-a bit drift and tbit- m drift. ? ? % th1 high level time for logic 1 0.6 0.8 x tbit 39 2 th0 high level time for logic 0 0.2 0.4 x tbit 39 t sstr rise time (measured from vol = 0.3v to vih,min) ? 25 + 5 ns/node t sstf fall time (measured from voh = 1.1v to vil,max) ? 33 ns/node table 171. peci timings (desktop only) sym parameter min max units fig notes t bit bit time (overall time evident on peci) bit time driven by an originator 0.495 0.495 500 250 s s 39 1 t bit,jitter bit time jitter between adjacent bits in an peci message header or data bytes after timing has been negotiated ? ? % t bit,drift change in bit time across a peci address or peci message bits as dr iven by the originator. this limit only applies across t bit-a bit drift and t bit-m drift. ? ? % t h1 high level time for logic 1 0.6 0.8 x t bit 39 2 t h0 high level time for logic 0 0.2 0.4 x t bit 39 t pecir rise time (measured from v ol to v ih,min , vtt (nom) ?5%) ? 30 + 5 ns/ node 3 t pecif fall time (measured from v oh to v il,max , vtt (nom) +5%) ? 30 ns/ node 3 electrical characteristics 846 intel ? ich8 family datasheet notes: 1. v5ref must be powered up before vcc3_3, or after vcc3_3 within 0.7 v. also, v5ref must power down after vcc3_3, or before vcc3_3 within 0.7 v. table 172. power sequencing and reset signal timings sym parameter min max units fig notes t200 vccrtc active to rtcrst# inactive 18 ? ms 39 40 t201 v5ref_sus active to vccsus3_3 active 0 ? ms 39 40 1 t202 vccsus3_3 active to vccsus1_05 active ? ? ? 39 40 2 t203 vccrtc supply active to vccsus supplies active 0 ? ms 39 40 3 t204 vccsus supplies active to lan_rst# inactive, rsmrst# inactive 10 ? ms 39 40 t205 vccsus3_3 active to vccsus1_5 active ? ? ? 9 t206 vcclan3_3 active to vcclan1_05 active ? ? ? 6 t207 vcccl3_3 active to vcccl1_05 active ? ? ms 7 t208 vcccl3_3 active to vcccl1_5 active ? ? ms 8 t209 v5ref active to vcc3_3 active 0 ? ms 39 1 t211 vcc1_5 active to v_cpu_io active ? ? ? 39 4 t212 vrmpwrgd active to pwrok active 3 ? ms 40 42 40 t213 vccsus supplies active to vcc supplies active 0 ? ms 39 3 t214 vcc supplies active to pwrok note: pwrok assertion indicates that pciclk has been stable for at least 1 ms. 99 ? ms 39 40 42 43 t215 vcc active to stpclk# and cpuslp# (desktop only) inactive ? 50 ns 40 42 43 t217 pwrok and vrmpwrgd active to sus_stat# inactive and processor i/f signals latched to strap value 32 38 rtcclk 40 42 43 45 5, 10 t218 sus_stat# inactive to pltrst# inactive 2 3 rtcclk 40 42 43 45 10 t219 pltrst# assertion to vccglanpll inactive for platforms using ich8 integrated gbe lan 200 ? s 11 t228 hda_rst# active low pulse width 1 ? us t229 hda_rst# inactive to hda_bit_clk startup delay 162.8 ? ns intel ? ich8 family datasheet 847 electrical characteristics 2. the associated 3.3 v and 1.05 v supplies are assumed to power up or down ?together?. if the integrated vccsus1_05 voltage regulator is not used: a ) vccsus3_3 must power up before vccsus1_05 or after vccsus1_05 within 0.7 v, b ) vccsus1_05 must power down before vccsus3_3 or afte r vccsus3_3 within 0.7 v. 3. the vccsus supplies must never be active while the vc crtc supply is inactive. 4. vcc1_5 must power up before v_cpu_io or after v_cpu_io within 0.7 v, b) v_cpu_io must power down before vcc1_5 or after vcc1_5 within 0.7 v. 5. init# value determined by value of the cpu bistenable bit (chipset configuration register offset 3414h: bit 2). 6. the associated 3.3 v and 1.05 v supplies are assumed to power up or down ?together?. if the integrated vcclan1_05 voltage regulator is not used: a ) vcclan3_3 must power up before vcclan1_05 or after vcclan1_05 within 0.7 v, b ) vcclan1_05 must power down before vcclan3_3 or afte r vcclan3_3 within 0.7 v. 7. the associated 3.3 v and 1.05 v supplies are assumed to power up or down ?together?. if the integrated vcccl1_05 voltage regulator is not used: a ) vcccl3_3 must power up before vcccl1_05 or after vcccl1_05 within 0.7 v, b ) vcccl1_05 must power down before vcccl3_3 or after vcccl3_3 within 0.7 v. 8. the associated 3.3 v and 1.5 v supplies are a ssumed to power up or down ?together?. if the integrated vcccl1_5 voltage regulator is not used: a ) vcccl3_3 must power up before vcccl1_5 or after vcccl1_5 within 0.7 v, b ) vcccl1_5 must power down before vcccl3_3 or after vcccl3_3 within 0.7 v. 9. the associated 3.3 v and 1.5 v supplies are a ssumed to power up or down ?together?. if the integrated vccsus1_5 voltage regulator is not used: a ) vccsus3_3 must power up before vccsus1_5 or after vccsus1_5 within 0.7 v, b ) vccsus1_5 must power down before vccsus3_3 or after vccsus3_3 within 0.7 v 10. these transitions are clocked off the inte rnal rtc. 1 rtc clock is approximately from 28.992 s to 32.044 s. 11. ?vccglanpll inactive" is defi ned for this timing to be when vccglanpll drops to 1.425 v or less, as measured at the ich8. this ti ming applies only to platforms using ich8 integrated gbe lan. electrical characteristics 848 intel ? ich8 family datasheet table 173. power management timings (sheet 1 of 3) sym parameter min max units fig notes t230 vccsus active to slp_s5#, slp_s4#, slp_s3#, sus_stat#, pltrst# and pcirst# active ? 50 ns 40 t231 t232 rsmrst# inactive to susclk running, slp_s5# inactive ? 110 ms 40 6,22 t233 slp_s5# inactive to slp_s4# inactive see note below 40 49 8 t234 slp_s4# inactive to slp_s3# inactive 1 note 16 rtcclk 40 49 1 t250 (mobile only) processor i/f signals latched prior to stpclk# active 0 ? ? 44 46 9 t251 (mobile only) bus master idle to cpu_ slp# active 2.88 ? pciclk 46 3, 11 t252 (mobile only) cpuslp# active to dpslp# active 16 ? pciclk 45 46 3 t253 (mobile only) dpslp# active to stp_cpu# active 1 1 pciclk 45 46 3 t254 (mobile only) stp_cpu# active to processor clock stopped 0 ? pciclk 46 3, 10 t255 (mobile only) stp_cpu# active to dprstp#, dprslpvr active 0 ? ? 46 t265 (mobile only) break event to dprstp#, dprslpvr inactive (c4 exit) 1.5 1.8 s 46 12 t266 (mobile only) dprslpvr, dprstp# inactive to stp_cpu# inactive and cpu vcc ramped programmable. see d31:f0:aa, bits 3:2 s 46 t267 (mobile only) break event to stp_cpu# inactive (c3 exit) 6 note 14 pciclk 45 3, 13, 14 t268 (mobile only) stp_cpu# inactive to processor clock running 0 3 pciclk 46 3, 10 t269 (mobile only) stp_cpu# inactive to dpslp# inactive 1 1 pciclk 45 46 3, 7 t270 (mobile only) dpslp# inactive to cpu_slp# inactive programmable. see d31:f0:aah, bits 1:0 s 45 46 7 t271 (desktop only) s1 wake event to cpuslp# inactive 1 25 pciclk 41 3 t272 (mobile only) cpuslp# inactive to stpclk# inactive 0 ? s 46 t273 (mobile only) break event to stpclk# inactive (c2 exit) 0 ? ns 44 t274 (mobile only) stpclk# inactive to processor i/f signals unlatched 8 9 pciclk 44 46 3, 9 intel ? ich8 family datasheet 849 electrical characteristics t280 stpclk# active to dmi message 0 ? pciclk 41 42 43 2 t281 (desktop only) dmi message to cpuslp# active 60 63 pciclk 41 3 t283 dmi message to sus_stat# active 2 rtcclk 42 43 1 t284 sus_stat# active to pltrst#, pcirst# active (desktop only) 7 17 rtcclk 42 1 t285 (mobile only) sus_stat# active to stp_pci# active 2 10 rtcclk 43 1 t286 (mobile only) stp_pci# active to pltrst# and pcirst# active 5 7 rtcclk 43 1 t287 pltrst#, pcirst# active to slp_s3# active 1 2 rtcclk 42 43 1 t288 (mobile only) slp_s3# active to pwrok, vrmpwrgd inactive 0 ? ms 43 4 t289 (desktop only) slp_s3# active to pwrok, vrmpwrgd inactive 0 ? ms 42 4 t290 (mobile only) pwrok, vrmpwrgd inactive to vcc supplies inactive 20 ? ns 43 53 27 t291 slp_s3# active to slp_s4# active 1 2 rtcclk 42 43 1 t294 (desktop only) pwrok, vrmpwrgd inactive to vcc supplies inactive 20 ? ns 42 52 23, 25 t295 slp_s4# active to slp_s5# active 1 2 rtcclk 42 43 1, 5 t296 wake event to slp_s5# inactive 1 10 rtcclk 42 43 1 t297 slp_s5# inactive to slp_s4# inactive see note below 42 43 49 50 51 8 t298 slp_s4# inactive to slp_s3# inactive 1 note 16 rtcclk 42 43 49 50 51 1 t299 s4 wake event to slp_s4# inactive (s4 wake) see note below 42 43 8 t300 s3 wake event to slp_s3# inactive (s3 wake) 0 small as possible rtcclk 42 43 1 table 173. power management timings (sheet 2 of 3) sym parameter min max units fig notes electrical characteristics 850 intel ? ich8 family datasheet notes: 1. these transitions are clocked off the intern al rtc. 1 rtc clock is approximately from 28.992 s to 32.044 s. 2. the ich8 stpclk# assertion will trigger the processor to send a st op grant acknowledge cycle. the timing for this cycle getting to th e ich8 is dependant on the processor and the memory controller. 3. these transitions are clocked off the 33 mh z pciclk. 1 pciclk is approximately 30 ns. 4. the ich8 has no maximum timing requirement fo r this transition. it is up to the system designer to determine if the slp_s3#, slp_s4# and slp_s5# signals are used to control the power planes. 5. if the transition to s5 is due to power button override, slp_s3#, slp_s4# and slp_s5# are asserted together similar to timing t287 (pcirst# active to slp_s3# active). 6. if there is no rtc battery in the system, so vccrtc and the vccsus supplies come up together, the delay from rtcrst# and rsmrst# inactive to susclk toggling may be as much as 2.5 s. 7. this value is programmable in multiples of 1024 pci clks. maximum is 8192 pci clks (245.6 s). 8. the minimum/maximum times depend on the programming of the ?slp_s4# minimum assertion width? and th e ?slp_s4# assertion stretch enable bits (d31:f0:a4h bits 5:3)?. 9. note that this does not apply for synchronous smis. 10. this is a clock generator specification 11. if the (g)mch does not have the cpuslp# signal, then the minimum value can be 0 s. 12. this is non-zero to enforce the minimum asse rt time for dprslpvr. if the minimum assert time for dprslpvr has been met, then this is permitted to be 0. 13. this is non-zero to enforce the minimum asse rt time for stp_cpu#. if the minimum assert time for stp_cpu# has been met, then this is permitted to be 0. 14. this value should be at most a few clocks greater than the minimum. 15. when amt enabled, s4_state# mimics slp_s4# (desktop only). t301 (desktop only) cpuslp# inactive to stpclk# inactive 8 ? pciclk 41 t302 slp_m# inactive to slp_s3# inactive ? 10 ns t303 slp_s4# inactive to slp_m# inactive when amt enabled ? 10 ns 15 t304 rsmrst# deassertion to lan_rst# deassertion 0 ms 17 t305 lan power rails active to lan_rst# deassertion 1 ? ms 18 t306 lan_rst# assertion to pwrok assertion 0 ? ms t307 slp_s3# active to vcc supplies inactive 5 ? us 42 24, 25 other timings t310 thrmtrip# active to slp_s3#, slp_s4#, slp_s5# active ? 3 pci clk t311 rsmrst# rising edge transition from 20% to 80% 50 us t312 rsmrst# falling edge transition 21 t313 slp_m# active to rsmrst# active 500 ? us 27 34 26 table 173. power management timings (sheet 3 of 3) sym parameter min max units fig notes intel ? ich8 family datasheet 851 electrical characteristics 16. for t234 and t298, if intel manageability engine firmware is installed in the system, the max value of t234 and t298 is 99 ms. without the installation of the firmware, the max value is 4 rtc clocks. 17. rsmrst# must deassert before or equal to lan_rst# 18. measured from vcclan3_3 or vcclan1_05 pwr with in voltage spec (which ever is later in time) to lan_rst# = (vih+vil)/2. it is ac ceptable to use an rc circuit sourced from vcclan3_3 to create lan_rst#. the rising edge of lan_rst# needs to be a clean, monotonic edge for frequen cy content below 10mhz. 19. if integrated lan is supported, lan_rst# mu st be deasserted before or equal to pwrok assertion. 20. if integrated lan is not supported, lan_rst# should be tied to ground and must never deassert 21. rsmrst# falling edge must transition to 0.8v or less before vccsus3_3 drops to 2.1v 22. if bit 0 of section 9.8.1.3 is set to a 1, slp_s5# will not be de-asserted until a wake event is detected. if bit 0 is set to 0, slp_s5# will deassert within the specification listed in the table. 23. t294 applies during s0 to g3 transitions on ly. the timing is not applied to v5ref. v5ref timings are bonded by power sequencing. 24. t307 applies during s0 to sx transitions. 25. a vcc supply is inactive when the voltage is below the min value specified in table 155 . 26. t313 is not applicable for non-intel amt syst ems. t313 applies to mobile intel amt systems only in case of s0/m0 to s4/s4moff (w/o wol). 27. t290 is also applied when the sy stem transistions from s0 to g3. 23.5 timing diagrams figure 22. clock timing figure 23. valid delay from rising clock edge 2.0v 0.8v period high time low time fall time rise time clock 1.5v valid delay vt output electrical characteristics 852 intel ? ich8 family datasheet figure 24. setup and hold times figure 25. float delay figure 26. pulse width figure 27. output enable delay clock vt input hold time setup time vt 1.5v input vt output float delay vt pulse width vt clock output output enable delay vt 1.5v intel ? ich8 family datasheet 853 electrical characteristics figure 28. ide pio mode (mobile only) figure 29. ide multiword dma (mobile only) cs0#, cs1#, da[2:0] dior#/diow# dd[15:0] writes dd[15:0] reads iordy iordy t60 t61 t62 t69 t62i t63 t64 t65 t66 t66 z t60a t60b t60rd t60c t60c cs0#/ cs1# ddreq ddack# dior#/diow# dd[15:0] read dd[15:0] write t70m t70n t70 t70l t70i t70d t70k t70j t70e t70f t70 z t70g t70g t70h electrical characteristics 854 intel ? ich8 family datasheet figure 30. ultra ata mode (drive in itiating a burst read) (mobile only) figure 31. ultra ata mode (sus tained burst) (mobile only) dmarq (drive) t91 t89 t89 dmack# (host) stop (host) dmardy# (host) strobe (drive) dd[15:0] da[2:0], cs[1:0] t96 t98 t94 t95 t85 t86 t97 t99b strobe @ sender t81 data @ sender t86 t85 t86 t85 t81 t82 t86 strobe @ receiver data @ receiver t84 t83 t84 t83 t84 t99e t99e t99e t99d t99d t99g t99g t99g t99f t99f intel ? ich8 family datasheet 855 electrical characteristics figure 32. ultra ata mode (pausing a dma burst) (mobile only) figure 33. ultra ata mode (termina ting a dma burst) (mobile only) t90 strobe data s top (host) dmardy# t99 t88 stop (host) strobe (host) dmardy# (drive) data (host) dmack# (host) t91 t87 dmarq (drive) crc t99c t87 t99a t91 t92 t93 electrical characteristics 856 intel ? ich8 family datasheet figure 34. usb rise and fall times figure 35. usb jitter figure 36. usb eop width differential data lines 90% 10% 10% 90% t r t f rise time fall time c l c l low-speed: 75 ns at c l = 50 pf, 300 ns at c l = 350 pf full-speed: 4 to 20 ns at c l = 50 pf high-speed: 0.8 to 1.2 ns at c l = 10 pf paired transitions consecutive transitions crossover points t period differential data lines jitter differential data lines eop width data crossover level tperiod intel ? ich8 family datasheet 857 electrical characteristics figure 37. smbus transaction figure 38. smbus timeout t130 smbclk smbdata t131 t19 t134 t20 t21 t135 t132 t18 t13 3 start stop t137 clk ack clk ack t138 t138 smbclk smbdata electrical characteristics 858 intel ? ich8 family datasheet notes: 1. other power includes vccusbpl l, vccdmipll, and vccsatapll . all of these power signals must independently meet the timings shown in the figure. there are no timing interdependencies between vcc1_05 and these other power signals. there are also no timing interdependencies for these power si gnals, including vcc1_05, to vcc3_3 and vcc1_5_a/vcc1_5_b. 2. pwrok must not glitch, even if rsmrst# is asserted. figure 39. power sequencing and reset signal timings vc c r t c v _c pu _ io v cc sus 3_3 r t c r st # r sm r st # t200 t201 v 5r ef _s us v 5r ef p w r o k vc c 3_3 vc c sus 1_05 t203 t2 04 t209 t2 11 t2 14 t202 t213 vc c 1_5_ a, vc c 1_5_b v cc 1_05 and o ther pow er 1 lan _ r st # intel ? ich8 family datasheet 859 electrical characteristics notes: 1. vcc includes vcc1_5_a, vcc1_5_b, vcc3_3, vcc1_05, vccusbpll, vccdmipll, vccsatapll, and v5ref. figure 40. g3 (mechanical off) to s0 timings vccsus1_05 running susclk slp_s3# vcc 1 pwrok sus_stat# pltrst# processor i/f signals stpclk#, cpuslp# dmi message rsmrst# lan_rst# t204 t214 t212 t218 t230 t231 t215 g3 s3 s0 s0 state g3 s5 system state s4 slp_s4# slp_s5# t232 t233 t234 vccsus3_3 strap values normal operation vrmpwrgd t217 t202 electrical characteristics 860 intel ? ich8 family datasheet notes: 1. vcc includes vcc1_5_a, vcc1_5_b, vcc 3_3, vcc1_05, vccusb pll, vccdmipll, vccsatapll, and v5ref. figure 41. s0 to s1 to s0 timing figure 42. s0 to s5 to s0 timings, s3 (desktop only) t280 t281 t271 t301 s0 s0 s1 s1 s1 s0 s0 state stpclk# dmi message cpuslp# wake event s t p c lk # d m i m es s age s u s _s t a t # p lt r s t # s lp _s 3# s lp _s 5# w ak e e ven t p w r o k v c c 1 s 0 s 0 s 3 s 3 s 5 s 0 t283 t28 4 t28 7 t214 t217 t218 t21 5 t2 80 s lp _s 4# t2 91 t29 5 t2 97 t2 98 s 4 s 4 s 3 s 3/s 4/s 5 s 0 t2 96 t300 t29 9 v r m p w r g d t289 t212 s lp _ m # t307 intel ? ich8 family datasheet 861 electrical characteristics note: t290 is also applied when the sy stem transistions from s0 to g3. figure 43. s0 to s5 to s0 timings, s3 (mobile only) stp_cpu#, cpuslp#, dpslp#, dprstp# pltrst# pcirst# slp_s3# slp_s5# wake event pwrok vcc s0 s0 s3 s3 s5 s3/s4/s5 s0 s0 t295 t288 t296 t214 t217 t218 stp_pci# stpclk# dmi message dprslpvr t280 t283 t285 t287 t286 sus_stat# s4 slp_s4# t291 t297 t300 t298 t216 t299 t302 slp_m# rsmrst# t313 t307 figure 44. c0 to c2 to c0 timings (mobile only) unlatched latched unlatched cpu i/f signals stpclk# break event t250 t273 t274 electrical characteristics 862 intel ? ich8 family datasheet figure 45. c0 to c3 to c0 timings (mobile only) figure 46. c0 to c4 to c0 timings (mobile only) unlatched latched cpu i/f signals stpclk# break event bus master cpuslp# stp_cpu# t250 t251 t252 t253 t268 t269 t274 t272 active idle dpslp# t270 unlatched cpu clocks running running stopped t267 t254 unlatched cpu i/f signals stpclk# break event bus master cpuslp# stp_cpu# t250 t251 t252 t253 t266 t269 t274 t270 dprstp# dpslp# active idle dprslpvr unlatched t272 cpu clocks running running t254 t255 cpu vcc t265 stopped t268 latched intel ? ich8 family datasheet 863 electrical characteristics figure 47. intel ? high definition audio input and output timings hda_sdout hda_sdin[3:0] hda_bit_clk t143 t143 t144 t144 t145 t146 figure 48. spi timings t182 t182 spi_clk spi_mosi spi_miso t184 t183 t185 spi_cs# t186 t187 electrical characteristics 864 intel ? ich8 family datasheet note: when both the host and me boot after g3, sl p_m# does not have any timing dependency on other sleep control signals. slp_m# will be de-asserted some time between slp_s5# de-assertion and sl p_s3# de-assertion. figure 49. sleep control signal rela tionship ? host boots and me off figure 50. sleep control signal relati onship ? host and me boot after g3 slp_m# slp_s5# slp_s4# slp_s3# t297 t298 s4_state# t302 s l p _ m # s l p _ s 5 # s l p _ s 4 # s l p _ s 3 # t2 9 8 s 4 _ s t a t e # t2 9 7 intel ? ich8 family datasheet 865 electrical characteristics note: vcc includes vcc1_5_a, vcc1_5_b, vcc3_3, vcc1_05, vccusbpll, vccdmipll, and vccsatapll. note: 1. vcc includes vcc1_5_a, vcc1_5_b, vcc3_3, vcc1_05, vccusbpll, vccdmipll, and vccsatapll. figure 51. sleep control signal relationship ? host stays in s5 and me boots after g3 s l p _ m # s l p _ s 5 # s l p _ s 4 # s l p _ s 3 # w a k e e v e n t s 4 _ s t a t e # t2 9 8 t2 9 7 t3 0 3 figure 52. s0 to g3 pwrok and vcc timing pw r o k vcc t294 figure 53. s0 to g3 timings (mobile only) pwrok vcc t290 electrical characteristics 866 intel ? ich8 family datasheet intel ? ich8 family datasheet 867 package information 24 package information 24.1 package dimensions (desktop only) figure 54 , figure 55 , and figure 56 . show the package information for the 82801hb ich8, 82801hr ich8r, 82801hdh ich8dh, and 82801hdo ich8do components. note: unless otherwise specified, all dimensions are in millimeters figure 54. package dimensions (top view) (desktop only) top view pin #1 i.d (shiny) 1.0 dia x 0.15 depth 9.0 x 9.0 from center line 0.127 a // a 0.127 -a- -b- 22.10 ref 4 x 45 package information 868 intel ? ich8 family datasheet figure 55. package di mensions (bottom view) (desktop only) bottom view 2 0.50 0.70 22 ag 1 2 3 ah 12 11 10 9 5 4 8 6 7 19 20 21 13 15 16 14 17 18 u t r p v ad ae af ac ab aa y w g n m l k j h f e d c b a ag 28 ah 23 24 25 26 27 p v ad ae af w y aa ab ac r t u g n h j k l m b c d f e a 22 2 1 3 10 9 11 12 5 4 8 7 6 19 21 20 13 16 15 14 17 18 28 23 24 25 26 27 652x 13.50 29.03 min 1mm, see xy coor 29.03 13.50 min 1mm, see xy coor figure 56. package dimensions (side view) (desktop only) side view -c- c // 0.20 0.15 3 seating plane intel ? ich8 family datasheet 869 package information 24.2 package dimensions (mobile only) figure 57 , figure 58 , and figure 59 show the top view ballout for the 82801hbm ich8m and 82801hem ich8m-e components. note: unless otherwise specified, all dimensions are in millimeters. figure 57. package dimensions (top view) (mobile only) package information 870 intel ? ich8 family datasheet figure 58. package dimensions (bottom view) (mobile only) figure 59. package dimensions (side view) (mobile only) side view -c- c // 0.20 0.15 3 seating plane intel ? ich8 family datasheet 871 package information register bit index 872 intel ? ich8 family datasheet appendix a register bit index symbols (ioad) 368 numerics interrupt pending status port 574 el_state0_cnt 486 el_state1_cnt 486 interrupt pending status port 574 i/o address 368 i/o limit address limit bits 413 interrupt pending status port 574 gp_blink 521, 522 gp_io_sel 519 interrupt pending status port 574 gp_lvl 520, 526 gpio_use_sel 519 gp_io_sel2 525 upper address 675 gp_lvl 525 gpio_use_sel2 524 64 bit address capable 778 64 bit address capable (c64) 547 64b address capability 715 64-bit address supported 729 64-bit addressing capability 667 64-bit indicator 764 64-bit indicator (i64b) 415 64-bit indicator (i64l) 415 66 mhz capable 398, 414, 426, 630, 650, 687, 706, 759 66mhz capable 530, 602 address 368 a a20gate pass-through enable 636 ac ?97 modem disable (amd) 390 ac ?97 static clock gate enable 394 ac97_en 501 ac97_sts 499 acaz_break_en 484 accept unsolicited response enable 731 acpi enable 429 active state link pm control 772 active state link pm control (apmc) 364 active state link pm support 771 active state link pm support (apms) 363 active-high byte enables (ahbe) 367 address 696, 778 address (addr) 550 address enable (ae) 385 address increment/d ecrement select 449 address of descriptor table 566, 621 address select (as) 385 address translater enable 781 adi 456 advanced error interrupt message number 791 advanced packet switching 785 advanced packet switching (aps) 355, 356 aecc 791 afterg3_en 480 aggressive link power management enable 589 aggressive slumber / partial 589 ahci enable 573 alarm flag 472 alarm interrupt enable 471 alternate a20 gate 474 alternate access mode enable (ame) 387 alternate gpi smi enable 506 alternate gpi smi status 506, 507 apic data 464 apic enable (aen) 384 apic id 465 apic index 463 apm_sts 505 apmc_en 503 arbiter disable 497 asynchronous schedule enable 669 asynchronous schedule park capability 667 asynchronous schedule status 671 asynclistaddr 676 attention button present 717, 768, 774 attention button pressed 776 attention button pressed enable 775 attention indicator control 775 attention indicator present 717, 768, 774 auto flush after disconnect enable 419 autoinitialize enable 449 automatic end of interrupt 458 automatically append crc 699 aux current 714 aux power detected 718, 770 aux power pm enable 769 intel ? ich8 family datasheet 873 register bit index aux_current 403, 780 auxiliary current 545, 615, 655 auxiliary power enable 718 azalia pin (zip) 374 azalia traffic class assignment 711 azalia/ac ?97 signal mode 711 b b2/b3 support 714, 780 bad dllp mask 790 bad dllp status 790 bad tlp mask 790 bad tlp status 790 bar location (barloc) 559 bar number 657 bar offset (barofst) 559 base address 428, 429, 444, 533, 534, 535, 604, 605, 606, 633, 643, 652, 689, 764 base address (low) 675 base address lower 793 base address lower (bal) 358 base address upper 793 base address upper (bau) 358 base and current address 446 base and current count 446 base class code 399, 400, 40 1, 402, 411, 427, 532, 603, 631, 651, 688, 707, 761 batlow_en 500 batlow_sts 498 bcc 631, 707, 761 bctrl 766 bfcs 561 bftd1 562 bftd2 562 bidirectional direction control 746 binary/bcd countdown select 452 bios interface lock-down (bild) 387 bios lock enable 441 bios release 502 bios write enable 441 bios_en 503 bios_pci_exp_en 477 bios_sts 506 bioswr_sts 513 bist fis failed 561 bist fis parameters 562 bist fis successful 561 bist fis transmit data 1 562 bist fis transmit data 2 563 bits per sample 752 block data 697 block delayed transactions 419 block/sector erase size (bses) 816 bm 484 bme receive check enable 782 bnum 762 boot bios straps (bbs) 386 boot_sts 514 buc 388 buffer completion interrupt status 748 buffer descriptor list pointer lower base address 753 buffer descriptor list pointer upper base address 753 buffered mode 458 bus master enable 397, 409, 425, 529, 601, 629, 649, 686, 706, 759 bus master ide active 566, 621 bus master reload 493 bus master status 491 bus number (bn) 359, 360, 361, 362, 363 bus power / clock control enable 780 bus power/clock control enable 714 bus_err 693 byte done status 693 byte enable mask (bem) 368 byte enables (tbe) 368 c c3_residency 510 c4 483 cap 571 cap 716 cap id 713, 715 capabilities list 398, 411, 426, 530, 602, 630, 650, 706, 760 capabilities list indicator 687 capabilities pointer 402, 537, 607, 653, 710, 765 capabilities pointer (ptr) 416 capability 357, 784 capability id 403, 404, 405, 544, 614, 659, 767, 778, 784, 791 capability id (cap) 558 capability id (cid) 353, 357, 363, 546 capability identifier 422, 779 capability register length value 665 capability version 717, 768, 791 capability version (cv) 353, 363 caplength 665 capp 402, 765 capptr 710 captured slot power limit scale 717, 768 register bit index 874 intel ? ich8 family datasheet captured slot power limit value 717, 768 cascaded interrupt controller irq connection 457 cc 399 ccc 577, 578 cem 790 ces 790 cg 392 channel mask bits 450 channel mask select 448 channel request status 448 channel terminal count status 448 clear byte pointer 449 clear mask register 450 clist 403, 405, 767 cls 399, 708, 761 cnf1_lpc_en 434 cnf2_lpc_en 434 cntl 681 cold port detect status 585 cold presence detect enable 587 coma decode range 433 coma_lpc_en 434 comb decode range 433 comb_lpc_en 434 command completed 776 command completed interrupt enable 775 command list base address 584 command list base address upper 584, 585 command list override (clo) 591 commands issued 598 common clock configuration 772 common clock exit latency 782 completion 787 completion abort mask 788 completion abort severity 789 completion abort status 787 completion timeout mask 788 completion timeout severity 789 component id 792 component id (cid) 357 config 683 configflag 676 configuration layout 632, 761 configure flag 638, 676 connect status change 646, 680 controller interrupt enable 736 controller interrupt status 737 controller reset 731 controller running 590 coprocessor error 475 coprocessor error enable (cen) 384 corb lower base address 738, 741 corb memory error indication 740 corb memory error interrupt enable 740 corb read pointer (corbrp) 739 corb read pointer reset 739 corb size 740 corb size capability 740 corb upper base address 739 corb write pointer 739 corbctl 740 corblbase 738 corbrp 739 corbsize 740 corbst 740 corbubase 739 corbwp 739 correctable error detected 718, 770 correctable error reporting enable 718, 769 count register status 454 countdown type status 454 counter 0 select 453 counter 1 select 453 counter 2 select 453 counter latch command 453 counter mode selection 452 counter out pin state 454 counter port 455 counter select 452 counter selection 453 counter size capability 796 counter value 798 cpu bist enable (cbe) 388 cpu pll lock time 478 cpu power failure 479 cpu slp# enable 477 cpu thermal trip status 479 crc error 698 ctrldssegment 675 current command slot 590 current connect status 646, 680 current interface speed 594, 623 cx 481 cycle trap smi# status (ctss) 367 cyclic buffer length 749 d d1 support 545, 615, 655, 714 d1_support 403, 780 d2 support 545, 615, 655, 714 intel ? ich8 family datasheet 875 register bit index d2_support 403, 780 d27ip 374 d28ip 373 d28ir 379 d29ip 372 d29ir 377 d30ip 371 d30ir 377 d31ir 375 dat 464 data 556, 560, 714, 779 data (data) 567, 622 data cycle? rw 803, 805, 806, 807, 811, 815, 816, 827, 829, 830, 831, 832, 833 data link layer active (dlla) 773 data link protocol error mask 788 data link protocol error severity 789 data link protocol error status 787 data message byte 0 698 data message byte 1 698 data mode 471 data parity error detected 411, 414, 426, 530, 602, 630, 687, 706, 763 data scale 656 data select 656 data_high_byte 702 data_len_cnt 682 data_low_byte 702 data0/count 696 data1 696 databuf 683 databuffer(63-0) 683 date alarm 472 daylight savings enable 471 dcap 768 dctl 769 debug port capability id 656 debug port number 665 debug port offset 657 delivery mode 467 delivery status 466 descriptor error 748 descriptor error interrupt enable 746 descriptor processed 586 descriptor processed interrupt enable 587 destination 466 destination mode 467 detected parity error 398, 410, 414, 426, 530, 602, 630, 650, 687, 706, 759, 763 dev_err 694 devc 718 devcap 717 device / port type 768 device connects 210 device detection 594, 623 device detection initialization 595, 624 device id 396, 408, 424, 529, 601, 629, 648, 686, 705, 758 device interlock enable 587 device interlock status 586 device monitor status 505 device number (dn) 359, 360, 361, 362, 363 device specific initialization 403, 545, 615, 655, 714, 780 device status 597 device to host register fis interrupt enable 588 device/port type 717 device_address 701 devs 718 devsel# timing status 398, 414, 426, 530, 602, 630, 650, 687, 706, 759 diagnostics 596, 625 did 396, 705 discard delayed transactions 419 discard timer serr# enable 417, 766 discard timer status 417, 766 division chain select 470 dma 745 dma channel group enable 447 dma channel select 448, 449 dma group arbitration priority 447 dma low page 447 dma position buffer enable 745 dma position lower base address 745 dma position upper base address 745 dma setup fis interrupt 586 dma setup fis interrupt enable 588 dma transfer mode 449 dma transfer type 449 dmi and pci express* rx dynamic clock gate en- able 393 dmi tx dynamic clock gate enable 393 dmisci_sts 512 dmiserr_sts 512 dmismi_sts 512 dock attach (da) 712 dock mated (dm) 713, 733 dock mated interrupt status (dmis) 733 docking supported (ds) 734 register bit index 876 intel ? ich8 family datasheet docking supported (ds) - r/wo 713 done_sts 681 dplbase 745 dprslpvr to stpcpu 483 dpslp-to-slp 483 dpubase 745 dr 404 dram initialization bit 478 drive 0 dma capable 566, 586, 621 drive 0 dma timing enable 539, 609 drive 0 fast timing bank 539, 609 drive 0 iordy sample point enable 539, 609 drive 0 prefetch/posting enable 539, 609 drive 1 dma capable 566, 621 drive 1 dma timing enable 538, 608 drive 1 fast timing bank 539, 609 drive 1 iordy sample point enable 538, 608 drive 1 prefetch/posting enable 538, 608 drive 1 timing register enable 538, 608 drive led on atapi enable 589 dsts 770 e ecap 734 ecrc 791 ecrc check capable 791 ecrc check enable 791 ecrc error mask 788 ecrc error severity 789 ecrc error status 787 ecrc generation enable 791 edge/level bank se lect (ltim) 456 ehc initialization 204 ehc resets 205 ehci disable (ehcid) 390 ehci extended capabilities pointer 667 ehci pin (eip) 372 ehci_break_en 484 el_en?r/w 487 el_led_own?r/w 486 el_pb_sci_sts - r/wc 485 el_pb_smi_sts - r/wc 485 el_sci_en ? r/w 500 el_sci_now_sts- r/wc 485 el_sci_sts ? r/wc 498 el_smi_en ? r/w 502 el_smi_sts ? ro 504 element type 792 element type (et) 357 em 579, 580 enable 444 enable 32-byte buffer 699 enable corb dma engine 740 enable no snoop 769 enable relaxed ordering 718, 769 enable rirb dma engine 742 enable special mask mode 460 enabled_cnt 681 end of smi 503 endpoint l0 acceptable latency 768 endpoint l0s acceptable latency 717 endpoint l1 acceptable latency 717, 768 enter c4 when c3 invoked 477 enter global suspend mode 638 eoir 464 erase opcode 816 erba 402 err_cor received 791 err_fatal/nonfatal received 791 error 566, 592, 597, 621, 625 error_good#_sts 681 esd 357, 723, 792 exception_sts 681 extended destination id 466 extended synch 772 extended synch (es) 364 extended tag field enable 718, 769 extended tag field support 717 extended tag field supported 768 extended vc count (evc) 353 f faddr 804, 829 failed 693 fast back to back capable 398, 411, 414, 426, 530, 602, 630, 650, 687, 706, 759 fast back to back enable 397, 409, 417, 425, 529, 601, 629, 686, 705, 758, 766 fast primary drive 0 base clock 543, 613 fast primary drive 1 base clock 543, 613 fast secondary drive 0 base clock 543, 613 fast secondary drive 1 base clock 543, 613 fatal error detected 718, 770 fatal error reporting enable 718, 769 fb_40_en 440 fb_40_idsel 438 intel ? ich8 family datasheet 877 register bit index fb_50_en 440 fb_50_idsel 438 fb_60_en 440 fb_60_idsel 438 fb_70_en 440 fb_70_idsel 438 fb_c0_en 439, 440 fb_c0_idsel 437 fb_c8_en 439 fb_c8_idsel 437 fb_d0_en 439 fb_d0_idsel 437 fb_d8_en 439 fb_d8_idsel 437 fb_e0_en 439 fb_e0_idsel 437 fb_e8_en 439 fb_e8_idsel 437 fb_f0_en 439 fb_f0_idsel 437 fb_f8_en 439 fb_f8_idsel 437 fdata0 805, 829 fdatan 805 fdd decode range 432 fdd_lpc_en 434 fdoc 814 fdod 815 ferr# mux enable (fme) 386 fifo error 748 fifo error interrupt enable 746 fifo ready 748 fifo size 751 fifo watermark 750 first error pointer 791 fis base address 585 fis receive enable 590 fis receive running 590 flcomp 818 flill 820 flow control protocol error mask 788 flow control protocol error severity 789 flow control protocol error status 787 flreg0 821 flush control 731 flush status 733, 814, 835 flvalsig 817 force global resume 638 force port resume 679 force thermal throttling 494 frame length timing value 658 frame list current inde x/frame number 642, 674 frame list rollover 672 frame list rollover enable 673 frame list size 670 frap 806, 829 freg0 806, 830 freg1 807, 830 freg2 807, 831 freg3 807, 831 frindex 674 full reset 475 function number (fn) 359, 360, 361, 362, 363 g gameh_lpc_en 434 gamel_lpc_en 434 gbl_smi_en 503 gc 430 gcap 729, 796 gcs 386 gctl 731 gen 797 generic decode range 1 enable 435, 436 generic i/o decode range 1 base address 435, 436 ghc 572 gintr 797 global enable 492 global interrupt enable 736 global interrupt status 737 global release 493 global reset 639 global status 491 go_cnt 681 gp 525 gp_inv(n) 523 gpe0_sts 505 gpin_en 500 gpin_sts 497 gpio 523 gpio enable 430 gpio0 route 487 gpio1 route 487 gpio11_alert_disable 516 gpio15 route 487 gpio2 route 487 gpiobase 429 gsts 733 register bit index 878 intel ? ich8 family datasheet h hba reset 573 hc bios owned semaphore 659 hc os owned semaphore 659 hccparams 667 hchalted 641, 671 hciversion 665 hcsparams 665 hdba 361 hdbarl 708 hdbaru 709 hdctl 711 hdd 361 hdevice is atapi 589 header type 412, 428, 708 headtyp 428, 708 hide device 0 418 hide device 1 418 hide device 2 418 hide device 3 418 high definition audio dynamic clock gate enable 392 high definition audio static clock gate enable 392, 394 high priority port (hpp) 365 high priority port enable (hpe) 365 host bus data error enable 587 host bus data error status 586 host bus fatal error enable 587 host bus fatal error status 585 host controller process error 641 host controller reset 639, 670 host system error 641, 671 host system error enable 673 host_busy 694 host_notify_intren 701 host_notify_sts 700 host_notify_wken 701 hot plug attention button smi status 783 hot plug capable 774 hot plug capable port 590 hot plug command completed smi status 783 hot plug interrupt enable 775 hot plug link active state changed smi status (hplas) 783 hot plug presence detect smi status 783 hot plug sci enable 781 hot plug sci status 783 hot plug smi enable 782 hot plug surprise 774 hot_plug_en 501 hot_plug_sts 499 hour format 471 hptc 385 hsfc 804, 828 hsfs 803, 827 ht 400 i i/o base address 762 i/o base address (ioba) 413 i/o base address capability 413, 762 i/o limit address 762 i/o limit address capability 762 i/o space enable 397, 409, 425, 529, 601, 629, 649, 686, 706, 759 i2c 220 i2c_en 691 i64_en 477 ic 743 icw/ocw select 456 icw4 write required 456 id 465 ide 484 ide decode enable 538, 608 ide_act_sts 509 ii/o limit address capability 413 ilcl 363 immediate command busy 744 immediate command write 743 immediate response read 744 immediate result valid 744 in_use_cnt 681 incorrect port multiplier enable 587 incorrect port multiplier status 586 ind 463 index (index) 567, 622 init_now 474 inpay 730 input fifo padding t ype (ipadtype) 735 input payload capability 730 input stream payload capability (instrmpay) 735 instrmpay 735 intctl 736 intel 374, 390 intel pro/wireless 3945abg status 784 intel speedstep enable 477 intel_usb2_en 502 intel_usb2_sts 504 interface 531, 532, 603 intel ? ich8 family datasheet 879 register bit index interface communication control 589 interface fatal error status 586 interface non-fatal error enable 587 interface non-fatal error status 586 interface power management 594, 623 interface power management transitions allowed 595, 624 interface speed support 571 interlock switch attached to port 590 interlock switch state 590 interrupt 566, 621 interrupt a pin route (iar) 376, 378, 380, 381, 382, 383 interrupt b pin route (ibr) 376, 377, 379, 381, 382, 383 interrupt c pin route (icr) 376, 377, 379, 380, 382, 383 interrupt d pin route (idr) 375, 376, 377, 379, 380 interrupt disable 397, 409, 529, 601, 629, 649, 686, 705, 758 interrupt enable 573 interrupt input pin polarity 466 interrupt level select 459 interrupt line 402, 416, 537, 607, 634, 653, 690, 710, 766 interrupt message number 717, 768 interrupt on async advance 671 interrupt on async advance doorbell 669 interrupt on async advance enable 673 interrupt on complete enable 642 interrupt on completion enable 746 interrupt pin 690 interrupt pin 402, 416, 537, 607, 653, 710, 766 interrupt request flag 472 interrupt request level 457 interrupt request mask 459 interrupt rout 798 interrupt routing enable 430, 432 interrupt status 398, 411, 426, 530, 602, 630, 650, 687, 706, 760 interrupt threshold control 669 interrupt vector base address 457 intln 710 intpn 710 intr 402, 694, 766 intrd_sel 516 intren 695 intruder detect 514 intsts 737 inuse_sts 693 invalid receive range check enable 782 io space indicator 689 iobl 762 iochk# nmi enable 473 iochk# nmi source status 473 iordy sample point 538, 608 ir 744 ireserved 375 irq routing 430, 432 irq1_cause 517 irq10 ecl 462 irq11 ecl 462 irq12 ecl 462 irq12_cause 517 irq14 ecl 462 irq15 ecl 462 irq3 ecl 461 irq4 ecl 461 irq5 ecl 461 irq6 ecl 461 irq7 ecl 461 irq9 ecl 462 irs 744 is 574 isa enable 418, 767 isochronous scheduling threshold 667 k kbc_act_sts 509 kbc_lpc_en 434 kill 695 l l0s exit latency 771 l0s exit latency (el0) 363 l1 exit latency 771 l1 exit latency (el1) 363 l1addl 724 l1addu 724 l1desc 724 last valid index 750 last_byte 694 latch count of selected counters 453 latch status of selected counters 453 latency count 761 latency timer 708 lcap 363, 770 lctl 364, 772 legacy (lpc) dynamic clock gate enable 392 legacy replacement rout 797 register bit index 880 intel ? ich8 family datasheet legacy replacement rout capable 796 legacy_usb_en 503 legacy_usb_sts 506 legacy_usb2_en 502 legacy_usb2_sts 504 light host controller reset 669 line status 646, 678 link 360, 362 link active changed enable (lace) 775 link active reporting capable (larc) 770 link active state changed (lasc) 776 link disable 772 link hold off 781 link pointer low 676 link position in buffer 749 link speed 773 link speed (ls) 364 link training 773 link training error 773 link type 792 link type (lt) 358, 359, 360, 361 link valid 792 link valid (lv) 358, 359, 360, 361, 362 link_id_sts 681 load port arbitration table 786 load port arbitration table (lat) 355, 356 load vc arbitration table 785 load vc arbitration table (lat) 354 loop back test mode 638 low priority extended vc count (lpevc) 353 low speed device attached 646 lower 128 byte lock (ll) 385 lower base address 708 lpc 371, 432 lpc bridge disable (lbd) 390 lpt decode range 432 lpt_lpc_en 434 lsts 364, 773 lt 708 m ma 778 maddh 406 maddl 405 main 798 main counter tick period 796 major revision (majrev) 558 major version 729 major version number 576 malformed tlp mask 788 malformed tlp severity 789 malformed tlp status 787 map value 551, 617 mask 466 mask (adma) 368 master abort mode 417, 766 master abort status 426 master clear 450 master data parity error detected 398, 650, 759 master latency count 427 master latency timer 632 master latency timer count 412, 413, 533, 604, 652 master/slave in buffered mode 458 max packet 638 max payload size 718, 769 max payload size supported 717, 768 max read request size 718, 769 maximum delayed transactions 419 maximum link speed 771 maximum link speed (mls) 363 maximum link width 771 maximum link width (mlw) 363 maximum redirection entries 465 maximum time slots 785 maximum time slots (mts) 354, 356 mbara 400 mbarb 400 mbarc 401 mbl 764 mc 778 mc_lpc_en 434 mcsmi_enmicrocontroller smi enable 502 mctl 405 md 779 mdat 406 memory base 415, 764 memory limit 415, 764 memory read line prefetch disable 419 memory read multiple prefetch disable 419 memory read prefetch disable 419 memory space enable 397, 40 9, 425, 529, 601, 629, 649, 686, 706, 759 memory write and inva lidate enable 409, 706 message data 716 message lower address 716 message upper address 716 microcontroller smi# status 505 microprocessor mode 458 mid 715, 778 minimum slp_s4# assertion width violation status intel ? ich8 family datasheet 881 register bit index 479 minor revision (minrev) 558 minor version 729, 803, 804, 805, 806, 807, 808, 809, 810, 811, 812, 815, 827, 828, 829, 830, 831, 832, 833, 834 minor version number 576 mlmg 402 mmc 715 mmd 716 mmla 716 mmua 716 mobile ide configuration lock down (micld) 386 mode selection status 454 monitor_sts 504 mpc 781 mrl sensor changed 776 mrl sensor changed enable 775 mrl sensor present 774 mrl sensor state 776 msi enable 715, 778 msi enable (msie) 549 multi-function device 412, 428, 632, 761 multiple err_cor received 791 multiple err_fatal/nonfatal received 791 multiple message capable 715, 778 multiple message capable (mmc 548 multiple message enable 715, 778 multiple message enable (mme) 548 n n response interrupt count 742 n_ports 666 negotiated link width 773 negotiated link width (nlw) 364 never prefetch 419 newcentury_sts 513 next capability 403, 405, 406, 422, 544, 614, 713, 715, 716, 767, 779, 791 next capability (next) 357 next capability offset 784 next capability offset (nco) 353 next capability offset (next) 363 next capability pointer (next) 558 next ehci capability pointer 659 next item pointer 1 value 654 next item pointer 2 capability 657 next pointer 778 next pointer (next) 546 nmi enable 474 nmi_now 515 nmi2smi_en 515 nmi2smi_sts 513 no reboot (nr) 386 no snoop enable 718 non-fatal error detected 718, 770 non-fatal error reporting enable 718, 769 notify 701, 702 number of active transactions 420 number of bidirectional stream supported 729 number of channels 752 number of companion controllers 665 number of input stream supported 729 number of link entries 792 number of link entries (nle) 357 number of output stream supported 729 number of pending transactions 420 number of ports 572 number of ports per companion controller 666 number of serial data out signals 729 number of timer capability 796 nvalid receive bus number check enable 781 o ocw2 select 459 ocw3 select 460 oic 384 opmenu 814, 835 optype 813, 834 os_policy 516 outpay 730 output fifo padding type (opadtype) 734 output payload capability 730 output stream payload capability (outstrmpay) 734 outstrmpay 734 overall enable 797 overcurrent active 646, 679 overcurrent change 679 overcurrent indicator 645 overflow error enable 587 overflow status 586 owner_cnt 681 p parallel 391 parity error response 397, 409, 425, 529, 601, 629, 649, 686, 706, 758 parity error response enable 418, 767 partial state capable 572 pass through state 636 register bit index 882 intel ? ich8 family datasheet pata dynamic clock gate enable 392 pata pin (smip) 370 pata reset state (prs) 388 pc 714 pci bridge pin (pip) 370 pci clkrun# enable 478 pci dynamic gate enable 393 pci express #1 pin (p1ip) 374 pci express #2 pin (p2ip) 373 pci express #3 pin (p3ip) 373 pci express #4 pin (p4ip) 373 pci express 1 disable (pe1d) 389 pci express 2 disable (pe2d) 389 pci express 3 disable (pe3d) 389 pci express 4 disable (pe4d) 389 pci express root port static clock gate enable 393 pci express tx dynamic clock gate enable 393 pci express wake disable 492 pci express wake status 490 pci interrupt enable 635 pci serr# enable 473 pci_break_en 484 pci_exp_en 500 pci_exp_smi_sts 504 pci_exp_sts 498 pcicmd 397, 705 pcie_break_en 484 pcists 398, 706 pcs 714 pec_data 697 pec_en 694 peer decode enable 421 peetm 793 periodic interrupt capable 799 periodic interrupt enable 471 periodic interrupt flag 472 periodic schedule enable 670 periodic schedule status 671 periodic smi# rate select 478 periodic_en 502 periodic_sts 505 periodiclistbase 675 perr# assertion detected 420 perr#-to-serr# enable 421 phantom 769 phantom function enable 718 phantom functions supported 717, 768 phyrdy 587 phyrdy change status 586 physical slot number 774 pi 575, 688, 707 pid 713 pio multiple drq block (pmd) 572 pio setup fis interrupt 586 pio setup fis interrupt enable 588 pirqae_act_sts 509 pirqbf_act_sts 509 pirqcg_act_sts 509 pirqdh_act_sts 509 plt 399, 427 pm1_sts_reg 505 pmbl 764 pmbu32 765 pmc 403, 780 pmcap 779 pmcs 404, 780 pme clock 403, 545, 615, 655, 714, 780 pme enable 404, 546, 616, 656, 714, 781 pme interrupt enable 777 pme pending 777 pme requestor id 777 pme status 404, 546, 616, 656, 714, 777, 780 pme support 545, 615, 655, 714 pme_b0_en 500 pme_b0_sts 498 pme_en 500 pme_sts 498 pme_support 403, 780 pmlu32 765 poisoned tlp mask 788 poisoned tlp severity 789 poisoned tlp status 787 poll mode command 460 popdown mode enable 481, 482 popup mode enable 482 port 557, 558 port 0 bist fis initiate 562 port 0 enabled 553, 617 port 0 present 552, 617 port 1 bist fis initiate 562 port 1 enabled 553, 617 port 1 present 552, 617 port 2 bist fis initiate 561 port 2 enabled 553 port 2 present 552 port 3 bist fis initiate 561 port 3 enabled 552, 553 port 3 present 552 port arbitration capability 785 port arbitration capability (pac) 355, 356 intel ? ich8 family datasheet 883 register bit index port arbitration select 786 port arbitration select (pas) 355, 356 port arbitration table entry size (pats) 353 port arbitration table offset 785 port arbitration table offset (at) 354, 356 port arbitration tables status 786 port arbitration tables status (ats) 355, 357 port change detect 672 port change interrupt enable 587, 673 port configuration (pc) 365 port connect change status 586 port enable/disable change 646, 679 port enabled/disabled 646, 680 port i/oxapic enable 782 port multipler fis based switching enable 590 port multiplier attached 590 port multiplier port 595, 624 port number 770, 792 port number (pn) 357 port owner 678 port power 678 port reset 646, 678 port test control 678 port wake implemented 659 port wake up capability mask 659 port0en 636 port1en 636 ports implemented port 0 575, 577, 580 ports implemented port 1 575 ports implemented port 2 575 ports implemented port 3 575, 577, 578, 579, 580 portsc 677 postable memory write enable 397, 425, 529, 601, 629, 649, 686, 758 power button enable 492 power button override status 490 power button status 491 power controller control 775 power controller present 774 power failure 480 power fault detected 776 power fault detected enable 775 power indicator control 775 power indicator present 717, 768, 774 power management capability id 654 power management sci enable 781 power management sci status 783 power management smi enable 782 power management smi status 783 power on device 591 power sequencing 285 power state 404, 546, 616, 656, 715, 781 pr0 808, 831 pr1 808, 832 pr2 809 pr3 809 pr4 810 prd interrupt status 566, 621 prefetchable 535, 652, 708, 764 prefetchable memo ry base 415, 764 prefetchable memory base upper portion 416, 765 prefetchable memory limit 415 prefetchable memory limi t upper portion 416, 765 prefix 813, 834 prefix opcode 0 813, 834 prefix opcode 1 813, 834 preop 813, 834 presence detect changed 776 presence detect changed enable 775 presence detect state 776 prim_sig_mode 543, 613 primary bus number 412, 762 primary discard timer 417, 766 primary drive 0 base clock 544, 614 primary drive 0 cycle time 542, 612 primary drive 0 synchronous dma mode enable 541, 611 primary drive 1 base clock 544, 614 primary drive 1 cycle time 542 primary drive 1 iordy sample point 540 primary drive 1 recovery time 540 primary drive 1 synchronous dma mode enable 541 primary master trap 560 primary mode native capable 531, 603 primary mode native enable 531, 603 primary slave trap 560 programmable frame list flag 667 programming interface 399, 411, 427, 631, 651, 707, 760 prq 465 pvc 354, 785 pvccap1 719 pvccap2 720 pvcctl 720 pvcsts 720 pvs 354, 785 pwrbtn_evnt?wo 486 pwrbtn_int_en?r/w 486 register bit index 884 intel ? ich8 family datasheet pwrbtn_lvl 477 pwrok failure 479 pxc 717 pxci 597 pxclb 583 pxclbu 584 pxcmd 589 pxfb 585 pxfbu 585 pxid 716 pxie 587 pxis 585 pxsact 597 pxsctl 595, 624 pxserr 596, 625 pxsig 593 pxssts 594, 623 pxtfd 591 r rate select 470 rc 385 rcba 444 rccap 723 rctcl 357, 791 rctl 777 read / write control 565, 620 read back command 453 read completion boundary control 772 read/write mask (rwm) 368 read/write select 452 read/write selection status 454 read/write# (rwi) 367 read/write# (rwio) 368 real time clock index address 474 received 763 received master abort 398, 411, 414, 530, 602, 630, 650, 687, 706, 759 received system error 414, 763 received target abort 398, 411, 414, 42 6, 650, 687, 706, 759, 763 received target abort serr# enable 421 received_pid_sts(23-16) 682 receiver error mask 790 receiver error status 790 receiver overflow mask 788 receiver overflow severity 789 receiver overflow status 787 reclamation 671 recovery time 538, 608 redir 466 redirection entry clear 464 reference clock (rc) 353 refresh cycle toggle 473 register read command 460 reject snoop transactions 785 reject snoop transactions (rts) 355, 356 remote irr 466 replay number rollover mask 790 replay number rollover status 790 replay timer timeout mask 790 replay timer timeout status 790 report zero for bm_sts 482 res 791 reserved page route (rpr) 387 reset cpu 475 resource type indicator 428, 533, 534, 535, 604, 605, 606, 633, 652 response interrupt 743 response interrupt control 742 response overrun interrupt control 742 response overrun interrupt status 743 resume detect 641, 646 resume interrupt enable 642 retrain link 772 revision id 399, 411, 427, 530, 602, 630, 651, 687, 707, 760 revision identificaiton 796 ri_en 500 ri_sts 498 rid 399, 687 rintcnt 742 rirb lower base unimplemented bits 741 rirb size 743 rirb size capability 743 rirb upper base address 741 rirb write pointer 741 rirb write pointer reset 741 rirbctl 742 rirblbase 741 rirbsize 743 rirbsts 743 rirbubase 741 rirbwp 741 rotate and eoi codes 459 rp1ba 359 rp1d 358 rp2ba 359 rp2d 359 rp3ba 360 intel ? ich8 family datasheet 885 register bit index rp3d 360 rp4ba 361 rp4d 360 rp5ba 362 rp5d 362 rp6ba 363 rp6d 362 rpfn?root port function number for pci express root ports 366 rsts 777 rtc 470, 471, 472 rtc event enable 492 rtc status 491 rtc_pwr_stsrtc power status 480 run/stop 639, 670 rw 696 s sample base rate 752 sample base rate devisor 752 sample base rate multiple 752 sata 557 sata 3 gb/s capability 443 sata pin (sip) 370 sata port 0 dynamic clock gate enable 392 sata port 1 dynamic clock gate enable 392 sata port 2 dynamic clock gate enable 392 sata port 3 dynamic clock gate enable 392 sci enable 493 sci irq select 429 sci_now_cnt?wo 486 sclkcg 554 sclkgc 555 scrambler bypass mode 793 scratchpad 482 scratchpad 642 scratchpad bit 465 sdbdpl 753 sdbdpu 753 sdcbl 749 sdctl 746 sdfifos 751 sdfifow 750 sdfmt 752 sdin state change status flags 733, 813, 834, 835 sdin wake enable flags 732 sdlpib 749 sdlvi 750 sdsts 748 sec_sig_mode 543, 613 second_to_sts 514 secondary 560 secondary 66 mhz capable 763 secondary bus number 412, 762 secondary bus reset 417, 766 secondary de vsel# timing status 763 secondary discard timer 417, 766 secondary discard timer testmode 421 secondary drive 0 base clock 544, 614 secondary drive 0 cycle time 542, 612 secondary drive 0 synchronous dma mode enable 541, 611 secondary drive 1 base clock 544, 614 secondary drive 1 cycle time 542 secondary drive 1 iordy sample point 540 secondary drive 1 recovery time 540 secondary drive 1 synchronous dma mode enable 541 secondary fast back to back capable 763 secondary master trap 560 secondary mode native capable 531, 603 secondary mode native enable 531, 603 secondary slave trap 555, 560 select power management 595, 624 send_pid_cnt(15-8) 682 serial ata disable (sad) 390 serial bus release number 634 serial irq enable 431 serial irq frame size 431 serial irq mode select 431 serirq_smi_sts 505 serr# enable 397, 409, 418, 425, 529, 601, 629, 649, 686, 705, 758, 767 serr# nmi source status 473 serr# status 706 server error reporting mode (serm) 386 set device bits fis interrupt enable 587 set device bits interrupt 586 short packet inte rrupt enable 642 sid 401, 690, 709 signaled system error 398, 410, 426, 530, 602, 650, 687, 759 signaled target abort 398, 411, 414, 426, 530, 602, 630, 650, 687, 706, 759, 763 signature 593 single or cascade 456 slave identification code 458 slave_addr 698 register bit index 886 intel ? ich8 family datasheet slcap 774 slctl 775 sleep enable 493 sleep type 493 slot clock configuration 773 slot implemented 717, 768 slot power limit scale 774 slot power limit value 774 slp_s4# assertion stretch enable 480 slp_s4# minimum assertion width 480 slp_smi_en 503 slp_smi_sts 505 slsts 776 slt 762 slumber state capable 572 slv 700, 701 sm bus disable (sd) 390 sm bus pin (smip) 370 smb_cmd 695 smb_smi_en 691 smbalert_dis 701 smbalert_sts 693 smbclk_ctl 700 smbclk_cur_sts 700 smbdata_cur_sts 700 smbus 700 smbus host enable 691 smbus smi status 504 smbus tco mode 698 smbus wake status 499 smi at end of pass-through enable 636 smi caused by end of pass-through 635 smi caused by port 60 read 635 smi caused by port 60 write 635 smi caused by port 64 read 635 smi caused by port 64 write 635 smi caused by usb interrupt 635 smi on async 662 smi on async advance 660 smi on async advance enable 661 smi on async enable 662 smi on bar 660 smi on bar enable 660 smi on cf 662 smi on cf enable 663 smi on frame list rollover 660 smi on frame list rollover enable 661 smi on hchalted 662 smi on hchalted enable 663 smi on hcreset 662 smi on hcreset enable 663 smi on host system error 660 smi on host system error enable 661 smi on os ownership change 660 smi on os ownership enable 661 smi on pci command 660 smi on pci command enable 660 smi on periodic 662 smi on periodic enable 663 smi on pmcsr 662 smi on pmscr enable 662 smi on port 60 reads enable 636 smi on port 60 writes enable 636 smi on port 64 reads enable 636 smi on port 64 writes enable 636 smi on port change detect 660 smi on port change enable 661 smi on portowner 662 smi on portowner enable 662 smi on usb complete 660 smi on usb complete enable 661 smi on usb error 660 smi on usb error enable 661 smi on usb irq enable 636 smi_lock 477 smi_option_cnt?r/w 486 smlink 699 smlink slave smi status 514 smlink_clk_ctl 699 smlink0_cur_sts 699 smlink1_cur_sts 699 sof timing value 644 software debug 638 software smi# timer enable 503 sp 560 space type 708 spdh 418 speaker data enable 473 special cycle enable 397, 409, 425, 529, 601, 629, 649, 686, 706, 758 special fully nested mode 458 special mask mode 460 speed allowed 595, 624 spi read configuration (src) 441 spi_sts 504 spin-up device 591 square wave enable 471 ss_state 510 ssfc 811, 833 intel ? ich8 family datasheet 887 register bit index ssfs 810, 832 ssts 763 ssync 738 start 694 start 591 start frame pulse width 431 start/stop bus master 565, 620 statests 733 static bus master stat us policy enable 637 status 592 stme 557 strd 555 stream interrupt enable 736 stream interrupt status 737 stream number 746 stream reset 747 stream run 747 stream synchronization 738 stripe control 746 sttt1 557 sttt2 558 sub class code 411, 427, 532, 631, 651, 688, 707, 760 subordinate bus number 412, 762 subsystem id 428, 537, 607, 633, 653, 690, 709 subsystem identifier 422, 779 subsystem vendor id 428, 536, 606, 633, 652, 690, 709 subsystem vendor identifier 422, 779 subtractive decode policy 421 supports 64-bit addressing 571 supports activity led 571 supports aggressive link power management 571 supports cold presence detect 571 supports command list override (sclo) 571 supports command qu eue acceleration 571 supports interlock switch 571 supports non-zero dma offsets 571 supports port multiplier 571 supports port multiplier fis based switching 571 supports port sel ector acceleration 571 supports staggered spin-up 571 suspend 645, 679 svcap 779 svid 401, 690, 709, 779 sw_tco_smi 513 swgpe_ctrl 508 swgpe_en 501 swgpe_sts 499 swsmi_rate_sel 480 swsmi_tmr_sts 505 system error on correctable error enable 777 system error on fatal error enable 777 system error on non-fatal error enable 777 system reset 475 system reset status 478 t target component id 792 target component id (tcid) 358, 359, 360, 361, 362 target port number 792 target port number (pn) 358, 359, 360, 361, 362 task file error enable 587 task file error status 585 tco 369 tco data in value 512 tco data out value 512 tco irq select (is) 369 tco timer halt 515 tco timer initial value 517 tco timer value 511 tco_en 502 tco_int_sts 513 tco_lock 515 tco_message(n) 516 tco_sts 505 tcosci_en 500 tcosci_sts 499 tcsel 711 tctl 369 thermal interrupt status 499 thrm#_pol 508 thrm_dty 495 thrm_en 501 throttle status 494 thtl_dty 495 thtl_en 495 timeout 513 timeout/crc interrupt enable 642 timer 0 interrupt active 797 timer 1 interrupt active 797 timer 2 interrupt active 797 timer compare value 800 timer counter 2 enable 473 timer counter 2 out status 473 timer interrupt rout capability 798 timer interrupt type 799 timer n 32-bit mode 799 timer n interrupt enable 799 timer n size 799 timer n type 799 timer n value set 799 register bit index 888 intel ? ich8 family datasheet timer overflow interrupt enable 492 timer overflow status 491 timer value 494 timn 800 token_pid_cnt(7-0) 682 top swap (ts) 388 top swap status (tss) 441 traffic priority 746 training 787 training error mask 788 training error severity 789 transaction class / virtual channel map 786 transaction class / virtual channel map (tvm) 355, 356 transactions pending 718, 770 trap and smi# enable (trse) 368 trapped i/o address (tioa) 367 trapped i/o data (tiod) 367 trcr 367 trigger mode 466 twdr 367 type 535, 652 u uem 788 ues 787 uev 789 uhci #0 pin (u0p) 372 uhci #1 disable (u1d) 390 uhci #1 pin (u1p) 372 uhci #2 disable (u2d) 390 uhci #2 pin (u2p) 372 uhci #3 disable (u3d) 390 uhci #3 pin (u3p) 372 uhci #4 disable (u4d) 390 uhci v/s ehci 204 uhci_break_en 484 ulba 358, 793 uld 358, 792 unexpected completion mask 788 unexpected completion severity 789 unexpected completion status 787 unimplemented asynchronous park mode bits 669 unique clock exit latency 782 unknown fis interrupt 586 unknown fis interrupt enable 587 unlocked 481 unsupported 788, 789 unsupported request detected 718, 770 unsupported request error status 787 unsupported request reporting enable 718, 769 update cycle inhibit 471 update in progress 470 update-ended flag 472 update-ended interrupt enable 471 upper 128 byte enable (ue) 385 upper 128 byte lock (ul) 385 upper address(63-44) 675 upper base address 709 upstream read latency threshold 421 usb 636 usb ehci dynamic clock gate enable 392 usb ehci static clock gate enable 392 usb error interrupt 641, 672 usb error interrupt enable 673 usb interrupt 641, 672 usb interrupt enable 673 usb release number 657 usb uhci dynamic clock gate enable 392 usb_address_cnf 683 usb_endpoint_cnf 683 usb1_en 501 usb1_sts 499 usb2 669, 671, 673 usb2_en 501 usb2_sts 499 usb3_en 500 usb3_sts 498 usb4_en 500 usb4_sts 497 usbpid 682 use sata class code 551 user definable features 530, 602, 630, 650, 687 v v0cap 354, 785 v0ctl 355, 786 v0sts 355, 786 v1ctl 356 v1sts 356 valid ram and time bit 472 vc arbitration capability (ac) 354 vc arbitration select 785 vc arbitration select (as) 354 vc arbitration table offset 784 vc arbitration table offset (ato) 354 vc arbitration table status 785 vc arbitration table status (vas) 354 vc negotiation pending 786 vc negotiation pending (np) 355, 357 intel ? ich8 family datasheet 889 register bit index vc0cap 721 vc0ctl 721 vc0sts 721 vcap1 353 vcap2 354, 784 vccap 719 vch 353, 784 vcicap 722 vcictl 722 vcists 723 vector 467 vendor id 396, 408, 424, 5 28, 600, 629, 648, 685, 705, 757 vendor id capability 796 ver 465 version 403, 465, 545, 615, 655, 714, 780 vga 16-bit decode 417, 766 vga enable 417, 767 vga palette snoop 397, 409, 425, 529, 601, 629, 649, 686, 706, 758 vid 396, 705 virtual channel enable 786 virtual channel enable (en) 355, 356 virtual channel identifier 786 virtual channel identifier (id) 355, 356 vmaj 729 vmin 729 vs 576 vscc 816 w wait cycle control 397, 409, 425, 529, 601, 629, 649, 686, 706, 758 wake on connect enable 677 wake on disconnect enable 677 wake on overcurrent enable 677 wake status 490 wakeen 731 walclk 737 wall clock counter 737 write granularity (wg) 816 write status required (wsr) 816 write_read#_cnt 682 wrt_rdonly 663 x xcap 768 (ioad) 285 interrupt pending status port 516 el_state0_cnt 388 el_state1_cnt 388 interrupt pending status port 516 i/o address 285 i/o limit address limit bits 437 interrupt pending status port 516 gp_blink 426 , 427 gp_io_sel 424 interrupt pending status port 516 gp_lvl 425 , 430 gpio_use_sel 424 gp_io_sel2 429 upper address 614 gp_lvl 429 gpio_use_sel2 428 64 bit address capable 721 64 bit address capable (c64) 483 64b address capability 655 64-bit address supported 670 64-bit addressing capability 606 64-bit indicator 707 64-bit indicator (i64b) 439 64-bit indicator (i64l) 439 66 mhz capable 312 , 326 , 438 , 568 , 588 , 627 , 647 , 702 66mhz capable 450 , 468 , 542 address 285 register bit index 890 intel ? ich8 family datasheet |
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